338 lines
11 KiB
Diff
338 lines
11 KiB
Diff
From cba6b8cbd391d50b593c51c67955c04b3c568b6d Mon Sep 17 00:00:00 2001
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From: Karol Herbst <kherbst@redhat.com>
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Date: Thu, 16 Sep 2021 13:07:48 -0400
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Subject: [PATCH 5/6] Revert "nouveau: Use
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D"
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This reverts commit cf999b3cc3dd4e38b5a6938eb85417abfc10227d.
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---
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.../drivers/nouveau/nvc0/nvc0_miptree.c | 122 ++++++++++--------
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.../drivers/nouveau/nvc0/nvc0_resource.c | 57 ++++----
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.../drivers/nouveau/nvc0/nvc0_resource.h | 15 ---
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3 files changed, 90 insertions(+), 104 deletions(-)
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diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
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index 8260a90f0d6..88623fb31ac 100644
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--- a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
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+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
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@@ -38,14 +38,16 @@ nvc0_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz, bool is_3d)
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}
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static uint32_t
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-tu102_choose_tiled_storage_type(enum pipe_format format,
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- unsigned ms,
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- bool compressed)
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-
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+tu102_mt_choose_storage_type(struct nv50_miptree *mt, bool compressed)
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{
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uint32_t kind;
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- switch (format) {
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+ if (unlikely(mt->base.base.bind & PIPE_BIND_CURSOR))
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+ return 0;
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+ if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR))
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+ return 0;
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+
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+ switch (mt->base.base.format) {
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case PIPE_FORMAT_Z16_UNORM:
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if (compressed)
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kind = 0x0b; // NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC
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@@ -84,18 +86,19 @@ tu102_choose_tiled_storage_type(enum pipe_format format,
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return kind;
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}
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-uint32_t
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-nvc0_choose_tiled_storage_type(struct pipe_screen *pscreen,
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- enum pipe_format format,
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- unsigned ms,
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- bool compressed)
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+static uint32_t
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+nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool compressed)
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{
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+ const unsigned ms = util_logbase2(mt->base.base.nr_samples);
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+
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uint32_t tile_flags;
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- if (nouveau_screen(pscreen)->device->chipset >= 0x160)
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- return tu102_choose_tiled_storage_type(format, ms, compressed);
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+ if (unlikely(mt->base.base.bind & PIPE_BIND_CURSOR))
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+ return 0;
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+ if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR))
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+ return 0;
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- switch (format) {
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+ switch (mt->base.base.format) {
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case PIPE_FORMAT_Z16_UNORM:
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if (compressed)
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tile_flags = 0x02 + ms;
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@@ -132,7 +135,7 @@ nvc0_choose_tiled_storage_type(struct pipe_screen *pscreen,
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tile_flags = 0xc3;
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break;
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default:
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- switch (util_format_get_blocksizebits(format)) {
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+ switch (util_format_get_blocksizebits(mt->base.base.format)) {
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case 128:
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if (compressed)
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tile_flags = 0xf4 + ms * 2;
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@@ -182,21 +185,6 @@ nvc0_choose_tiled_storage_type(struct pipe_screen *pscreen,
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return tile_flags;
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}
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-static uint32_t
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-nvc0_mt_choose_storage_type(struct pipe_screen *pscreen,
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- struct nv50_miptree *mt,
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- bool compressed)
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-{
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- const unsigned ms = util_logbase2(mt->base.base.nr_samples);
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-
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- if (unlikely(mt->base.base.bind & PIPE_BIND_CURSOR))
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- return 0;
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- if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR))
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- return 0;
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-
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- return nvc0_choose_tiled_storage_type(pscreen, mt->base.base.format, ms, compressed);
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-}
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-
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static inline bool
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nvc0_miptree_init_ms_mode(struct nv50_miptree *mt)
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{
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@@ -297,34 +285,57 @@ nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt)
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}
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}
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-static uint64_t
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-nvc0_miptree_get_modifier(struct pipe_screen *pscreen, struct nv50_miptree *mt)
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+static uint64_t nvc0_miptree_get_modifier(struct nv50_miptree *mt)
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{
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- const union nouveau_bo_config *config = &mt->base.bo->config;
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- const uint32_t uc_kind =
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- nvc0_choose_tiled_storage_type(pscreen,
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- mt->base.base.format,
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- mt->base.base.nr_samples,
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- false);
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- const uint32_t kind_gen = nvc0_get_kind_generation(pscreen);
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+ union nouveau_bo_config *config = &mt->base.bo->config;
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+ uint64_t modifier;
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if (mt->layout_3d)
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return DRM_FORMAT_MOD_INVALID;
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- if (mt->base.base.nr_samples > 1)
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- return DRM_FORMAT_MOD_INVALID;
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- if (config->nvc0.memtype == 0x00)
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- return DRM_FORMAT_MOD_LINEAR;
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- if (NVC0_TILE_MODE_Y(config->nvc0.tile_mode) > 5)
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- return DRM_FORMAT_MOD_INVALID;
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- if (config->nvc0.memtype != uc_kind)
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- return DRM_FORMAT_MOD_INVALID;
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- return DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(
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- 0,
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- nouveau_screen(pscreen)->tegra_sector_layout ? 0 : 1,
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- kind_gen,
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- config->nvc0.memtype,
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- NVC0_TILE_MODE_Y(config->nvc0.tile_mode));
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+ switch (config->nvc0.memtype) {
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+ case 0x00:
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+ modifier = DRM_FORMAT_MOD_LINEAR;
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+ break;
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+
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+ case 0xfe:
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+ switch (NVC0_TILE_MODE_Y(config->nvc0.tile_mode)) {
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+ case 0:
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+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB;
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+ break;
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+
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+ case 1:
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+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB;
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+ break;
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+
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+ case 2:
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+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB;
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+ break;
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+
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+ case 3:
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+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB;
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+ break;
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+
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+ case 4:
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+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB;
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+ break;
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+
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+ case 5:
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+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB;
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+ break;
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+
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+ default:
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+ modifier = DRM_FORMAT_MOD_INVALID;
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+ break;
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+ }
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+ break;
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+
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+ default:
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+ modifier = DRM_FORMAT_MOD_INVALID;
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+ break;
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+ }
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+
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+ return modifier;
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}
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bool
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@@ -341,7 +352,7 @@ nvc0_miptree_get_handle(struct pipe_screen *pscreen,
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if (!ret)
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return ret;
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- whandle->modifier = nvc0_miptree_get_modifier(pscreen, mt);
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+ whandle->modifier = nvc0_miptree_get_modifier(mt);
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return true;
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}
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@@ -388,7 +399,10 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
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if (pt->bind & PIPE_BIND_LINEAR)
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pt->flags |= NOUVEAU_RESOURCE_FLAG_LINEAR;
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- bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(pscreen, mt, compressed);
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+ if (dev->chipset < 0x160)
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+ bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(mt, compressed);
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+ else
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+ bo_config.nvc0.memtype = tu102_mt_choose_storage_type(mt, compressed);
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if (!nvc0_miptree_init_ms_mode(mt)) {
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FREE(mt);
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diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
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index 668d2f95a54..a4482854196 100644
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--- a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
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+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
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@@ -32,6 +32,16 @@ nvc0_resource_create_with_modifiers(struct pipe_screen *screen,
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}
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}
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+static const uint64_t nvc0_supported_modifiers[] = {
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+ DRM_FORMAT_MOD_LINEAR,
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+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB,
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+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB,
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+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB,
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+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB,
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+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB,
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+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB,
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+};
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+
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static void
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nvc0_resource_destroy(struct pipe_screen *pscreen, struct pipe_resource *res)
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{
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@@ -47,37 +57,26 @@ nvc0_query_dmabuf_modifiers(struct pipe_screen *screen,
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uint64_t *modifiers, unsigned int *external_only,
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int *count)
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{
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- const int s = nouveau_screen(screen)->tegra_sector_layout ? 0 : 1;
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- const uint32_t uc_kind =
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- nvc0_choose_tiled_storage_type(screen, format, 0, false);
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- const uint32_t num_uc = uc_kind ? 6 : 0; /* max block height = 32 GOBs */
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- const int num_supported = num_uc + 1; /* LINEAR is always supported */
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- const uint32_t kind_gen = nvc0_get_kind_generation(screen);
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int i, num = 0;
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- if (max > num_supported)
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- max = num_supported;
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+ if (max > ARRAY_SIZE(nvc0_supported_modifiers))
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+ max = ARRAY_SIZE(nvc0_supported_modifiers);
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if (!max) {
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- max = num_supported;
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+ max = ARRAY_SIZE(nvc0_supported_modifiers);
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external_only = NULL;
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modifiers = NULL;
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}
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-#define NVC0_ADD_MOD(m) do { \
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- if (modifiers) modifiers[num] = m; \
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- if (external_only) external_only[num] = 0; \
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- num++; \
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-} while (0)
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-
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- for (i = 0; i < max && i < num_uc; i++)
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- NVC0_ADD_MOD(DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, s, kind_gen,
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- uc_kind, 5 - i));
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+ for (i = 0; i < max; i++) {
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+ if (modifiers)
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+ modifiers[num] = nvc0_supported_modifiers[i];
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- if (i < max)
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- NVC0_ADD_MOD(DRM_FORMAT_MOD_LINEAR);
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+ if (external_only)
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+ external_only[num] = 0;
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-#undef NVC0_ADD_MOD
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+ num++;
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+ }
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*count = num;
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}
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@@ -87,22 +86,10 @@ nvc0_is_dmabuf_modifier_supported(struct pipe_screen *screen,
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uint64_t modifier, enum pipe_format format,
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bool *external_only)
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{
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- const int s = nouveau_screen(screen)->tegra_sector_layout ? 0 : 1;
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- const uint32_t uc_kind =
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- nvc0_choose_tiled_storage_type(screen, format, 0, false);
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- const uint32_t num_uc = uc_kind ? 6 : 0; /* max block height = 32 GOBs */
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- const uint32_t kind_gen = nvc0_get_kind_generation(screen);
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int i;
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- if (modifier == DRM_FORMAT_MOD_LINEAR) {
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- if (external_only)
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- *external_only = false;
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-
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- return true;
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- }
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-
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- for (i = 0; i < num_uc; i++) {
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- if (DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, s, kind_gen, uc_kind, i) == modifier) {
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+ for (i = 0; i < ARRAY_SIZE(nvc0_supported_modifiers); i++) {
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+ if (nvc0_supported_modifiers[i] == modifier) {
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if (external_only)
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*external_only = false;
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diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h
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index a281d427c94..7573d372985 100644
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--- a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h
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+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h
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@@ -3,7 +3,6 @@
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#define __NVC0_RESOURCE_H__
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#include "nv50/nv50_resource.h"
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-#include "nouveau_screen.h"
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#define NVC0_RESOURCE_FLAG_VIDEO (NOUVEAU_RESOURCE_FLAG_DRV_PRIV << 0)
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@@ -25,14 +24,6 @@
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#define NVC0_TILE_SIZE(m) ((64 * 8) << (((m) + ((m) >> 4) + ((m) >> 8)) & 0xf))
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-static inline uint32_t
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-nvc0_get_kind_generation(struct pipe_screen *pscreen)
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-{
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- if (nouveau_screen(pscreen)->device->chipset >= 0x160)
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- return 2;
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- else
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- return 0;
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-}
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void
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nvc0_init_resource_functions(struct pipe_context *pcontext);
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@@ -42,12 +33,6 @@ nvc0_screen_init_resource_functions(struct pipe_screen *pscreen);
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/* Internal functions:
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*/
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-uint32_t
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-nvc0_choose_tiled_storage_type(struct pipe_screen *pscreen,
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- enum pipe_format format,
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- unsigned ms,
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- bool compressed);
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-
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struct pipe_resource *
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nvc0_miptree_create(struct pipe_screen *pscreen,
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const struct pipe_resource *tmp,
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--
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2.31.1
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