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This commit is contained in:
Adam Williamson 2021-10-12 11:54:46 -07:00
parent fbd143696e
commit d11d1f44a5
6 changed files with 784 additions and 0 deletions
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96
0001-tegra-Use-private-reference-count-for-sampler-views.patch Normal file
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@ -0,0 +1,96 @@
From f308e4cd8c50c9bad725a6d4ccbc574b76912929 Mon Sep 17 00:00:00 2001
From: Thierry Reding <treding@nvidia.com>
Date: Wed, 6 Oct 2021 22:42:36 +0200
Subject: [PATCH 1/6] tegra: Use private reference count for sampler views
With the recent addition of the shortcuts aiming to avoid atomic
operations, the reference count on sampler views can become unbalanced
in the Tegra driver since they are wrapped and then proxied to the
Nouveau driver.
Fix this by keeping a private reference count.
Fixes: ef5d42741327 ("st/mesa: add a mechanism to bypass atomics when binding sampler views")
Tested-by: Karol Herbst <kherbst@redhat.com>
---
src/gallium/drivers/tegra/tegra_context.c | 30 ++++++++++++++++++-----
src/gallium/drivers/tegra/tegra_context.h | 1 +
2 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/tegra/tegra_context.c b/src/gallium/drivers/tegra/tegra_context.c
index b7dc73bb1be..fe88478a22a 100644
--- a/src/gallium/drivers/tegra/tegra_context.c
+++ b/src/gallium/drivers/tegra/tegra_context.c
@@ -566,10 +566,22 @@ tegra_set_sampler_views(struct pipe_context *pcontext, unsigned shader,
{
struct pipe_sampler_view *views[PIPE_MAX_SHADER_SAMPLER_VIEWS];
struct tegra_context *context = to_tegra_context(pcontext);
+ struct tegra_sampler_view *view;
unsigned i;
- for (i = 0; i < num_views; i++)
+ for (i = 0; i < num_views; i++) {
+ /* adjust private reference count */
+ view = to_tegra_sampler_view(pviews[i]);
+ if (view) {
+ view->refcount--;
+ if (!view->refcount) {
+ view->refcount = 100000000;
+ p_atomic_add(&view->gpu->reference.count, view->refcount);
+ }
+ }
+
views[i] = tegra_sampler_view_unwrap(pviews[i]);
+ }
context->gpu->set_sampler_views(context->gpu, shader, start_slot,
num_views, unbind_num_trailing_slots,
@@ -835,15 +847,19 @@ tegra_create_sampler_view(struct pipe_context *pcontext,
if (!view)
return NULL;
- view->gpu = context->gpu->create_sampler_view(context->gpu, resource->gpu,
- template);
- memcpy(&view->base, view->gpu, sizeof(*view->gpu));
+ view->base = *template;
+ view->base.context = pcontext;
/* overwrite to prevent reference from being released */
view->base.texture = NULL;
-
pipe_reference_init(&view->base.reference, 1);
pipe_resource_reference(&view->base.texture, presource);
- view->base.context = pcontext;
+
+ view->gpu = context->gpu->create_sampler_view(context->gpu, resource->gpu,
+ template);
+
+ /* use private reference count */
+ view->gpu->reference.count += 100000000;
+ view->refcount = 100000000;
return &view->base;
}
@@ -855,6 +871,8 @@ tegra_sampler_view_destroy(struct pipe_context *pcontext,
struct tegra_sampler_view *view = to_tegra_sampler_view(pview);
pipe_resource_reference(&view->base.texture, NULL);
+ /* adjust private reference count */
+ p_atomic_add(&view->gpu->reference.count, -view->refcount);
pipe_sampler_view_reference(&view->gpu, NULL);
free(view);
}
diff --git a/src/gallium/drivers/tegra/tegra_context.h b/src/gallium/drivers/tegra/tegra_context.h
index 4869b0913a6..c2d8eb33ca5 100644
--- a/src/gallium/drivers/tegra/tegra_context.h
+++ b/src/gallium/drivers/tegra/tegra_context.h
@@ -47,6 +47,7 @@ tegra_screen_context_create(struct pipe_screen *pscreen, void *priv,
struct tegra_sampler_view {
struct pipe_sampler_view base;
struct pipe_sampler_view *gpu;
+ unsigned int refcount;
};
static inline struct tegra_sampler_view *
--
2.31.1

58
0002-tegra-Use-private-reference-count-for-resources.patch Normal file
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@ -0,0 +1,58 @@
From 6e786d9e657dc3a0cb659dbf68a11fe75e554d8f Mon Sep 17 00:00:00 2001
From: Thierry Reding <treding@nvidia.com>
Date: Wed, 6 Oct 2021 22:47:17 +0200
Subject: [PATCH 2/6] tegra: Use private reference count for resources
With the recent addition of the shortcuts aiming to avoid atomic
operations, the reference count on resources can become unbalanced
in the Tegra driver since they are wrapped and then proxied to the
Nouveau driver.
Fix this by keeping a private reference count.
Fixes: 7688b8ae9802 ("st/mesa: eliminate all atomic ops when setting vertex buffers")
Tested-by: Karol Herbst <kherbst@redhat.com>
---
src/gallium/drivers/tegra/tegra_resource.h | 1 +
src/gallium/drivers/tegra/tegra_screen.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/src/gallium/drivers/tegra/tegra_resource.h b/src/gallium/drivers/tegra/tegra_resource.h
index 67507d64590..892afaf5e0f 100644
--- a/src/gallium/drivers/tegra/tegra_resource.h
+++ b/src/gallium/drivers/tegra/tegra_resource.h
@@ -31,6 +31,7 @@ struct winsys_handle;
struct tegra_resource {
struct pipe_resource base;
struct pipe_resource *gpu;
+ unsigned int refcount;
uint64_t modifier;
uint32_t stride;
diff --git a/src/gallium/drivers/tegra/tegra_screen.c b/src/gallium/drivers/tegra/tegra_screen.c
index 2b108b07908..3c4c36e0c94 100644
--- a/src/gallium/drivers/tegra/tegra_screen.c
+++ b/src/gallium/drivers/tegra/tegra_screen.c
@@ -245,6 +245,10 @@ tegra_screen_resource_create(struct pipe_screen *pscreen,
pipe_reference_init(&resource->base.reference, 1);
resource->base.screen = &screen->base;
+ /* use private reference count for wrapped resources */
+ resource->gpu->reference.count += 100000000;
+ resource->refcount = 100000000;
+
return &resource->base;
destroy:
@@ -352,6 +356,8 @@ tegra_screen_resource_destroy(struct pipe_screen *pscreen,
{
struct tegra_resource *resource = to_tegra_resource(presource);
+ /* adjust private reference count */
+ p_atomic_add(&resource->gpu->reference.count, -resource->refcount);
pipe_resource_reference(&resource->gpu, NULL);
free(resource);
}
--
2.31.1

212
0003-Revert-nouveau-Use-format-modifiers-in-buffer-alloca.patch Normal file
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@ -0,0 +1,212 @@
From 7c19437292c0da14bda555b3f55875eb8c0b2ed2 Mon Sep 17 00:00:00 2001
From: Karol Herbst <kherbst@redhat.com>
Date: Thu, 16 Sep 2021 13:07:31 -0400
Subject: [PATCH 3/6] Revert "nouveau: Use format modifiers in buffer
allocation"
This reverts commit 129d83cac2accc4a66eae50c19ac245b864dc98c.
---
.../drivers/nouveau/nvc0/nvc0_miptree.c | 125 ++----------------
1 file changed, 8 insertions(+), 117 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
index e0a9d48249f..8260a90f0d6 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
@@ -184,7 +184,7 @@ nvc0_choose_tiled_storage_type(struct pipe_screen *pscreen,
static uint32_t
nvc0_mt_choose_storage_type(struct pipe_screen *pscreen,
- const struct nv50_miptree *mt,
+ struct nv50_miptree *mt,
bool compressed)
{
const unsigned ms = util_logbase2(mt->base.base.nr_samples);
@@ -249,7 +249,7 @@ nvc0_miptree_init_layout_video(struct nv50_miptree *mt)
}
static void
-nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt, uint64_t modifier)
+nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt)
{
struct pipe_resource *pt = &mt->base.base;
unsigned w, h, d, l;
@@ -266,9 +266,6 @@ nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt, uint64_t modifier)
d = mt->layout_3d ? pt->depth0 : 1;
assert(!mt->ms_mode || !pt->last_level);
- assert(modifier == DRM_FORMAT_MOD_INVALID ||
- (!pt->last_level && !mt->layout_3d));
- assert(modifier != DRM_FORMAT_MOD_LINEAR);
for (l = 0; l <= pt->last_level; ++l) {
struct nv50_miptree_level *lvl = &mt->level[l];
@@ -278,16 +275,7 @@ nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt, uint64_t modifier)
lvl->offset = mt->total_size;
- if (modifier != DRM_FORMAT_MOD_INVALID)
- /* Extract the log2(block height) field from the modifier and pack it
- * into tile_mode's y field. Other tile dimensions are always 1
- * (represented using 0 here) for 2D surfaces, and non-2D surfaces are
- * not supported by the current modifiers (asserted above). Note the
- * modifier must be validated prior to calling this function.
- */
- lvl->tile_mode = ((uint32_t)modifier & 0xf) << 4;
- else
- lvl->tile_mode = nvc0_tex_choose_tile_dims(nbx, nby, d, mt->layout_3d);
+ lvl->tile_mode = nvc0_tex_choose_tile_dims(nbx, nby, d, mt->layout_3d);
tsx = NVC0_TILE_SIZE_X(lvl->tile_mode); /* x is tile row pitch in bytes */
tsy = NVC0_TILE_SIZE_Y(lvl->tile_mode);
@@ -358,84 +346,6 @@ nvc0_miptree_get_handle(struct pipe_screen *pscreen,
return true;
}
-static uint64_t
-nvc0_miptree_select_best_modifier(struct pipe_screen *pscreen,
- const struct nv50_miptree *mt,
- const uint64_t *modifiers,
- unsigned int count)
-{
- /*
- * Supported block heights are 1,2,4,8,16,32, stored as log2() their
- * value. Reserve one slot for each, as well as the linear modifier.
- */
- uint64_t prio_supported_mods[] = {
- DRM_FORMAT_MOD_INVALID,
- DRM_FORMAT_MOD_INVALID,
- DRM_FORMAT_MOD_INVALID,
- DRM_FORMAT_MOD_INVALID,
- DRM_FORMAT_MOD_INVALID,
- DRM_FORMAT_MOD_INVALID,
- DRM_FORMAT_MOD_LINEAR,
- };
- const uint32_t uc_kind = nvc0_mt_choose_storage_type(pscreen, mt, false);
- int top_mod_slot = ARRAY_SIZE(prio_supported_mods);
- const uint32_t kind_gen = nvc0_get_kind_generation(pscreen);
- unsigned int i;
- int p;
-
- if (uc_kind != 0u) {
- const struct pipe_resource *pt = &mt->base.base;
- const unsigned nbx = util_format_get_nblocksx(pt->format, pt->width0);
- const unsigned nby = util_format_get_nblocksy(pt->format, pt->height0);
- const uint32_t lbh_preferred =
- NVC0_TILE_MODE_Y(nvc0_tex_choose_tile_dims(nbx, nby, 1u, false));
- uint32_t lbh = lbh_preferred;
- bool dec_lbh = true;
- const uint8_t s = nouveau_screen(pscreen)->tegra_sector_layout ? 0 : 1;
-
- for (i = 0; i < ARRAY_SIZE(prio_supported_mods) - 1; i++) {
- assert(lbh <= 5u);
- prio_supported_mods[i] =
- DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, s, kind_gen, uc_kind, lbh);
-
- /*
- * The preferred block height is the largest block size that doesn't
- * waste excessive space with unused padding bytes relative to the
- * height of the image. Construct the priority array such that
- * the preferred block height is highest priority, followed by
- * progressively smaller block sizes down to a block height of one,
- * followed by progressively larger (more wasteful) block sizes up
- * to 5.
- */
- if (lbh == 0u) {
- lbh = lbh_preferred + 1u;
- dec_lbh = false;
- } else if (dec_lbh) {
- lbh--;
- } else {
- lbh++;
- }
- }
- }
-
- assert(prio_supported_mods[ARRAY_SIZE(prio_supported_mods) - 1] ==
- DRM_FORMAT_MOD_LINEAR);
-
- for (i = 0u; i < count; i++) {
- for (p = 0; p < ARRAY_SIZE(prio_supported_mods); p++) {
- if (prio_supported_mods[p] == modifiers[i]) {
- if (top_mod_slot > p) top_mod_slot = p;
- break;
- }
- }
- }
-
- if (top_mod_slot >= ARRAY_SIZE(prio_supported_mods))
- return DRM_FORMAT_MOD_INVALID;
-
- return prio_supported_mods[top_mod_slot];
-}
-
struct pipe_resource *
nvc0_miptree_create(struct pipe_screen *pscreen,
const struct pipe_resource *templ,
@@ -450,7 +360,6 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
union nouveau_bo_config bo_config;
uint32_t bo_flags;
unsigned pitch_align;
- uint64_t modifier = DRM_FORMAT_MOD_INVALID;
if (!mt)
return NULL;
@@ -460,9 +369,6 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
pt->screen = pscreen;
if (pt->usage == PIPE_USAGE_STAGING) {
- /* PIPE_USAGE_STAGING, and usage in general, should not be specified when
- * modifiers are used. */
- assert(count == 0);
switch (pt->target) {
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_RECT:
@@ -476,27 +382,13 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
}
}
- if (pt->bind & PIPE_BIND_LINEAR)
+ if (count == 1 && modifiers[0] == DRM_FORMAT_MOD_LINEAR)
pt->flags |= NOUVEAU_RESOURCE_FLAG_LINEAR;
- if (count > 0) {
- modifier = nvc0_miptree_select_best_modifier(pscreen, mt,
- modifiers, count);
-
- if (modifier == DRM_FORMAT_MOD_INVALID) {
- FREE(mt);
- return NULL;
- }
+ if (pt->bind & PIPE_BIND_LINEAR)
+ pt->flags |= NOUVEAU_RESOURCE_FLAG_LINEAR;
- if (modifier == DRM_FORMAT_MOD_LINEAR) {
- pt->flags |= NOUVEAU_RESOURCE_FLAG_LINEAR;
- bo_config.nvc0.memtype = 0;
- } else {
- bo_config.nvc0.memtype = (modifier >> 12) & 0xff;
- }
- } else {
- bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(pscreen, mt, compressed);
- }
+ bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(pscreen, mt, compressed);
if (!nvc0_miptree_init_ms_mode(mt)) {
FREE(mt);
@@ -504,11 +396,10 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
}
if (unlikely(pt->flags & NVC0_RESOURCE_FLAG_VIDEO)) {
- assert(modifier == DRM_FORMAT_MOD_INVALID);
nvc0_miptree_init_layout_video(mt);
} else
if (likely(bo_config.nvc0.memtype)) {
- nvc0_miptree_init_layout_tiled(mt, modifier);
+ nvc0_miptree_init_layout_tiled(mt);
} else {
/* When modifiers are supplied, usage is zero. TODO: detect the
* modifiers+cursor case. */
--
2.31.1

32
0004-Revert-nouveau-no-modifier-the-invalid-modifier.patch Normal file
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@ -0,0 +1,32 @@
From 140e7c3de1928f65dc04b9c9a22a705890784f86 Mon Sep 17 00:00:00 2001
From: Karol Herbst <kherbst@redhat.com>
Date: Thu, 16 Sep 2021 13:07:42 -0400
Subject: [PATCH 4/6] Revert "nouveau: no modifier != the invalid modifier"
This reverts commit df451091ac96c09d726379384fa14dea5db2d5b5.
---
src/gallium/drivers/nouveau/nvc0/nvc0_resource.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
index afe8dd7d429..668d2f95a54 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
@@ -9,11 +9,13 @@ static struct pipe_resource *
nvc0_resource_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
+ const uint64_t modifier = DRM_FORMAT_MOD_INVALID;
+
switch (templ->target) {
case PIPE_BUFFER:
return nouveau_buffer_create(screen, templ);
default:
- return nvc0_miptree_create(screen, templ, NULL, 0);
+ return nvc0_miptree_create(screen, templ, &modifier, 1);
}
}
--
2.31.1

337
0005-Revert-nouveau-Use-DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEA.patch Normal file
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@ -0,0 +1,337 @@
From cba6b8cbd391d50b593c51c67955c04b3c568b6d Mon Sep 17 00:00:00 2001
From: Karol Herbst <kherbst@redhat.com>
Date: Thu, 16 Sep 2021 13:07:48 -0400
Subject: [PATCH 5/6] Revert "nouveau: Use
DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D"
This reverts commit cf999b3cc3dd4e38b5a6938eb85417abfc10227d.
---
.../drivers/nouveau/nvc0/nvc0_miptree.c | 122 ++++++++++--------
.../drivers/nouveau/nvc0/nvc0_resource.c | 57 ++++----
.../drivers/nouveau/nvc0/nvc0_resource.h | 15 ---
3 files changed, 90 insertions(+), 104 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
index 8260a90f0d6..88623fb31ac 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
@@ -38,14 +38,16 @@ nvc0_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz, bool is_3d)
}
static uint32_t
-tu102_choose_tiled_storage_type(enum pipe_format format,
- unsigned ms,
- bool compressed)
-
+tu102_mt_choose_storage_type(struct nv50_miptree *mt, bool compressed)
{
uint32_t kind;
- switch (format) {
+ if (unlikely(mt->base.base.bind & PIPE_BIND_CURSOR))
+ return 0;
+ if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR))
+ return 0;
+
+ switch (mt->base.base.format) {
case PIPE_FORMAT_Z16_UNORM:
if (compressed)
kind = 0x0b; // NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC
@@ -84,18 +86,19 @@ tu102_choose_tiled_storage_type(enum pipe_format format,
return kind;
}
-uint32_t
-nvc0_choose_tiled_storage_type(struct pipe_screen *pscreen,
- enum pipe_format format,
- unsigned ms,
- bool compressed)
+static uint32_t
+nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool compressed)
{
+ const unsigned ms = util_logbase2(mt->base.base.nr_samples);
+
uint32_t tile_flags;
- if (nouveau_screen(pscreen)->device->chipset >= 0x160)
- return tu102_choose_tiled_storage_type(format, ms, compressed);
+ if (unlikely(mt->base.base.bind & PIPE_BIND_CURSOR))
+ return 0;
+ if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR))
+ return 0;
- switch (format) {
+ switch (mt->base.base.format) {
case PIPE_FORMAT_Z16_UNORM:
if (compressed)
tile_flags = 0x02 + ms;
@@ -132,7 +135,7 @@ nvc0_choose_tiled_storage_type(struct pipe_screen *pscreen,
tile_flags = 0xc3;
break;
default:
- switch (util_format_get_blocksizebits(format)) {
+ switch (util_format_get_blocksizebits(mt->base.base.format)) {
case 128:
if (compressed)
tile_flags = 0xf4 + ms * 2;
@@ -182,21 +185,6 @@ nvc0_choose_tiled_storage_type(struct pipe_screen *pscreen,
return tile_flags;
}
-static uint32_t
-nvc0_mt_choose_storage_type(struct pipe_screen *pscreen,
- struct nv50_miptree *mt,
- bool compressed)
-{
- const unsigned ms = util_logbase2(mt->base.base.nr_samples);
-
- if (unlikely(mt->base.base.bind & PIPE_BIND_CURSOR))
- return 0;
- if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR))
- return 0;
-
- return nvc0_choose_tiled_storage_type(pscreen, mt->base.base.format, ms, compressed);
-}
-
static inline bool
nvc0_miptree_init_ms_mode(struct nv50_miptree *mt)
{
@@ -297,34 +285,57 @@ nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt)
}
}
-static uint64_t
-nvc0_miptree_get_modifier(struct pipe_screen *pscreen, struct nv50_miptree *mt)
+static uint64_t nvc0_miptree_get_modifier(struct nv50_miptree *mt)
{
- const union nouveau_bo_config *config = &mt->base.bo->config;
- const uint32_t uc_kind =
- nvc0_choose_tiled_storage_type(pscreen,
- mt->base.base.format,
- mt->base.base.nr_samples,
- false);
- const uint32_t kind_gen = nvc0_get_kind_generation(pscreen);
+ union nouveau_bo_config *config = &mt->base.bo->config;
+ uint64_t modifier;
if (mt->layout_3d)
return DRM_FORMAT_MOD_INVALID;
- if (mt->base.base.nr_samples > 1)
- return DRM_FORMAT_MOD_INVALID;
- if (config->nvc0.memtype == 0x00)
- return DRM_FORMAT_MOD_LINEAR;
- if (NVC0_TILE_MODE_Y(config->nvc0.tile_mode) > 5)
- return DRM_FORMAT_MOD_INVALID;
- if (config->nvc0.memtype != uc_kind)
- return DRM_FORMAT_MOD_INVALID;
- return DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(
- 0,
- nouveau_screen(pscreen)->tegra_sector_layout ? 0 : 1,
- kind_gen,
- config->nvc0.memtype,
- NVC0_TILE_MODE_Y(config->nvc0.tile_mode));
+ switch (config->nvc0.memtype) {
+ case 0x00:
+ modifier = DRM_FORMAT_MOD_LINEAR;
+ break;
+
+ case 0xfe:
+ switch (NVC0_TILE_MODE_Y(config->nvc0.tile_mode)) {
+ case 0:
+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB;
+ break;
+
+ case 1:
+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB;
+ break;
+
+ case 2:
+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB;
+ break;
+
+ case 3:
+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB;
+ break;
+
+ case 4:
+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB;
+ break;
+
+ case 5:
+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB;
+ break;
+
+ default:
+ modifier = DRM_FORMAT_MOD_INVALID;
+ break;
+ }
+ break;
+
+ default:
+ modifier = DRM_FORMAT_MOD_INVALID;
+ break;
+ }
+
+ return modifier;
}
bool
@@ -341,7 +352,7 @@ nvc0_miptree_get_handle(struct pipe_screen *pscreen,
if (!ret)
return ret;
- whandle->modifier = nvc0_miptree_get_modifier(pscreen, mt);
+ whandle->modifier = nvc0_miptree_get_modifier(mt);
return true;
}
@@ -388,7 +399,10 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
if (pt->bind & PIPE_BIND_LINEAR)
pt->flags |= NOUVEAU_RESOURCE_FLAG_LINEAR;
- bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(pscreen, mt, compressed);
+ if (dev->chipset < 0x160)
+ bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(mt, compressed);
+ else
+ bo_config.nvc0.memtype = tu102_mt_choose_storage_type(mt, compressed);
if (!nvc0_miptree_init_ms_mode(mt)) {
FREE(mt);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
index 668d2f95a54..a4482854196 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
@@ -32,6 +32,16 @@ nvc0_resource_create_with_modifiers(struct pipe_screen *screen,
}
}
+static const uint64_t nvc0_supported_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB,
+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB,
+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB,
+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB,
+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB,
+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB,
+};
+
static void
nvc0_resource_destroy(struct pipe_screen *pscreen, struct pipe_resource *res)
{
@@ -47,37 +57,26 @@ nvc0_query_dmabuf_modifiers(struct pipe_screen *screen,
uint64_t *modifiers, unsigned int *external_only,
int *count)
{
- const int s = nouveau_screen(screen)->tegra_sector_layout ? 0 : 1;
- const uint32_t uc_kind =
- nvc0_choose_tiled_storage_type(screen, format, 0, false);
- const uint32_t num_uc = uc_kind ? 6 : 0; /* max block height = 32 GOBs */
- const int num_supported = num_uc + 1; /* LINEAR is always supported */
- const uint32_t kind_gen = nvc0_get_kind_generation(screen);
int i, num = 0;
- if (max > num_supported)
- max = num_supported;
+ if (max > ARRAY_SIZE(nvc0_supported_modifiers))
+ max = ARRAY_SIZE(nvc0_supported_modifiers);
if (!max) {
- max = num_supported;
+ max = ARRAY_SIZE(nvc0_supported_modifiers);
external_only = NULL;
modifiers = NULL;
}
-#define NVC0_ADD_MOD(m) do { \
- if (modifiers) modifiers[num] = m; \
- if (external_only) external_only[num] = 0; \
- num++; \
-} while (0)
-
- for (i = 0; i < max && i < num_uc; i++)
- NVC0_ADD_MOD(DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, s, kind_gen,
- uc_kind, 5 - i));
+ for (i = 0; i < max; i++) {
+ if (modifiers)
+ modifiers[num] = nvc0_supported_modifiers[i];
- if (i < max)
- NVC0_ADD_MOD(DRM_FORMAT_MOD_LINEAR);
+ if (external_only)
+ external_only[num] = 0;
-#undef NVC0_ADD_MOD
+ num++;
+ }
*count = num;
}
@@ -87,22 +86,10 @@ nvc0_is_dmabuf_modifier_supported(struct pipe_screen *screen,
uint64_t modifier, enum pipe_format format,
bool *external_only)
{
- const int s = nouveau_screen(screen)->tegra_sector_layout ? 0 : 1;
- const uint32_t uc_kind =
- nvc0_choose_tiled_storage_type(screen, format, 0, false);
- const uint32_t num_uc = uc_kind ? 6 : 0; /* max block height = 32 GOBs */
- const uint32_t kind_gen = nvc0_get_kind_generation(screen);
int i;
- if (modifier == DRM_FORMAT_MOD_LINEAR) {
- if (external_only)
- *external_only = false;
-
- return true;
- }
-
- for (i = 0; i < num_uc; i++) {
- if (DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, s, kind_gen, uc_kind, i) == modifier) {
+ for (i = 0; i < ARRAY_SIZE(nvc0_supported_modifiers); i++) {
+ if (nvc0_supported_modifiers[i] == modifier) {
if (external_only)
*external_only = false;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h
index a281d427c94..7573d372985 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h
@@ -3,7 +3,6 @@
#define __NVC0_RESOURCE_H__
#include "nv50/nv50_resource.h"
-#include "nouveau_screen.h"
#define NVC0_RESOURCE_FLAG_VIDEO (NOUVEAU_RESOURCE_FLAG_DRV_PRIV << 0)
@@ -25,14 +24,6 @@
#define NVC0_TILE_SIZE(m) ((64 * 8) << (((m) + ((m) >> 4) + ((m) >> 8)) & 0xf))
-static inline uint32_t
-nvc0_get_kind_generation(struct pipe_screen *pscreen)
-{
- if (nouveau_screen(pscreen)->device->chipset >= 0x160)
- return 2;
- else
- return 0;
-}
void
nvc0_init_resource_functions(struct pipe_context *pcontext);
@@ -42,12 +33,6 @@ nvc0_screen_init_resource_functions(struct pipe_screen *pscreen);
/* Internal functions:
*/
-uint32_t
-nvc0_choose_tiled_storage_type(struct pipe_screen *pscreen,
- enum pipe_format format,
- unsigned ms,
- bool compressed);
-
struct pipe_resource *
nvc0_miptree_create(struct pipe_screen *pscreen,
const struct pipe_resource *tmp,
--
2.31.1

49
0006-Revert-nouveau-Stash-supported-sector-layout-in-scre.patch Normal file
View File

@ -0,0 +1,49 @@
From 8339af08627104557ecd69e0e23396f2caed2050 Mon Sep 17 00:00:00 2001
From: Karol Herbst <kherbst@redhat.com>
Date: Thu, 16 Sep 2021 13:07:55 -0400
Subject: [PATCH 6/6] Revert "nouveau: Stash supported sector layout in screen"
This reverts commit ff534e1b5066f1c8e7969f99f40ec080eee1b907.
---
src/gallium/drivers/nouveau/nouveau_screen.c | 12 ------------
src/gallium/drivers/nouveau/nouveau_screen.h | 1 -
2 files changed, 13 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c b/src/gallium/drivers/nouveau/nouveau_screen.c
index 192044c7fb4..5c5253097b1 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.c
+++ b/src/gallium/drivers/nouveau/nouveau_screen.c
@@ -272,18 +272,6 @@ nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev)
} while ((start + screen->svm_cutout_size) < BITFIELD64_MASK(limit_bit));
}
- switch (dev->chipset) {
- case 0x0ea: /* TK1, GK20A */
- case 0x12b: /* TX1, GM20B */
- case 0x13b: /* TX2, GP10B */
- screen->tegra_sector_layout = true;
- break;
- default:
- /* Xavier's GPU and everything else */
- screen->tegra_sector_layout = false;
- break;
- }
-
/*
* Set default VRAM domain if not overridden
*/
diff --git a/src/gallium/drivers/nouveau/nouveau_screen.h b/src/gallium/drivers/nouveau/nouveau_screen.h
index 9460152eff1..58bdaa2065f 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.h
+++ b/src/gallium/drivers/nouveau/nouveau_screen.h
@@ -60,7 +60,6 @@ struct nouveau_screen {
int64_t cpu_gpu_time_delta;
bool hint_buf_keep_sysmem_copy;
- bool tegra_sector_layout;
unsigned vram_domain;
--
2.31.1