101 lines
3.7 KiB
Diff
101 lines
3.7 KiB
Diff
From a9dbe40fc10cea2efe6e1ff9e03c62dd7579c5ba Mon Sep 17 00:00:00 2001
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From: David Woodhouse <dwmw2@infradead.org>
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Date: Wed, 21 Nov 2012 10:27:19 +0000
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Subject: [PATCH] 8139cp: set ring address after enabling C+ mode
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This fixes (for me) a regression introduced by commit b01af457 ("8139cp:
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set ring address before enabling receiver"). That commit configured the
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descriptor ring addresses earlier in the initialisation sequence, in
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order to avoid the possibility of triggering stray DMA before the
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correct address had been set up.
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Unfortunately, it seems that the hardware will scribble garbage into the
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TxRingAddr registers when we enable "plus mode" Tx in the CpCmd
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register. Observed on a Traverse Geos router board.
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To deal with this, while not reintroducing the problem which led to the
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original commit, we augment cp_start_hw() to write to the CpCmd register
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*first*, then set the descriptor ring addresses, and then finally to
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enable Rx and Tx in the original 8139 Cmd register. The datasheet
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actually indicates that we should enable Tx/Rx in the Cmd register
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*before* configuring the descriptor addresses, but that would appear to
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re-introduce the problem that the offending commit b01af457 was trying
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to solve. And this variant appears to work fine on real hardware.
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Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Cc: stable@kernel.org [3.5+]
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/realtek/8139cp.c | 40 +++++++++++++++++++++++----------
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1 files changed, 28 insertions(+), 12 deletions(-)
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diff --git a/drivers/net/ethernet/realtek/8139cp.c b/drivers/net/ethernet/realtek/8139cp.c
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index 1c81825..5166d94 100644
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--- a/drivers/net/ethernet/realtek/8139cp.c
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+++ b/drivers/net/ethernet/realtek/8139cp.c
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@@ -957,7 +957,35 @@ static void cp_reset_hw (struct cp_private *cp)
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static inline void cp_start_hw (struct cp_private *cp)
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{
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+ dma_addr_t ring_dma;
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+
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cpw16(CpCmd, cp->cpcmd);
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+
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+ /*
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+ * These (at least TxRingAddr) need to be configured after the
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+ * corresponding bits in CpCmd are enabled. Datasheet v1.6 §6.33
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+ * (C+ Command Register) recommends that these and more be configured
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+ * *after* the [RT]xEnable bits in CpCmd are set. And on some hardware
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+ * it's been observed that the TxRingAddr is actually reset to garbage
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+ * when C+ mode Tx is enabled in CpCmd.
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+ */
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+ cpw32_f(HiTxRingAddr, 0);
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+ cpw32_f(HiTxRingAddr + 4, 0);
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+
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+ ring_dma = cp->ring_dma;
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+ cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
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+ cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
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+
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+ ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
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+ cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
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+ cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
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+
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+ /*
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+ * Strictly speaking, the datasheet says this should be enabled
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+ * *before* setting the descriptor addresses. But what, then, would
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+ * prevent it from doing DMA to random unconfigured addresses?
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+ * This variant appears to work fine.
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+ */
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cpw8(Cmd, RxOn | TxOn);
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}
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@@ -969,7 +997,6 @@ static void cp_enable_irq(struct cp_private *cp)
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static void cp_init_hw (struct cp_private *cp)
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{
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struct net_device *dev = cp->dev;
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- dma_addr_t ring_dma;
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cp_reset_hw(cp);
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@@ -979,17 +1006,6 @@ static void cp_init_hw (struct cp_private *cp)
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cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
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cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
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- cpw32_f(HiTxRingAddr, 0);
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- cpw32_f(HiTxRingAddr + 4, 0);
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-
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- ring_dma = cp->ring_dma;
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- cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
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- cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
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-
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- ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
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- cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
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- cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
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-
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cp_start_hw(cp);
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cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
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--
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1.7.6.5
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