44 lines
1.6 KiB
Diff
44 lines
1.6 KiB
Diff
From fdb41f0b6fa42a692e5fa39da3801f6ca18e8a6b Mon Sep 17 00:00:00 2001
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From: Jiri Bohac <jbohac@suse.cz>
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Date: Mon, 25 Jan 2021 22:44:50 +0100
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Subject: [PATCH 13/13] xen: increase __PHYSICAL_MASK_SHIFT_XEN to 52
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The current value of __PHYSICAL_MASK_SHIFT_XEN in crash (40) is
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smaller than the kernel (52) since kernel commit 6f0e8bf167 (xen:
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support 52 bit physical addresses in pv guests).
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This can cause x86_64_pud_offset() to lose the most significant
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bits of pgd_pte, leading to a failed xen_m2p() translation,
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resulting in crash failing with an error message like this:
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crash: read error: physical address: ffffffffffffffff type: "pud page"
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Both Intel and AMD documentation mandate that unused physical
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address bits must be 0, so there is no need to explicitly mask them
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out with a mask narrower than the architecture limit of 52. This
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is also confirmed by this kernel commit: b83ce5ee91.
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Increase the value of __PHYSICAL_MASK_SHIFT_XEN to 52.
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Signed-off-by: Jiri Bohac <jbohac@suse.cz>
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Signed-off-by: Lianbo Jiang <lijiang@redhat.com>
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---
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defs.h | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/defs.h b/defs.h
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index ffbe73bfb508..35cdac20420c 100644
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--- a/defs.h
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+++ b/defs.h
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@@ -3585,7 +3585,7 @@ struct arm64_stackframe {
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* PHYSICAL_PAGE_MASK changed (enlarged) between 2.4 and 2.6, so
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* for safety, use the 2.6 values to generate it.
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*/
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-#define __PHYSICAL_MASK_SHIFT_XEN 40
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+#define __PHYSICAL_MASK_SHIFT_XEN 52
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#define __PHYSICAL_MASK_SHIFT_2_6 46
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#define __PHYSICAL_MASK_SHIFT_5LEVEL 52
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#define __PHYSICAL_MASK_SHIFT (machdep->machspec->physical_mask_shift)
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--
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2.17.1
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