From fdb41f0b6fa42a692e5fa39da3801f6ca18e8a6b Mon Sep 17 00:00:00 2001 From: Jiri Bohac Date: Mon, 25 Jan 2021 22:44:50 +0100 Subject: [PATCH 13/13] xen: increase __PHYSICAL_MASK_SHIFT_XEN to 52 The current value of __PHYSICAL_MASK_SHIFT_XEN in crash (40) is smaller than the kernel (52) since kernel commit 6f0e8bf167 (xen: support 52 bit physical addresses in pv guests). This can cause x86_64_pud_offset() to lose the most significant bits of pgd_pte, leading to a failed xen_m2p() translation, resulting in crash failing with an error message like this: crash: read error: physical address: ffffffffffffffff type: "pud page" Both Intel and AMD documentation mandate that unused physical address bits must be 0, so there is no need to explicitly mask them out with a mask narrower than the architecture limit of 52. This is also confirmed by this kernel commit: b83ce5ee91. Increase the value of __PHYSICAL_MASK_SHIFT_XEN to 52. Signed-off-by: Jiri Bohac Signed-off-by: Lianbo Jiang --- defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/defs.h b/defs.h index ffbe73bfb508..35cdac20420c 100644 --- a/defs.h +++ b/defs.h @@ -3585,7 +3585,7 @@ struct arm64_stackframe { * PHYSICAL_PAGE_MASK changed (enlarged) between 2.4 and 2.6, so * for safety, use the 2.6 values to generate it. */ -#define __PHYSICAL_MASK_SHIFT_XEN 40 +#define __PHYSICAL_MASK_SHIFT_XEN 52 #define __PHYSICAL_MASK_SHIFT_2_6 46 #define __PHYSICAL_MASK_SHIFT_5LEVEL 52 #define __PHYSICAL_MASK_SHIFT (machdep->machspec->physical_mask_shift) -- 2.17.1