Patrik Novotný
Ondrej Dubaj
parent
a4a3718ffd
commit
7878600f3a
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@ -0,0 +1,455 @@
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From 367e79caf76bda5fdb974420b72c6ddabdcd664e Mon Sep 17 00:00:00 2001
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From: Ilya Leoshkevich <iii@linux.ibm.com>
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Date: Thu, 19 Mar 2020 11:52:03 +0100
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Subject: [PATCH] s390x: vectorize crc32
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Use vector extensions when compiling for s390x and binutils knows
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about them. At runtime, check whether kernel supports vector
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extensions (it has to be not just the CPU, but also the kernel) and
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choose between the regular and the vectorized implementations.
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---
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Makefile.in | 8 ++
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configure | 16 +++
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contrib/s390/crc32le-vx.S | 273 ++++++++++++++++++++++++++++++++++++++
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crc32.c | 66 ++++++++-
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4 files changed, 361 insertions(+), 2 deletions(-)
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create mode 100644 contrib/s390/crc32le-vx.S
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diff --git a/Makefile.in b/Makefile.in
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index 6070dcc..23e8694 100644
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--- a/Makefile.in
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+++ b/Makefile.in
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@@ -179,6 +179,9 @@ crc32_power8.o: $(SRCDIR)contrib/power8-crc/vec_crc32.c
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crc32.o: $(SRCDIR)crc32.c
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$(CC) $(CFLAGS) $(ZINC) -c -o $@ $(SRCDIR)crc32.c
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+crc32le-vx.o: $(SRCDIR)contrib/s390/crc32le-vx.S
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+ $(CC) $(CFLAGS) -march=z13 $(ZINC) -c -o $@ $(SRCDIR)contrib/s390/crc32le-vx.S
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+
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deflate.o: $(SRCDIR)deflate.c
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$(CC) $(CFLAGS) $(ZINC) -c -o $@ $(SRCDIR)deflate.c
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@@ -234,6 +237,11 @@ crc32.lo: $(SRCDIR)crc32.c
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$(CC) $(SFLAGS) $(ZINC) -DPIC -c -o objs/crc32.o $(SRCDIR)crc32.c
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-@mv objs/crc32.o $@
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+crc32le-vx.lo: $(SRCDIR)contrib/s390/crc32le-vx.S
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+ -@mkdir objs 2>/dev/null || test -d objs
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+ $(CC) $(SFLAGS) -march=z13 $(ZINC) -DPIC -c -o objs/crc32le-vx.o $(SRCDIR)contrib/s390/crc32le-vx.S
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+ -@mv objs/crc32le-vx.o $@
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+
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deflate.lo: $(SRCDIR)deflate.c
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-@mkdir objs 2>/dev/null || test -d objs
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$(CC) $(SFLAGS) $(ZINC) -DPIC -c -o objs/deflate.o $(SRCDIR)deflate.c
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diff --git a/configure b/configure
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index 70ed86b..e658039 100755
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--- a/configure
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+++ b/configure
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@@ -923,6 +923,22 @@ EOF
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fi
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fi
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+# check if we are compiling for s390 and binutils support vector extensions
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+cat > $test.c <<EOF
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+#ifndef __s390__
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+#error
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+#endif
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+EOF
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+if try $CC -c $CFLAGS -march=z13 $test.c; then
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+ CFLAGS="$CFLAGS -DHAVE_S390X_VX"
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+ SFLAGS="$SFLAGS -DHAVE_S390X_VX"
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+ OBJC="$OBJC crc32le-vx.o"
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+ PIC_OBJC="$PIC_OBJC crc32le-vx.lo"
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+ echo "Checking for s390 vector extensions... Yes." | tee -a configure.log
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+else
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+ echo "Checking for s390 vector extensions... No." | tee -a configure.log
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+fi
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+
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# show the results in the log
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echo >> configure.log
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echo ALL = $ALL >> configure.log
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diff --git a/contrib/s390/crc32le-vx.S b/contrib/s390/crc32le-vx.S
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new file mode 100644
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index 0000000..029cfff
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--- /dev/null
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+++ b/contrib/s390/crc32le-vx.S
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@@ -0,0 +1,273 @@
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+/*
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+ * Hardware-accelerated CRC-32 variants for Linux on z Systems
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+ *
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+ * Use the z/Architecture Vector Extension Facility to accelerate the
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+ * computing of bitreflected CRC-32 checksums.
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+ *
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+ * This CRC-32 implementation algorithm is bitreflected and processes
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+ * the least-significant bit first (Little-Endian).
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+ *
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+ * This code has been originally written by Hendrik Brueckner
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+ * <brueckner@linux.vnet.ibm.com> and included in the Linux kernel:
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+ *
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+ * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/s390/crypto/crc32le-vx.S?h=v5.5
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+ *
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+ * Hendrik Brueckner has allowed reusing it under zlib license.
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+ *
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+ * The following adjustments were made:
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+ *
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+ * - Reformatted in order to match the zlib code style.
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+ * - Changed the vector register numbers in order to avoid clobbering the call-saved %v8-%v16.
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+ * - Fixed clang compatibility.
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+ * - Added 31-bit compatibility.
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+ */
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+
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+#ifndef __clang__
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+.machinemode zarch
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+#endif
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+
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+#define PART1 %v16
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+#define PART2 %v17
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+#define PART3 %v18
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+#define PART4 %v19
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+#define SHIFTS %v20
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+
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+/* Vector register range containing CRC-32 constants */
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+#define CONST_PERM_LE2BE %v21
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+#define CONST_R2R1 %v22
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+#define CONST_R4R3 %v23
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+#define CONST_R5 %v24
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+#define CONST_RU_POLY %v25
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+#define CONST_CRC_POLY %v26
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+
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+#if defined(__s390x__)
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+#define AGHI aghi
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+#define CGHI cghi
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+#else
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+#define AGHI ahi
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+#define CGHI chi
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+#endif
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+
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+.data
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+.align 8
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+
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+/*
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+ * The CRC-32 constant block contains reduction constants to fold and
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+ * process particular chunks of the input data stream in parallel.
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+ *
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+ * For the CRC-32 variants, the constants are precomputed according to
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+ * these definitions:
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+ *
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+ * R1 = [(x4*128+32 mod P'(x) << 32)]' << 1
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+ * R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
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+ * R3 = [(x128+32 mod P'(x) << 32)]' << 1
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+ * R4 = [(x128-32 mod P'(x) << 32)]' << 1
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+ * R5 = [(x64 mod P'(x) << 32)]' << 1
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+ * R6 = [(x32 mod P'(x) << 32)]' << 1
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+ *
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+ * The bitreflected Barret reduction constant, u', is defined as
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+ * the bit reversal of floor(x**64 / P(x)).
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+ *
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+ * where P(x) is the polynomial in the normal domain and the P'(x) is the
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+ * polynomial in the reversed (bitreflected) domain.
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+ *
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+ * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
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+ *
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+ * P(x) = 0x04C11DB7
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+ * P'(x) = 0xEDB88320
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+ */
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+
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+.Lconstants_CRC_32_LE:
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+ .octa 0x0F0E0D0C0B0A09080706050403020100 # BE->LE mask
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+ .quad 0x1c6e41596, 0x154442bd4 # R2, R1
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+ .quad 0x0ccaa009e, 0x1751997d0 # R4, R3
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+ .octa 0x163cd6124 # R5
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+ .octa 0x1F7011641 # u'
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+ .octa 0x1DB710641 # P'(x) << 1
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+
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+.text
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+
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+/*
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+ * The CRC-32 functions use these calling conventions:
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+ *
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+ * Parameters:
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+ *
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+ * %r2: Initial CRC value, typically ~0; and final CRC (return) value.
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+ * %r3: Input buffer pointer, performance might be improved if the
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+ * buffer is on a doubleword boundary.
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+ * %r4: Length of the buffer, must be 64 bytes or greater.
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+ *
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+ * Register usage:
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+ *
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+ * %r5: CRC-32 constant pool base pointer.
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+ * V0: Initial CRC value and intermediate constants and results.
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+ * V1..V4: Data for CRC computation.
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+ * V16..V19: Next data chunks that are fetched from the input buffer.
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+ * V20: Constant for BE->LE conversion and shift operations
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+ *
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+ * V21..V26: CRC-32 constants.
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+ */
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+
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+ .globl crc32_le_vgfm_16
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+ .align 4, 0x07
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+crc32_le_vgfm_16:
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+ /* Load CRC-32 constants */
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+ larl %r5,.Lconstants_CRC_32_LE
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+ VLM CONST_PERM_LE2BE,CONST_CRC_POLY,0(%r5)
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+
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+ /*
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+ * Load the initial CRC value.
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+ *
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+ * The CRC value is loaded into the rightmost word of the
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+ * vector register and is later XORed with the LSB portion
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+ * of the loaded input data.
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+ */
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+ VZERO %v0 /* Clear V0 */
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+ VLVGF %v0,%r2,3 /* Load CRC into rightmost word */
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+
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+ /* Load a 64-byte data chunk and XOR with CRC */
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+ VLM %v1,%v4,0(%r3) /* 64-bytes into V1..V4 */
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+ VPERM %v1,%v1,%v1,CONST_PERM_LE2BE
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+ VPERM %v2,%v2,%v2,CONST_PERM_LE2BE
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+ VPERM %v3,%v3,%v3,CONST_PERM_LE2BE
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+ VPERM %v4,%v4,%v4,CONST_PERM_LE2BE
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+
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+ VX %v1,%v0,%v1 /* V1 ^= CRC */
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+ AGHI %r3,64 /* BUF = BUF + 64 */
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+ AGHI %r4,-64 /* LEN = LEN - 64 */
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+
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+ CGHI %r4,64
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+ jl .Lless_than_64bytes
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+
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+.Lfold_64bytes_loop:
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+ /* Load the next 64-byte data chunk into PART1 to PART4 */
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+ VLM PART1,PART4,0(%r3)
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+ VPERM PART1,PART1,PART1,CONST_PERM_LE2BE
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+ VPERM PART2,PART2,PART2,CONST_PERM_LE2BE
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+ VPERM PART3,PART3,PART3,CONST_PERM_LE2BE
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+ VPERM PART4,PART4,PART4,CONST_PERM_LE2BE
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+
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+ /*
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+ * Perform a GF(2) multiplication of the doublewords in V1 with
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+ * the R1 and R2 reduction constants in V0. The intermediate result
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+ * is then folded (accumulated) with the next data chunk in PART1 and
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+ * stored in V1. Repeat this step for the register contents
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+ * in V2, V3, and V4 respectively.
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+ */
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+ VGFMAG %v1,CONST_R2R1,%v1,PART1
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+ VGFMAG %v2,CONST_R2R1,%v2,PART2
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+ VGFMAG %v3,CONST_R2R1,%v3,PART3
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+ VGFMAG %v4,CONST_R2R1,%v4,PART4
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+
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+ AGHI %r3,64 /* BUF = BUF + 64 */
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+ AGHI %r4,-64 /* LEN = LEN - 64 */
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+
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+ CGHI %r4,64
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+ jnl .Lfold_64bytes_loop
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+
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+.Lless_than_64bytes:
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+ /*
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+ * Fold V1 to V4 into a single 128-bit value in V1. Multiply V1 with R3
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+ * and R4 and accumulating the next 128-bit chunk until a single 128-bit
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+ * value remains.
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+ */
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+ VGFMAG %v1,CONST_R4R3,%v1,%v2
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+ VGFMAG %v1,CONST_R4R3,%v1,%v3
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+ VGFMAG %v1,CONST_R4R3,%v1,%v4
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+
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+ CGHI %r4,16
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+ jl .Lfinal_fold
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+
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+.Lfold_16bytes_loop:
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+
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+ VL %v2,0(%r3) /* Load next data chunk */
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+ VPERM %v2,%v2,%v2,CONST_PERM_LE2BE
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+ VGFMAG %v1,CONST_R4R3,%v1,%v2 /* Fold next data chunk */
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+
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+ AGHI %r3,16
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+ AGHI %r4,-16
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+
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+ CGHI %r4,16
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+ jnl .Lfold_16bytes_loop
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+
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+.Lfinal_fold:
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+ /*
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+ * Set up a vector register for byte shifts. The shift value must
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+ * be loaded in bits 1-4 in byte element 7 of a vector register.
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+ * Shift by 8 bytes: 0x40
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+ * Shift by 4 bytes: 0x20
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+ */
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+ VLEIB SHIFTS,0x40,7
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+
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+ /*
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+ * Prepare V0 for the next GF(2) multiplication: shift V0 by 8 bytes
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+ * to move R4 into the rightmost doubleword and set the leftmost
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+ * doubleword to 0x1.
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+ */
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+ VSRLB %v0,CONST_R4R3,SHIFTS
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+ VLEIG %v0,1,0
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+
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+ /*
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+ * Compute GF(2) product of V1 and V0. The rightmost doubleword
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+ * of V1 is multiplied with R4. The leftmost doubleword of V1 is
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+ * multiplied by 0x1 and is then XORed with rightmost product.
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+ * Implicitly, the intermediate leftmost product becomes padded
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+ */
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+ VGFMG %v1,%v0,%v1
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+
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+ /*
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+ * Now do the final 32-bit fold by multiplying the rightmost word
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+ * in V1 with R5 and XOR the result with the remaining bits in V1.
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+ *
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+ * To achieve this by a single VGFMAG, right shift V1 by a word
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+ * and store the result in V2 which is then accumulated. Use the
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+ * vector unpack instruction to load the rightmost half of the
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+ * doubleword into the rightmost doubleword element of V1; the other
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+ * half is loaded in the leftmost doubleword.
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+ * The vector register with CONST_R5 contains the R5 constant in the
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+ * rightmost doubleword and the leftmost doubleword is zero to ignore
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+ * the leftmost product of V1.
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+ */
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+ VLEIB SHIFTS,0x20,7 /* Shift by words */
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+ VSRLB %v2,%v1,SHIFTS /* Store remaining bits in V2 */
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+ VUPLLF %v1,%v1 /* Split rightmost doubleword */
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+ VGFMAG %v1,CONST_R5,%v1,%v2 /* V1 = (V1 * R5) XOR V2 */
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+
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+ /*
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+ * Apply a Barret reduction to compute the final 32-bit CRC value.
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+ *
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+ * The input values to the Barret reduction are the degree-63 polynomial
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+ * in V1 (R(x)), degree-32 generator polynomial, and the reduction
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+ * constant u. The Barret reduction result is the CRC value of R(x) mod
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+ * P(x).
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+ *
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+ * The Barret reduction algorithm is defined as:
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+ *
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+ * 1. T1(x) = floor( R(x) / x^32 ) GF2MUL u
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+ * 2. T2(x) = floor( T1(x) / x^32 ) GF2MUL P(x)
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+ * 3. C(x) = R(x) XOR T2(x) mod x^32
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+ *
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+ * Note: The leftmost doubleword of vector register containing
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+ * CONST_RU_POLY is zero and, thus, the intermediate GF(2) product
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+ * is zero and does not contribute to the final result.
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+ */
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+
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+ /* T1(x) = floor( R(x) / x^32 ) GF2MUL u */
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+ VUPLLF %v2,%v1
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+ VGFMG %v2,CONST_RU_POLY,%v2
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+
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+ /*
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+ * Compute the GF(2) product of the CRC polynomial with T1(x) in
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+ * V2 and XOR the intermediate result, T2(x), with the value in V1.
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+ * The final result is stored in word element 2 of V2.
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+ */
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+ VUPLLF %v2,%v2
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+ VGFMAG %v2,CONST_CRC_POLY,%v2,%v1
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+
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+.Ldone:
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+ VLGVF %r2,%v2,2
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+ BR %r14
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+ .type crc32_le_vgfm_16, @function
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+ .size crc32_le_vgfm_16, .-crc32_le_vgfm_16
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+
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+.previous
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diff --git a/crc32.c b/crc32.c
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index 34132ea..af5d3cd 100644
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--- a/crc32.c
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+++ b/crc32.c
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@@ -252,12 +252,26 @@ unsigned long crc32_vpmsum(unsigned long, const unsigned char FAR *, z_size_t);
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#endif
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#endif
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+#ifdef HAVE_S390X_VX
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+#include <sys/auxv.h>
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+
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+local unsigned long crc32_s390_vx(unsigned long crc,
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+ const unsigned char FAR *buf,
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+ z_size_t len);
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+#endif
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+
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/* due to a quirk of gnu_indirect_function - "local" (aka static) is applied to
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* crc32_z which is not desired. crc32_z_ifunc is implictly "local" */
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#ifndef Z_IFUNC_ASM
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local
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#endif
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-unsigned long (*(crc32_z_ifunc(void)))(unsigned long, const unsigned char FAR *, z_size_t)
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+unsigned long (*(crc32_z_ifunc(
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+#ifdef __s390__
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+unsigned long hwcap
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+#else
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+void
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+#endif
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+)))(unsigned long, const unsigned char FAR *, z_size_t)
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{
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#if _ARCH_PWR8==1
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#if defined(__BUILTIN_CPU_SUPPORTS__)
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@@ -269,6 +283,11 @@ unsigned long (*(crc32_z_ifunc(void)))(unsigned long, const unsigned char FAR *,
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#endif
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#endif /* _ARCH_PWR8 */
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+#ifdef HAVE_S390X_VX
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+ if (hwcap & HWCAP_S390_VX)
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+ return crc32_s390_vx;
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+#endif
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+
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/* return a function pointer for optimized arches here */
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#ifdef DYNAMIC_CRC_TABLE
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@@ -301,7 +320,11 @@ unsigned long ZEXPORT crc32_z(crc, buf, len)
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static unsigned long ZEXPORT (*crc32_func)(unsigned long, const unsigned char FAR *, z_size_t) = NULL;
|
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if (!crc32_func)
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||||
- crc32_func = crc32_z_ifunc();
|
||||
+ crc32_func = crc32_z_ifunc(
|
||||
+#ifdef __s390__
|
||||
+ getauxval(AT_HWCAP)
|
||||
+#endif
|
||||
+ );
|
||||
return (*crc32_func)(crc, buf, len);
|
||||
}
|
||||
|
||||
@@ -500,6 +523,45 @@ local uLong crc32_combine_(crc1, crc2, len2)
|
||||
return crc1;
|
||||
}
|
||||
|
||||
+#ifdef HAVE_S390X_VX
|
||||
+#define VX_MIN_LEN 64
|
||||
+#define VX_ALIGNMENT 16L
|
||||
+#define VX_ALIGN_MASK (VX_ALIGNMENT - 1)
|
||||
+
|
||||
+unsigned int crc32_le_vgfm_16(unsigned int crc,
|
||||
+ unsigned char const *buf,
|
||||
+ size_t size);
|
||||
+
|
||||
+local unsigned long crc32_s390_vx(crc, buf, len)
|
||||
+ unsigned long crc;
|
||||
+ const unsigned char FAR *buf;
|
||||
+ z_size_t len;
|
||||
+{
|
||||
+ unsigned long prealign, aligned, remaining;
|
||||
+
|
||||
+ if (buf == Z_NULL) return 0UL;
|
||||
+
|
||||
+ if (len < VX_MIN_LEN + VX_ALIGN_MASK)
|
||||
+ return crc32_big(crc, buf, len);
|
||||
+
|
||||
+ if ((unsigned long)buf & VX_ALIGN_MASK) {
|
||||
+ prealign = VX_ALIGNMENT - ((unsigned long)buf & VX_ALIGN_MASK);
|
||||
+ len -= prealign;
|
||||
+ crc = crc32_big(crc, buf, prealign);
|
||||
+ buf = (void *)((unsigned long)buf + prealign);
|
||||
+ }
|
||||
+ aligned = len & ~VX_ALIGN_MASK;
|
||||
+ remaining = len & VX_ALIGN_MASK;
|
||||
+
|
||||
+ crc = crc32_le_vgfm_16(crc ^ 0xffffffff, buf, aligned) ^ 0xffffffff;
|
||||
+
|
||||
+ if (remaining)
|
||||
+ crc = crc32_big(crc, buf + aligned, remaining);
|
||||
+
|
||||
+ return crc;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
/* ========================================================================= */
|
||||
uLong ZEXPORT crc32_combine(crc1, crc2, len2)
|
||||
uLong crc1;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
Name: zlib
|
||||
Version: 1.2.11
|
||||
Release: 27%{?dist}
|
||||
Release: 28%{?dist}
|
||||
Summary: Compression and decompression library
|
||||
# /contrib/dotzlib/ have Boost license
|
||||
License: zlib and Boost
|
||||
|
|
@ -33,6 +33,8 @@ Patch14: zlib-1.2.11-inflateSyncPoint-return-value-fix.patch
|
|||
# fixed issues found by covscan for rhel-9
|
||||
# ref: https://github.com/madler/zlib/pull/554
|
||||
Patch15: zlib-1.2.11-covscan-issues-rhel9.patch
|
||||
# Fix for s390x vectorize CRC32
|
||||
Patch16: zlib-1.2.11-s390x-vectorize-crc32.patch
|
||||
|
||||
BuildRequires: make
|
||||
BuildRequires: automake, autoconf, libtool
|
||||
|
|
@ -100,6 +102,7 @@ developing applications which use minizip.
|
|||
%patch13 -p1
|
||||
%patch14 -p1
|
||||
%patch15 -p1
|
||||
%patch16 -p1
|
||||
|
||||
|
||||
iconv -f iso-8859-2 -t utf-8 < ChangeLog > ChangeLog.tmp
|
||||
|
|
@ -181,6 +184,9 @@ find $RPM_BUILD_ROOT -name '*.la' -delete
|
|||
|
||||
|
||||
%changelog
|
||||
* Thu Jun 03 2021 Patrik Novotný <panovotn@redhat.com> - 1.2.11-28
|
||||
- IBM CRC32 optimalization rhbz#1959423
|
||||
|
||||
* Fri Apr 16 2021 Mohan Boddu <mboddu@redhat.com> - 1.2.11-27
|
||||
- Rebuilt for RHEL 9 BETA on Apr 15th 2021. Related: rhbz#1947937
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue