74 lines
2.6 KiB
Diff
74 lines
2.6 KiB
Diff
commit 3f055b64899cc4b7c34f9ebdc4beb418a8bced07
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Author: carll <carll@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
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Date: Fri Mar 10 20:07:09 2017 +0000
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PowerPC: Fix incorrect register pair check for lxv, stxv, stxsd, stxssp, lxsd,
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lxssp instructions
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The lfdpx, stdpx, lfdp and stfdp instructions work on a register pair. The
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register pair test must only be applied to these instructions in the
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dis_fp_pair() function.
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bugzilla 377427
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git-svn-id: svn://svn.valgrind.org/vex/trunk@3308 8f6e269a-dfd6-0310-a8e1-e2731360e62c
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diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
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index b19dcbc..0d27389 100644
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--- a/VEX/priv/guest_ppc_toIR.c
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+++ b/VEX/priv/guest_ppc_toIR.c
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@@ -11310,13 +11310,16 @@ static Bool dis_fp_pair ( UInt theInstr )
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UChar b0 = ifieldBIT0(theInstr);
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Bool is_load = 0;
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- if ((frT_hi_addr %2) != 0) {
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- vex_printf("dis_fp_pair(ppc) : odd frT register\n");
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- return False;
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- }
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-
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switch (opc1) {
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case 0x1F: // register offset
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+ /* These instructions work on a pair of registers. The specified
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+ * register must be even.
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+ */
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+ if ((frT_hi_addr %2) != 0) {
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+ vex_printf("dis_fp_pair(ppc) ldpx or stdpx: odd frT register\n");
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+ return False;
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+ }
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+
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switch(opc2) {
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case 0x317: // lfdpx (FP Load Double Pair X-form, ISA 2.05 p125)
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DIP("ldpx fr%u,r%u,r%u\n", frT_hi_addr, rA_addr, rB_addr);
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@@ -11346,6 +11349,14 @@ static Bool dis_fp_pair ( UInt theInstr )
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switch(opc2) {
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case 0x0: // lfdp (FP Load Double Pair DS-form, ISA 2.05 p125)
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+ /* This instruction works on a pair of registers. The specified
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+ * register must be even.
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+ */
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+ if ((frT_hi_addr %2) != 0) {
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+ vex_printf("dis_fp_pair(ppc) lfdp : odd frT register\n");
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+ return False;
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+ }
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+
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DIP("lfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
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assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
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is_load = 1;
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@@ -11390,6 +11401,14 @@ static Bool dis_fp_pair ( UInt theInstr )
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switch(opc2) {
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case 0x0:
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// stfdp (FP Store Double Pair DS-form, ISA 2.05 p125)
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+ /* This instruction works on a pair of registers. The specified
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+ * register must be even.
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+ */
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+ if ((frT_hi_addr %2) != 0) {
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+ vex_printf("dis_fp_pair(ppc) stfdp : odd frT register\n");
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+ return False;
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+ }
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+
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DIP("stfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
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assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
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break;
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