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Add valgrind-3.12.0-powerpc-register-pair.patch

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Mark Wielaard 2017-03-28 22:55:23 +02:00
parent 3dda5d8d28
commit 27f6306ee9
2 changed files with 81 additions and 0 deletions
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73
valgrind-3.12.0-powerpc-register-pair.patch Normal file
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@ -0,0 +1,73 @@
commit 3f055b64899cc4b7c34f9ebdc4beb418a8bced07
Author: carll <carll@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
Date: Fri Mar 10 20:07:09 2017 +0000
PowerPC: Fix incorrect register pair check for lxv, stxv, stxsd, stxssp, lxsd,
lxssp instructions
The lfdpx, stdpx, lfdp and stfdp instructions work on a register pair. The
register pair test must only be applied to these instructions in the
dis_fp_pair() function.
bugzilla 377427
git-svn-id: svn://svn.valgrind.org/vex/trunk@3308 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index b19dcbc..0d27389 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -11310,13 +11310,16 @@ static Bool dis_fp_pair ( UInt theInstr )
UChar b0 = ifieldBIT0(theInstr);
Bool is_load = 0;
- if ((frT_hi_addr %2) != 0) {
- vex_printf("dis_fp_pair(ppc) : odd frT register\n");
- return False;
- }
-
switch (opc1) {
case 0x1F: // register offset
+ /* These instructions work on a pair of registers. The specified
+ * register must be even.
+ */
+ if ((frT_hi_addr %2) != 0) {
+ vex_printf("dis_fp_pair(ppc) ldpx or stdpx: odd frT register\n");
+ return False;
+ }
+
switch(opc2) {
case 0x317: // lfdpx (FP Load Double Pair X-form, ISA 2.05 p125)
DIP("ldpx fr%u,r%u,r%u\n", frT_hi_addr, rA_addr, rB_addr);
@@ -11346,6 +11349,14 @@ static Bool dis_fp_pair ( UInt theInstr )
switch(opc2) {
case 0x0: // lfdp (FP Load Double Pair DS-form, ISA 2.05 p125)
+ /* This instruction works on a pair of registers. The specified
+ * register must be even.
+ */
+ if ((frT_hi_addr %2) != 0) {
+ vex_printf("dis_fp_pair(ppc) lfdp : odd frT register\n");
+ return False;
+ }
+
DIP("lfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
is_load = 1;
@@ -11390,6 +11401,14 @@ static Bool dis_fp_pair ( UInt theInstr )
switch(opc2) {
case 0x0:
// stfdp (FP Store Double Pair DS-form, ISA 2.05 p125)
+ /* This instruction works on a pair of registers. The specified
+ * register must be even.
+ */
+ if ((frT_hi_addr %2) != 0) {
+ vex_printf("dis_fp_pair(ppc) stfdp : odd frT register\n");
+ return False;
+ }
+
DIP("stfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
break;

8
valgrind.spec
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@ -126,6 +126,10 @@ Patch17: valgrind-3.12.0-ppc-xxsel.patch
# getcpu and sethostname syscalls on arm64.
Patch18: valgrind-3.12.0-aarch64-syscalls.patch
# KDE#377427 Fix incorrect register pair check for lxv, stxv, stxsd,
# stxssp, lxsd, lxssp instructions
Patch19: valgrind-3.12.0-powerpc-register-pair.patch
%if %{build_multilib}
# Ensure glibc{,-devel} is installed for both multilib arches
BuildRequires: /lib/libc.so.6 /usr/lib/libc.so /lib64/libc.so.6 /usr/lib64/libc.so
@ -253,6 +257,7 @@ Valgrind User Manual for details.
%patch16 -p1
%patch17 -p1
%patch18 -p1
%patch19 -p1
%build
# We need to use the software collection compiler and binutils if available.
@ -446,6 +451,9 @@ echo ===============END TESTING===============
%endif
%changelog
* Tue Mar 28 2017 Mark Wielaard <mjw@redhat.com>
- Add valgrind-3.12.0-powerpc-register-pair.patch
* Sat Feb 18 2017 Mark Wielaard <mjw@redhat.com> - 3.12.0-7
- Add valgrind-3.12.0-aarch64-syscalls.patch