Enable arm64 optimizations.
The same already exists for power/x86. Resolves: rhbz#1884728 Related: rhbz#1947938
This commit is contained in:
Vít Ondruch
parent
f80c0b1d07
commit
d064a7f405
@ -0,0 +1,178 @@
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From c5806d668f84a86e9e6a522f84b8aa6cb4cdaae9 Mon Sep 17 00:00:00 2001
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From: Ali Saidi <alisaidi@amazon.com>
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Date: Wed, 5 Aug 2020 20:46:28 -0500
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Subject: [PATCH 1/3] Enable unaligned accesses on arm64
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64-bit Arm platforms support unaligned accesses.
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Running the string benchmarks this change improves performance
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by an average of 1.04x, min .96x, max 1.21x, median 1.01x
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---
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include/ruby/defines.h | 2 +-
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regint.h | 2 +-
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siphash.c | 2 +-
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st.c | 2 +-
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4 files changed, 4 insertions(+), 4 deletions(-)
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diff --git a/include/ruby/defines.h b/include/ruby/defines.h
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index 49f673ef936a..0193275e8b78 100644
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--- a/include/ruby/defines.h
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+++ b/include/ruby/defines.h
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@@ -485,7 +485,7 @@
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#ifndef UNALIGNED_WORD_ACCESS
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# if defined(__i386) || defined(__i386__) || defined(_M_IX86) || \
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defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64) || \
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- defined(__powerpc64__) || \
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+ defined(__powerpc64__) || defined(__aarch64__) || \
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defined(__mc68020__)
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# define UNALIGNED_WORD_ACCESS 1
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# else
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diff --git a/regint.h b/regint.h
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index a2f5bbba1d1f..0740429688bc 100644
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--- a/regint.h
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+++ b/regint.h
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@@ -52,7 +52,7 @@
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#ifndef UNALIGNED_WORD_ACCESS
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# if defined(__i386) || defined(__i386__) || defined(_M_IX86) || \
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defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64) || \
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- defined(__powerpc64__) || \
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+ defined(__powerpc64__) || defined(__aarch64__) || \
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defined(__mc68020__)
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# define UNALIGNED_WORD_ACCESS 1
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# else
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diff --git a/siphash.c b/siphash.c
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index 153d2c690ab9..ddf8ee245d81 100644
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--- a/siphash.c
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+++ b/siphash.c
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@@ -30,7 +30,7 @@
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#ifndef UNALIGNED_WORD_ACCESS
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# if defined(__i386) || defined(__i386__) || defined(_M_IX86) || \
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defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64) || \
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- defined(__powerpc64__) || \
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+ defined(__powerpc64__) || defined(__aarch64__) || \
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defined(__mc68020__)
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# define UNALIGNED_WORD_ACCESS 1
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# endif
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diff --git a/st.c b/st.c
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index c11535ef9779..8be466bf733f 100644
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--- a/st.c
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+++ b/st.c
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@@ -1815,7 +1815,7 @@ st_values_check(st_table *tab, st_data_t *values, st_index_t size,
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#ifndef UNALIGNED_WORD_ACCESS
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# if defined(__i386) || defined(__i386__) || defined(_M_IX86) || \
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defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64) || \
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- defined(__powerpc64__) || \
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+ defined(__powerpc64__) || defined(__aarch64__) || \
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defined(__mc68020__)
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# define UNALIGNED_WORD_ACCESS 1
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# endif
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From 79b7b9143fda0f33fc9375980cecc61eb42c6f66 Mon Sep 17 00:00:00 2001
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From: Ali Saidi <alisaidi@amazon.com>
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Date: Wed, 5 Aug 2020 21:04:37 -0500
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Subject: [PATCH 2/3] arm64 enable gc optimizations
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Similar to x86 and powerpc optimizations.
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| |compare-ruby|built-ruby|
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|:------|-----------:|---------:|
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|hash1 | 0.225| 0.237|
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| | -| 1.05x|
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|hash2 | 0.110| 0.110|
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| | 1.00x| -|
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---
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gc.c | 13 +++++++++++++
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gc.h | 2 ++
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2 files changed, 15 insertions(+)
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diff --git a/gc.c b/gc.c
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index 22972dfc806c..788f06f1586e 100644
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--- a/gc.c
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+++ b/gc.c
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@@ -1153,6 +1153,19 @@ tick(void)
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return val;
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}
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+#elif defined(__aarch64__) && defined(__GNUC__)
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+typedef unsigned long tick_t;
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+#define PRItick "lu"
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+
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+static __inline__ tick_t
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+tick(void)
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+{
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+ unsigned long val;
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+ __asm__ __volatile__ ("mrs %0, cntvct_el0", : "=r" (val));
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+ return val;
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+}
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+
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+
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#elif defined(_WIN32) && defined(_MSC_VER)
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#include <intrin.h>
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typedef unsigned __int64 tick_t;
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diff --git a/gc.h b/gc.h
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index 6568079c54e5..47a4ca19a0c5 100644
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--- a/gc.h
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+++ b/gc.h
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@@ -8,6 +8,8 @@
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#define SET_MACHINE_STACK_END(p) __asm__ __volatile__ ("movl\t%%esp, %0" : "=r" (*(p)))
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#elif defined(__powerpc64__) && defined(__GNUC__)
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#define SET_MACHINE_STACK_END(p) __asm__ __volatile__ ("mr\t%0, %%r1" : "=r" (*(p)))
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+#elif defined(__aarch64__) && defined(__GNUC__)
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+#define SET_MACHINE_STACK_END(p) __asm__ __volatile__ ("mov\t%0, sp" : "=r" (*(p)))
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#else
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NOINLINE(void rb_gc_set_stack_end(VALUE **stack_end_p));
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#define SET_MACHINE_STACK_END(p) rb_gc_set_stack_end(p)
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From c985b8c6868a380e44e285368af4a4f414ce3309 Mon Sep 17 00:00:00 2001
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From: Ali Saidi <alisaidi@amazon.com>
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Date: Wed, 5 Aug 2020 21:15:55 -0500
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Subject: [PATCH 3/3] vm_exec.c: improve performance for arm64
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| |compare-ruby|built-ruby|
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|:------------------------------|-----------:|---------:|
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|vm_array | 26.501M| 27.959M|
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| | -| 1.06x|
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|vm_attr_ivar | 21.606M| 31.429M|
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| | -| 1.45x|
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|vm_attr_ivar_set | 21.178M| 26.113M|
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| | -| 1.23x|
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|vm_backtrace | 6.621| 6.668|
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| | -| 1.01x|
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|vm_bigarray | 26.205M| 29.958M|
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| | -| 1.14x|
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|vm_bighash | 504.155k| 479.306k|
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| | 1.05x| -|
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|vm_block | 16.692M| 21.315M|
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| | -| 1.28x|
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|block_handler_type_iseq | 5.083| 7.004|
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| | -| 1.38x|
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---
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vm_exec.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/vm_exec.c b/vm_exec.c
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index ce2e053ee745..7aa56f6ad620 100644
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--- a/vm_exec.c
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+++ b/vm_exec.c
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@@ -27,6 +27,9 @@ static void vm_insns_counter_count_insn(int insn) {}
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#elif defined(__GNUC__) && defined(__powerpc64__)
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#define DECL_SC_REG(type, r, reg) register type reg_##r __asm__("r" reg)
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+#elif defined(__GNUC__) && defined(__aarch64__)
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+#define DECL_SC_REG(type, r, reg) register type reg_##r __asm__("x" reg)
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+
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#else
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#define DECL_SC_REG(type, r, reg) register type reg_##r
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#endif
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@@ -74,6 +77,11 @@ vm_exec_core(rb_execution_context_t *ec, VALUE initial)
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DECL_SC_REG(rb_control_frame_t *, cfp, "15");
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#define USE_MACHINE_REGS 1
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+#elif defined(__GNUC__) && defined(__aarch64__)
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+ DECL_SC_REG(const VALUE *, pc, "19");
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+ DECL_SC_REG(rb_control_frame_t *, cfp, "20");
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+#define USE_MACHINE_REGS 1
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+
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#else
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register rb_control_frame_t *reg_cfp;
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const VALUE *reg_pc;
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@ -164,6 +164,10 @@ Patch18: rubygems-3.1.3-Fix-correctness-and-performance-regression-in-require.pa
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# Avoid possible timeout errors in TestBugReporter#test_bug_reporter_add.
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# Avoid possible timeout errors in TestBugReporter#test_bug_reporter_add.
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# https://bugs.ruby-lang.org/issues/16492
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# https://bugs.ruby-lang.org/issues/16492
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Patch19: ruby-2.7.1-Timeout-the-test_bug_reporter_add-witout-raising-err.patch
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Patch19: ruby-2.7.1-Timeout-the-test_bug_reporter_add-witout-raising-err.patch
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# Enable arm64 optimizations.
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# https://bugzilla.redhat.com/show_bug.cgi?id=1884728
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# https://github.com/ruby/ruby/pull/3393
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Patch20: ruby-3.0.0-preview1-Enable-arm64-optimizations-that-exist-for-power-x86.patch
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Requires: %{name}-libs%{?_isa} = %{version}-%{release}
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Requires: %{name}-libs%{?_isa} = %{version}-%{release}
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Suggests: rubypick
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Suggests: rubypick
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@ -579,6 +583,7 @@ rm -rf ext/fiddle/libffi*
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%patch17 -p1
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%patch17 -p1
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%patch18 -p1
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%patch18 -p1
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%patch19 -p1
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%patch19 -p1
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%patch20 -p1
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# Provide an example of usage of the tapset:
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# Provide an example of usage of the tapset:
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cp -a %{SOURCE3} .
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cp -a %{SOURCE3} .
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