cfbebe833a
- kvm-target-i386-cpu-set-correct-supported-XCR0-features-.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-do-not-rely-on-ExtSaveArea-for-accelerat.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-return-bool-from-x86_cpu_filter_features.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-AVX10-feature-and-AVX10-version-prop.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-CPUID.24-features-for-AVX10.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Add-feature-dependencies-for-AVX10.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Add-AVX512-state-when-AVX10-is-supported.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Introduce-GraniteRapids-v2-model.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-sha512-sm3-sm4-feature-bits.patch [RHEL-30316 RHEL-45111] - kvm-arm-disable-pauth-for-virt-rhel9.patch [RHEL-75782] - kvm-tests-qtest-disable-most-pauth-tests.patch [RHEL-75782] - Resolves: RHEL-30316 ([Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support) - Resolves: RHEL-45111 ([Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4) - Resolves: RHEL-75782 ([Nvidia "Grace"] Lack of "PAuth" CPU feature results in live migration failure from RHEL 9.6 to 10)
60 lines
2.3 KiB
Diff
60 lines
2.3 KiB
Diff
From 1895c3aa9eb0037eb06745ef499eb7476bebd554 Mon Sep 17 00:00:00 2001
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From: Tao Su <tao1.su@linux.intel.com>
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Date: Thu, 31 Oct 2024 16:52:33 +0800
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Subject: [PATCH 08/11] target/i386: Introduce GraniteRapids-v2 model
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
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RH-Jira: RHEL-30316 RHEL-45111
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [8/9] 5b684731a1d2c2687515eb984398c9dc5bc3fc23 (bonzini/rhel-qemu-kvm)
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Update GraniteRapids CPU model to add AVX10 and the missing features(ss,
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tsc-adjust, cldemote, movdiri, movdir64b).
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Tested-by: Xuelian Guo <xuelian.guo@intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Link: https://lore.kernel.org/r/20241028024512.156724-7-tao1.su@linux.intel.com
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Link: https://lore.kernel.org/r/20241031085233.425388-9-tao1.su@linux.intel.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 1a519388a882fbb352e49cbebb0ed8f62d05842d)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/cpu.c | 17 +++++++++++++++++
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1 file changed, 17 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 5042cbaa0e..ad368252d8 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -4393,6 +4393,23 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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.model_id = "Intel Xeon Processor (GraniteRapids)",
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.versions = (X86CPUVersionDefinition[]) {
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{ .version = 1 },
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+ {
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+ .version = 2,
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+ .props = (PropValue[]) {
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+ { "ss", "on" },
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+ { "tsc-adjust", "on" },
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+ { "cldemote", "on" },
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+ { "movdiri", "on" },
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+ { "movdir64b", "on" },
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+ { "avx10", "on" },
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+ { "avx10-128", "on" },
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+ { "avx10-256", "on" },
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+ { "avx10-512", "on" },
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+ { "avx10-version", "1" },
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+ { "stepping", "1" },
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+ { /* end of list */ }
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+ }
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+ },
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{ /* end of list */ },
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},
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},
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--
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2.48.0
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