* Mon Jan 27 2025 Jon Maloy <jmaloy@redhat.com> - 9.1.0-12
- kvm-target-i386-cpu-set-correct-supported-XCR0-features-.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-do-not-rely-on-ExtSaveArea-for-accelerat.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-return-bool-from-x86_cpu_filter_features.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-AVX10-feature-and-AVX10-version-prop.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-CPUID.24-features-for-AVX10.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Add-feature-dependencies-for-AVX10.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Add-AVX512-state-when-AVX10-is-supported.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Introduce-GraniteRapids-v2-model.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-sha512-sm3-sm4-feature-bits.patch [RHEL-30316 RHEL-45111] - kvm-arm-disable-pauth-for-virt-rhel9.patch [RHEL-75782] - kvm-tests-qtest-disable-most-pauth-tests.patch [RHEL-75782] - Resolves: RHEL-30316 ([Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support) - Resolves: RHEL-45111 ([Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4) - Resolves: RHEL-75782 ([Nvidia "Grace"] Lack of "PAuth" CPU feature results in live migration failure from RHEL 9.6 to 10)
This commit is contained in:
Jon Maloy
parent
7a1f7d789e
commit
cfbebe833a
60
kvm-arm-disable-pauth-for-virt-rhel9.patch
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60
kvm-arm-disable-pauth-for-virt-rhel9.patch
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@ -0,0 +1,60 @@
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From 664e672182e39516f26e5f6b10784e42c9dd9864 Mon Sep 17 00:00:00 2001
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From: Sebastian Ott <sebott@redhat.com>
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Date: Wed, 22 Jan 2025 06:01:21 -0500
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Subject: [PATCH 10/11] arm: disable pauth for virt-rhel9*
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RH-Author: Sebastian Ott <sebott@redhat.com>
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RH-MergeRequest: 330: arm: disable pauth for virt-rhel9*
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RH-Jira: RHEL-75782
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RH-Acked-by: Eric Auger <eric.auger@redhat.com>
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RH-Acked-by: Kashyap Chamarthy <None>
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RH-Acked-by: Gavin Shan <gshan@redhat.com>
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RH-Commit: [1/2] 6b30d9a755f06d6823b8a874babf12a1b5fc3295 (seott1/cos-qemu-kvm)
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RHEL9 kernels have pauth disabled while RHEL10 has it enabled,
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since qemu will setup the VM/VCPU with pauth when KVM supports it
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the guest visible ID registers will change when a RHEL9 qemu is
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used on a RHEL10 kernel (e.g. in a container on a host with pauth
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support).
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Make sure that virt-rhel9* machine types in RHEL9 stay the same
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independent of the kernel.
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Signed-off-by: Sebastian Ott <sebott@redhat.com>
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JIRA: https://issues.redhat.com/browse/RHEL-75782
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---
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hw/arm/virt.c | 11 +++++++++++
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1 file changed, 11 insertions(+)
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diff --git a/hw/arm/virt.c b/hw/arm/virt.c
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index c50bff2a6c..c5270a5abc 100644
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--- a/hw/arm/virt.c
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+++ b/hw/arm/virt.c
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@@ -90,6 +90,16 @@ static GlobalProperty arm_virt_compat[] = {
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};
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static const size_t arm_virt_compat_len = G_N_ELEMENTS(arm_virt_compat);
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+/*
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+ * RHEL9 kernels have pauth disabled while RHEL10 has it enabled,
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+ * since qemu will setup the VM with pauth when KVM supports it we
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+ * have to disable it for virt-rhel9* to support upgrades / migration.
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+ */
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+GlobalProperty arm_rhel9_compat[] = {
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+ {TYPE_ARM_CPU, "pauth", "off", .optional = true},
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+};
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+const size_t arm_rhel9_compat_len = G_N_ELEMENTS(arm_rhel9_compat);
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+
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/*
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* This variable is for changes to properties that are RHEL specific,
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* different to the current upstream and to be applied to the latest
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@@ -3589,6 +3599,7 @@ DEFINE_VIRT_MACHINE(2, 6)
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static void virt_rhel_machine_9_6_0_options(MachineClass *mc)
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{
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+ compat_props_add(mc->compat_props, arm_rhel9_compat, arm_rhel9_compat_len);
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}
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DEFINE_VIRT_MACHINE_AS_LATEST(9, 6, 0)
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--
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2.48.0
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@ -0,0 +1,56 @@
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From bc3752c831177ce5a57121b6a7f6753e024b211c Mon Sep 17 00:00:00 2001
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From: Tao Su <tao1.su@linux.intel.com>
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Date: Thu, 31 Oct 2024 16:52:32 +0800
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Subject: [PATCH 07/11] target/i386: Add AVX512 state when AVX10 is supported
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
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RH-Jira: RHEL-30316 RHEL-45111
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [7/9] 6c1875f13c0d3224e8afe7d03ef3681285f85c98 (bonzini/rhel-qemu-kvm)
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AVX10 state enumeration in CPUID leaf D and enabling in XCR0 register
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are identical to AVX512 state regardless of the supported vector lengths.
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Given that some E-cores will support AVX10 but not support AVX512, add
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AVX512 state components to guest when AVX10 is enabled.
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Based on a patch by Tao Su <tao1.su@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Tested-by: Xuelian Guo <xuelian.guo@intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Link: https://lore.kernel.org/r/20241031085233.425388-8-tao1.su@linux.intel.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 0d7475be3b402c25d74c5a4573cbeb733c8f3559)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/cpu.c | 10 +++++++++-
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1 file changed, 9 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 71d1f362e2..5042cbaa0e 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -7142,7 +7142,15 @@ static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa)
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return false;
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}
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- return (env->features[esa->feature] & esa->bits);
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+ if (env->features[esa->feature] & esa->bits) {
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+ return true;
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+ }
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+ if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F
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+ && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) {
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+ return true;
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+ }
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+
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+ return false;
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}
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static void x86_cpu_reset_hold(Object *obj, ResetType type)
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--
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2.48.0
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89
kvm-target-i386-Add-feature-dependencies-for-AVX10.patch
Normal file
89
kvm-target-i386-Add-feature-dependencies-for-AVX10.patch
Normal file
@ -0,0 +1,89 @@
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From eaa0a5dae408cb2848fcd2a8fe3999cba992ddef Mon Sep 17 00:00:00 2001
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From: Tao Su <tao1.su@linux.intel.com>
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Date: Thu, 31 Oct 2024 16:52:31 +0800
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Subject: [PATCH 06/11] target/i386: Add feature dependencies for AVX10
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
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RH-Jira: RHEL-30316 RHEL-45111
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [6/9] cbe290c488128b5b5a8f11b29d90399fb6172c57 (bonzini/rhel-qemu-kvm)
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Since the highest supported vector length for a processor implies that
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all lesser vector lengths are also supported, add the dependencies of
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the supported vector lengths. If all vector lengths aren't supported,
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clear AVX10 enable bit as well.
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Note that the order of AVX10 related dependencies should be kept as:
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CPUID_24_0_EBX_AVX10_128 -> CPUID_24_0_EBX_AVX10_256,
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CPUID_24_0_EBX_AVX10_256 -> CPUID_24_0_EBX_AVX10_512,
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CPUID_24_0_EBX_AVX10_VL_MASK -> CPUID_7_1_EDX_AVX10,
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CPUID_7_1_EDX_AVX10 -> CPUID_24_0_EBX,
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so that prevent user from setting weird CPUID combinations, e.g. 256-bits
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and 512-bits are supported but 128-bits is not, no vector lengths are
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supported but AVX10 enable bit is still set.
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Since AVX10_128 will be reserved as 1, adding these dependencies has the
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bonus that when user sets -cpu host,-avx10-128, CPUID_7_1_EDX_AVX10 and
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CPUID_24_0_EBX will be disabled automatically.
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Tested-by: Xuelian Guo <xuelian.guo@intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Link: https://lore.kernel.org/r/20241028024512.156724-5-tao1.su@linux.intel.com
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Link: https://lore.kernel.org/r/20241031085233.425388-7-tao1.su@linux.intel.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 150ab84b2d0083e6af344cca70290614d4fe568d)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/cpu.c | 16 ++++++++++++++++
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target/i386/cpu.h | 4 ++++
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2 files changed, 20 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index b6021be50d..71d1f362e2 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1766,6 +1766,22 @@ static FeatureDep feature_dependencies[] = {
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.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX },
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.to = { FEAT_SGX_12_1_EAX, ~0ull },
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},
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+ {
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+ .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 },
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+ .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 },
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+ },
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+ {
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+ .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 },
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+ .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 },
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+ },
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+ {
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+ .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK },
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+ .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
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+ },
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+ {
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+ .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
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+ .to = { FEAT_24_0_EBX, ~0ull },
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+ },
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};
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typedef struct X86RegisterInfo32 {
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index c60290b8d5..4da9ed5930 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -997,6 +997,10 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
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#define CPUID_24_0_EBX_AVX10_256 (1U << 17)
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/* AVX10 512-bit vector support is present */
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#define CPUID_24_0_EBX_AVX10_512 (1U << 18)
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+/* AVX10 vector length support mask */
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+#define CPUID_24_0_EBX_AVX10_VL_MASK (CPUID_24_0_EBX_AVX10_128 | \
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+ CPUID_24_0_EBX_AVX10_256 | \
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+ CPUID_24_0_EBX_AVX10_512)
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/* RAS Features */
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#define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0)
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--
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2.48.0
|
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59
kvm-target-i386-Introduce-GraniteRapids-v2-model.patch
Normal file
59
kvm-target-i386-Introduce-GraniteRapids-v2-model.patch
Normal file
@ -0,0 +1,59 @@
|
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From 1895c3aa9eb0037eb06745ef499eb7476bebd554 Mon Sep 17 00:00:00 2001
|
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From: Tao Su <tao1.su@linux.intel.com>
|
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Date: Thu, 31 Oct 2024 16:52:33 +0800
|
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Subject: [PATCH 08/11] target/i386: Introduce GraniteRapids-v2 model
|
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|
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
|
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RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
|
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RH-Jira: RHEL-30316 RHEL-45111
|
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
|
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
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RH-Commit: [8/9] 5b684731a1d2c2687515eb984398c9dc5bc3fc23 (bonzini/rhel-qemu-kvm)
|
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|
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Update GraniteRapids CPU model to add AVX10 and the missing features(ss,
|
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tsc-adjust, cldemote, movdiri, movdir64b).
|
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|
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Tested-by: Xuelian Guo <xuelian.guo@intel.com>
|
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
|
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Link: https://lore.kernel.org/r/20241028024512.156724-7-tao1.su@linux.intel.com
|
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
|
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
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Link: https://lore.kernel.org/r/20241031085233.425388-9-tao1.su@linux.intel.com
|
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
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(cherry picked from commit 1a519388a882fbb352e49cbebb0ed8f62d05842d)
|
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
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---
|
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target/i386/cpu.c | 17 +++++++++++++++++
|
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1 file changed, 17 insertions(+)
|
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|
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
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index 5042cbaa0e..ad368252d8 100644
|
||||
--- a/target/i386/cpu.c
|
||||
+++ b/target/i386/cpu.c
|
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@@ -4393,6 +4393,23 @@ static const X86CPUDefinition builtin_x86_defs[] = {
|
||||
.model_id = "Intel Xeon Processor (GraniteRapids)",
|
||||
.versions = (X86CPUVersionDefinition[]) {
|
||||
{ .version = 1 },
|
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+ {
|
||||
+ .version = 2,
|
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+ .props = (PropValue[]) {
|
||||
+ { "ss", "on" },
|
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+ { "tsc-adjust", "on" },
|
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+ { "cldemote", "on" },
|
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+ { "movdiri", "on" },
|
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+ { "movdir64b", "on" },
|
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+ { "avx10", "on" },
|
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+ { "avx10-128", "on" },
|
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+ { "avx10-256", "on" },
|
||||
+ { "avx10-512", "on" },
|
||||
+ { "avx10-version", "1" },
|
||||
+ { "stepping", "1" },
|
||||
+ { /* end of list */ }
|
||||
+ }
|
||||
+ },
|
||||
{ /* end of list */ },
|
||||
},
|
||||
},
|
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--
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2.48.0
|
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|
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224
kvm-target-i386-add-AVX10-feature-and-AVX10-version-prop.patch
Normal file
224
kvm-target-i386-add-AVX10-feature-and-AVX10-version-prop.patch
Normal file
@ -0,0 +1,224 @@
|
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From 887a4929ea393510d6867c160ced628798e17163 Mon Sep 17 00:00:00 2001
|
||||
From: Tao Su <tao1.su@linux.intel.com>
|
||||
Date: Thu, 31 Oct 2024 16:52:29 +0800
|
||||
Subject: [PATCH 04/11] target/i386: add AVX10 feature and AVX10 version
|
||||
property
|
||||
|
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
|
||||
RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
|
||||
RH-Jira: RHEL-30316 RHEL-45111
|
||||
RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
|
||||
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
||||
RH-Commit: [4/9] c71d05d79d1a228c01ab5fc5f486ae5db9e98a1b (bonzini/rhel-qemu-kvm)
|
||||
|
||||
When AVX10 enable bit is set, the 0x24 leaf will be present as "AVX10
|
||||
Converged Vector ISA leaf" containing fields for the version number and
|
||||
the supported vector bit lengths.
|
||||
|
||||
Introduce avx10-version property so that avx10 version can be controlled
|
||||
by user and cpu model. Per spec, avx10 version can never be 0, the default
|
||||
value of avx10-version is set to 0 to determine whether it is specified by
|
||||
user. The default can come from the device model or, for the max model,
|
||||
from KVM's reported value.
|
||||
|
||||
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
|
||||
Link: https://lore.kernel.org/r/20241028024512.156724-3-tao1.su@linux.intel.com
|
||||
Link: https://lore.kernel.org/r/20241028024512.156724-4-tao1.su@linux.intel.com
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
|
||||
Link: https://lore.kernel.org/r/20241031085233.425388-5-tao1.su@linux.intel.com
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
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(cherry picked from commit bccfb846fd52d6f20704ecfa4d01b60b43c6f640)
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
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---
|
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target/i386/cpu.c | 64 ++++++++++++++++++++++++++++++++++++++-----
|
||||
target/i386/cpu.h | 4 +++
|
||||
target/i386/kvm/kvm.c | 3 +-
|
||||
3 files changed, 63 insertions(+), 8 deletions(-)
|
||||
|
||||
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
||||
index 982d9bd7f6..6c041ec5af 100644
|
||||
--- a/target/i386/cpu.c
|
||||
+++ b/target/i386/cpu.c
|
||||
@@ -47,6 +47,9 @@
|
||||
#include "cpu-internal.h"
|
||||
|
||||
static void x86_cpu_realizefn(DeviceState *dev, Error **errp);
|
||||
+static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index,
|
||||
+ uint32_t *eax, uint32_t *ebx,
|
||||
+ uint32_t *ecx, uint32_t *edx);
|
||||
|
||||
/* Helpers for building CPUID[2] descriptors: */
|
||||
|
||||
@@ -1133,7 +1136,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
||||
"avx-vnni-int8", "avx-ne-convert", NULL, NULL,
|
||||
"amx-complex", NULL, "avx-vnni-int16", NULL,
|
||||
NULL, NULL, "prefetchiti", NULL,
|
||||
- NULL, NULL, NULL, NULL,
|
||||
+ NULL, NULL, NULL, "avx10",
|
||||
NULL, NULL, NULL, NULL,
|
||||
NULL, NULL, NULL, NULL,
|
||||
NULL, NULL, NULL, NULL,
|
||||
@@ -1961,6 +1964,7 @@ typedef struct X86CPUDefinition {
|
||||
int family;
|
||||
int model;
|
||||
int stepping;
|
||||
+ uint8_t avx10_version;
|
||||
FeatureWordArray features;
|
||||
const char *model_id;
|
||||
const CPUCaches *const cache_info;
|
||||
@@ -6328,6 +6332,9 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
|
||||
*/
|
||||
object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
|
||||
|
||||
+ object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version,
|
||||
+ &error_abort);
|
||||
+
|
||||
x86_cpu_apply_version_props(cpu, model);
|
||||
|
||||
/*
|
||||
@@ -6856,6 +6863,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
||||
}
|
||||
break;
|
||||
}
|
||||
+ case 0x24: {
|
||||
+ *eax = 0;
|
||||
+ *ebx = 0;
|
||||
+ *ecx = 0;
|
||||
+ *edx = 0;
|
||||
+ if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) {
|
||||
+ *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version;
|
||||
+ }
|
||||
+ break;
|
||||
+ }
|
||||
case 0x40000000:
|
||||
/*
|
||||
* CPUID code in kvm_arch_init_vcpu() ignores stuff
|
||||
@@ -7436,6 +7453,12 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
|
||||
~env->user_features[w] &
|
||||
~feature_word_info[w].no_autoenable_flags;
|
||||
}
|
||||
+
|
||||
+ if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) {
|
||||
+ uint32_t eax, ebx, ecx, edx;
|
||||
+ x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx);
|
||||
+ env->avx10_version = ebx & 0xff;
|
||||
+ }
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
|
||||
@@ -7499,6 +7522,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
|
||||
x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
|
||||
}
|
||||
|
||||
+ /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */
|
||||
+ if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) {
|
||||
+ x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24);
|
||||
+ }
|
||||
+
|
||||
/* SVM requires CPUID[0x8000000A] */
|
||||
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
|
||||
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
|
||||
@@ -7549,6 +7577,10 @@ static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose)
|
||||
CPUX86State *env = &cpu->env;
|
||||
FeatureWord w;
|
||||
const char *prefix = NULL;
|
||||
+ bool have_filtered_features;
|
||||
+
|
||||
+ uint32_t eax_0, ebx_0, ecx_0, edx_0;
|
||||
+ uint32_t eax_1, ebx_1, ecx_1, edx_1;
|
||||
|
||||
if (verbose) {
|
||||
prefix = accel_uses_host_cpuid()
|
||||
@@ -7570,13 +7602,10 @@ static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose)
|
||||
*/
|
||||
if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
|
||||
kvm_enabled()) {
|
||||
- uint32_t eax_0, ebx_0, ecx_0, edx_0_unused;
|
||||
- uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused;
|
||||
-
|
||||
x86_cpu_get_supported_cpuid(0x14, 0,
|
||||
- &eax_0, &ebx_0, &ecx_0, &edx_0_unused);
|
||||
+ &eax_0, &ebx_0, &ecx_0, &edx_0);
|
||||
x86_cpu_get_supported_cpuid(0x14, 1,
|
||||
- &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused);
|
||||
+ &eax_1, &ebx_1, &ecx_1, &edx_1);
|
||||
|
||||
if (!eax_0 ||
|
||||
((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
|
||||
@@ -7597,7 +7626,27 @@ static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose)
|
||||
}
|
||||
}
|
||||
|
||||
- return x86_cpu_have_filtered_features(cpu);
|
||||
+ have_filtered_features = x86_cpu_have_filtered_features(cpu);
|
||||
+
|
||||
+ if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) {
|
||||
+ x86_cpu_get_supported_cpuid(0x24, 0,
|
||||
+ &eax_0, &ebx_0, &ecx_0, &edx_0);
|
||||
+ uint8_t version = ebx_0 & 0xff;
|
||||
+
|
||||
+ if (version < env->avx10_version) {
|
||||
+ if (prefix) {
|
||||
+ warn_report("%s: avx10.%d. Adjust to avx10.%d",
|
||||
+ prefix, env->avx10_version, version);
|
||||
+ }
|
||||
+ env->avx10_version = version;
|
||||
+ have_filtered_features = true;
|
||||
+ }
|
||||
+ } else if (env->avx10_version && prefix) {
|
||||
+ warn_report("%s: avx10.%d.", prefix, env->avx10_version);
|
||||
+ have_filtered_features = true;
|
||||
+ }
|
||||
+
|
||||
+ return have_filtered_features;
|
||||
}
|
||||
|
||||
static void x86_cpu_hyperv_realize(X86CPU *cpu)
|
||||
@@ -8378,6 +8427,7 @@ static Property x86_cpu_properties[] = {
|
||||
DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
|
||||
DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
|
||||
DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
|
||||
+ DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0),
|
||||
DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
|
||||
DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
|
||||
DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
|
||||
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
|
||||
index 14edd57a37..591113349d 100644
|
||||
--- a/target/i386/cpu.h
|
||||
+++ b/target/i386/cpu.h
|
||||
@@ -972,6 +972,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
|
||||
#define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8)
|
||||
/* PREFETCHIT0/1 Instructions */
|
||||
#define CPUID_7_1_EDX_PREFETCHITI (1U << 14)
|
||||
+/* Support for Advanced Vector Extensions 10 */
|
||||
+#define CPUID_7_1_EDX_AVX10 (1U << 19)
|
||||
/* Flexible return and event delivery (FRED) */
|
||||
#define CPUID_7_1_EAX_FRED (1U << 17)
|
||||
/* Load into IA32_KERNEL_GS_BASE (LKGS) */
|
||||
@@ -1914,6 +1916,8 @@ typedef struct CPUArchState {
|
||||
uint32_t cpuid_vendor3;
|
||||
uint32_t cpuid_version;
|
||||
FeatureWordArray features;
|
||||
+ /* AVX10 version */
|
||||
+ uint8_t avx10_version;
|
||||
/* Features that were explicitly enabled/disabled */
|
||||
FeatureWordArray user_features;
|
||||
uint32_t cpuid_model[12];
|
||||
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
|
||||
index 814f93da19..d0329a4ed7 100644
|
||||
--- a/target/i386/kvm/kvm.c
|
||||
+++ b/target/i386/kvm/kvm.c
|
||||
@@ -1891,7 +1891,8 @@ static uint32_t kvm_x86_build_cpuid(CPUX86State *env,
|
||||
case 0x7:
|
||||
case 0x14:
|
||||
case 0x1d:
|
||||
- case 0x1e: {
|
||||
+ case 0x1e:
|
||||
+ case 0x24: {
|
||||
uint32_t times;
|
||||
|
||||
c->function = i;
|
||||
--
|
||||
2.48.0
|
||||
|
||||
91
kvm-target-i386-add-CPUID.24-features-for-AVX10.patch
Normal file
91
kvm-target-i386-add-CPUID.24-features-for-AVX10.patch
Normal file
@ -0,0 +1,91 @@
|
||||
From 4d68991ce4c1bbc6acf74d249c8cea504560780f Mon Sep 17 00:00:00 2001
|
||||
From: Tao Su <tao1.su@linux.intel.com>
|
||||
Date: Thu, 31 Oct 2024 16:52:30 +0800
|
||||
Subject: [PATCH 05/11] target/i386: add CPUID.24 features for AVX10
|
||||
|
||||
RH-Author: Paolo Bonzini <pbonzini@redhat.com>
|
||||
RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
|
||||
RH-Jira: RHEL-30316 RHEL-45111
|
||||
RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
|
||||
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
||||
RH-Commit: [5/9] e70e79b79037c77df17a028b7451b92bde042c0e (bonzini/rhel-qemu-kvm)
|
||||
|
||||
Introduce features for the supported vector bit lengths.
|
||||
|
||||
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
|
||||
Link: https://lore.kernel.org/r/20241028024512.156724-3-tao1.su@linux.intel.com
|
||||
Link: https://lore.kernel.org/r/20241028024512.156724-4-tao1.su@linux.intel.com
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
|
||||
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
|
||||
Link: https://lore.kernel.org/r/20241031085233.425388-6-tao1.su@linux.intel.com
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
(cherry picked from commit 2d055b8fe11ee567c2ae8047311fd83697e494b6)
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
---
|
||||
target/i386/cpu.c | 15 +++++++++++++++
|
||||
target/i386/cpu.h | 8 ++++++++
|
||||
2 files changed, 23 insertions(+)
|
||||
|
||||
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
||||
index 6c041ec5af..b6021be50d 100644
|
||||
--- a/target/i386/cpu.c
|
||||
+++ b/target/i386/cpu.c
|
||||
@@ -902,6 +902,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
|
||||
#define TCG_SGX_12_0_EAX_FEATURES 0
|
||||
#define TCG_SGX_12_0_EBX_FEATURES 0
|
||||
#define TCG_SGX_12_1_EAX_FEATURES 0
|
||||
+#define TCG_24_0_EBX_FEATURES 0
|
||||
|
||||
#if defined CONFIG_USER_ONLY
|
||||
#define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \
|
||||
@@ -1167,6 +1168,20 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
||||
},
|
||||
.tcg_features = TCG_7_2_EDX_FEATURES,
|
||||
},
|
||||
+ [FEAT_24_0_EBX] = {
|
||||
+ .type = CPUID_FEATURE_WORD,
|
||||
+ .feat_names = {
|
||||
+ [16] = "avx10-128",
|
||||
+ [17] = "avx10-256",
|
||||
+ [18] = "avx10-512",
|
||||
+ },
|
||||
+ .cpuid = {
|
||||
+ .eax = 0x24,
|
||||
+ .needs_ecx = true, .ecx = 0,
|
||||
+ .reg = R_EBX,
|
||||
+ },
|
||||
+ .tcg_features = TCG_24_0_EBX_FEATURES,
|
||||
+ },
|
||||
[FEAT_8000_0007_EDX] = {
|
||||
.type = CPUID_FEATURE_WORD,
|
||||
.feat_names = {
|
||||
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
|
||||
index 591113349d..c60290b8d5 100644
|
||||
--- a/target/i386/cpu.h
|
||||
+++ b/target/i386/cpu.h
|
||||
@@ -666,6 +666,7 @@ typedef enum FeatureWord {
|
||||
FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */
|
||||
FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */
|
||||
FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */
|
||||
+ FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */
|
||||
FEATURE_WORDS,
|
||||
} FeatureWord;
|
||||
|
||||
@@ -990,6 +991,13 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
|
||||
/* Packets which contain IP payload have LIP values */
|
||||
#define CPUID_14_0_ECX_LIP (1U << 31)
|
||||
|
||||
+/* AVX10 128-bit vector support is present */
|
||||
+#define CPUID_24_0_EBX_AVX10_128 (1U << 16)
|
||||
+/* AVX10 256-bit vector support is present */
|
||||
+#define CPUID_24_0_EBX_AVX10_256 (1U << 17)
|
||||
+/* AVX10 512-bit vector support is present */
|
||||
+#define CPUID_24_0_EBX_AVX10_512 (1U << 18)
|
||||
+
|
||||
/* RAS Features */
|
||||
#define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0)
|
||||
#define CPUID_8000_0007_EBX_SUCCOR (1U << 1)
|
||||
--
|
||||
2.48.0
|
||||
|
||||
43
kvm-target-i386-add-sha512-sm3-sm4-feature-bits.patch
Normal file
43
kvm-target-i386-add-sha512-sm3-sm4-feature-bits.patch
Normal file
@ -0,0 +1,43 @@
|
||||
From 3edc5689dd2b5a55655ab99e0153ad85ab50d773 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Bonzini <pbonzini@redhat.com>
|
||||
Date: Wed, 3 Jul 2024 13:42:49 +0200
|
||||
Subject: [PATCH 09/11] target/i386: add sha512, sm3, sm4 feature bits
|
||||
|
||||
RH-Author: Paolo Bonzini <pbonzini@redhat.com>
|
||||
RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
|
||||
RH-Jira: RHEL-30316 RHEL-45111
|
||||
RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
|
||||
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
||||
RH-Commit: [9/9] ec773b43841f1a38f0e5829c1d66cd5b517c5267 (bonzini/rhel-qemu-kvm)
|
||||
|
||||
Status: queued for QEMU 10.0
|
||||
|
||||
SHA512, SM3, SM4 (CPUID[EAX=7,ECX=1).EAX bits 0 to 2) is supported by
|
||||
Clearwater Forest processor, add it to QEMU as it does not need any
|
||||
specific enablement.
|
||||
|
||||
See https://lore.kernel.org/kvm/20241105054825.870939-1-tao1.su@linux.intel.com/
|
||||
for reference.
|
||||
|
||||
Reviewed-by: Tao Su <tao1.su@linux.intel.com>
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
---
|
||||
target/i386/cpu.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
||||
index ad368252d8..a70a3aa670 100644
|
||||
--- a/target/i386/cpu.c
|
||||
+++ b/target/i386/cpu.c
|
||||
@@ -1114,7 +1114,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
||||
[FEAT_7_1_EAX] = {
|
||||
.type = CPUID_FEATURE_WORD,
|
||||
.feat_names = {
|
||||
- NULL, NULL, NULL, NULL,
|
||||
+ "sha512", "sm3", "sm4", NULL,
|
||||
"avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
|
||||
NULL, NULL, "fzrm", "fsrs",
|
||||
"fsrc", NULL, NULL, NULL,
|
||||
--
|
||||
2.48.0
|
||||
|
||||
@ -0,0 +1,50 @@
|
||||
From 9ed7a4e63c88a9b2afe51ffad36c12b174ad6e7a Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Bonzini <pbonzini@redhat.com>
|
||||
Date: Thu, 31 Oct 2024 16:52:26 +0800
|
||||
Subject: [PATCH 01/11] target/i386: cpu: set correct supported XCR0 features
|
||||
for TCG
|
||||
|
||||
RH-Author: Paolo Bonzini <pbonzini@redhat.com>
|
||||
RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
|
||||
RH-Jira: RHEL-30316 RHEL-45111
|
||||
RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
|
||||
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
||||
RH-Commit: [1/9] a27738f95f7c00915cd16288e469276a879f6bdf (bonzini/rhel-qemu-kvm)
|
||||
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
|
||||
Link: https://lore.kernel.org/r/20241031085233.425388-2-tao1.su@linux.intel.com
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
(cherry picked from commit 33098002a838a0450f243f5e17463aca700e923d)
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
---
|
||||
target/i386/cpu.c | 6 ++++--
|
||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
||||
index ed278dd4a1..cff7ae1c54 100644
|
||||
--- a/target/i386/cpu.c
|
||||
+++ b/target/i386/cpu.c
|
||||
@@ -1297,7 +1297,9 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
||||
.needs_ecx = true, .ecx = 0,
|
||||
.reg = R_EAX,
|
||||
},
|
||||
- .tcg_features = ~0U,
|
||||
+ .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK |
|
||||
+ XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
|
||||
+ XSTATE_PKRU_MASK,
|
||||
.migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
|
||||
XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
|
||||
XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
|
||||
@@ -1310,7 +1312,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
||||
.needs_ecx = true, .ecx = 0,
|
||||
.reg = R_EDX,
|
||||
},
|
||||
- .tcg_features = ~0U,
|
||||
+ .tcg_features = 0U,
|
||||
},
|
||||
/*Below are MSR exposed features*/
|
||||
[FEAT_ARCH_CAPABILITIES] = {
|
||||
--
|
||||
2.48.0
|
||||
|
||||
117
kvm-target-i386-do-not-rely-on-ExtSaveArea-for-accelerat.patch
Normal file
117
kvm-target-i386-do-not-rely-on-ExtSaveArea-for-accelerat.patch
Normal file
@ -0,0 +1,117 @@
|
||||
From a6d31ad703d50bce0c0fb054356f50e480cf5a4d Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Bonzini <pbonzini@redhat.com>
|
||||
Date: Thu, 31 Oct 2024 16:52:27 +0800
|
||||
Subject: [PATCH 02/11] target/i386: do not rely on ExtSaveArea for
|
||||
accelerator-supported XCR0 bits
|
||||
|
||||
RH-Author: Paolo Bonzini <pbonzini@redhat.com>
|
||||
RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
|
||||
RH-Jira: RHEL-30316 RHEL-45111
|
||||
RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
|
||||
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
||||
RH-Commit: [2/9] e53b5e7a58018c0635012382d93819dbe7cb6201 (bonzini/rhel-qemu-kvm)
|
||||
|
||||
Right now, QEMU is using the "feature" and "bits" fields of ExtSaveArea
|
||||
to query the accelerator for the support status of extended save areas.
|
||||
This is a problem for AVX10, which attaches two feature bits (AVX512F
|
||||
and AVX10) to the same extended save states.
|
||||
|
||||
To keep the AVX10 hacks to the minimum, limit usage of esa->features
|
||||
and esa->bits. Instead, just query the accelerator for the 0xD leaf.
|
||||
Do it in common code and clear esa->size if an extended save state is
|
||||
unsupported.
|
||||
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
|
||||
Link: https://lore.kernel.org/r/20241031085233.425388-3-tao1.su@linux.intel.com
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
(cherry picked from commit b888c7807049cc044d10d70139cb945202fb7cd2)
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
---
|
||||
target/i386/cpu.c | 33 +++++++++++++++++++++++++++++++--
|
||||
target/i386/kvm/kvm-cpu.c | 4 ----
|
||||
2 files changed, 31 insertions(+), 6 deletions(-)
|
||||
|
||||
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
||||
index cff7ae1c54..4e240ab181 100644
|
||||
--- a/target/i386/cpu.c
|
||||
+++ b/target/i386/cpu.c
|
||||
@@ -7088,6 +7088,15 @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
|
||||
#endif
|
||||
}
|
||||
|
||||
+static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa)
|
||||
+{
|
||||
+ if (!esa->size) {
|
||||
+ return false;
|
||||
+ }
|
||||
+
|
||||
+ return (env->features[esa->feature] & esa->bits);
|
||||
+}
|
||||
+
|
||||
static void x86_cpu_reset_hold(Object *obj, ResetType type)
|
||||
{
|
||||
CPUState *cs = CPU(obj);
|
||||
@@ -7196,7 +7205,7 @@ static void x86_cpu_reset_hold(Object *obj, ResetType type)
|
||||
if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) {
|
||||
continue;
|
||||
}
|
||||
- if (env->features[esa->feature] & esa->bits) {
|
||||
+ if (cpuid_has_xsave_feature(env, esa)) {
|
||||
xcr0 |= 1ull << i;
|
||||
}
|
||||
}
|
||||
@@ -7334,7 +7343,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu)
|
||||
mask = 0;
|
||||
for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
|
||||
const ExtSaveArea *esa = &x86_ext_save_areas[i];
|
||||
- if (env->features[esa->feature] & esa->bits) {
|
||||
+ if (cpuid_has_xsave_feature(env, esa)) {
|
||||
mask |= (1ULL << i);
|
||||
}
|
||||
}
|
||||
@@ -8005,6 +8014,26 @@ static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc,
|
||||
|
||||
static void x86_cpu_post_initfn(Object *obj)
|
||||
{
|
||||
+ static bool first = true;
|
||||
+ uint64_t supported_xcr0;
|
||||
+ int i;
|
||||
+
|
||||
+ if (first) {
|
||||
+ first = false;
|
||||
+
|
||||
+ supported_xcr0 =
|
||||
+ ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) |
|
||||
+ x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO);
|
||||
+
|
||||
+ for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) {
|
||||
+ ExtSaveArea *esa = &x86_ext_save_areas[i];
|
||||
+
|
||||
+ if (!(supported_xcr0 & (1 << i))) {
|
||||
+ esa->size = 0;
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
accel_cpu_instance_init(CPU(obj));
|
||||
}
|
||||
|
||||
diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
|
||||
index 684e731cbc..961b87e98e 100644
|
||||
--- a/target/i386/kvm/kvm-cpu.c
|
||||
+++ b/target/i386/kvm/kvm-cpu.c
|
||||
@@ -143,10 +143,6 @@ static void kvm_cpu_xsave_init(void)
|
||||
if (!esa->size) {
|
||||
continue;
|
||||
}
|
||||
- if ((x86_cpu_get_supported_feature_word(NULL, esa->feature) & esa->bits)
|
||||
- != esa->bits) {
|
||||
- continue;
|
||||
- }
|
||||
host_cpuid(0xd, i, &eax, &ebx, &ecx, &edx);
|
||||
if (eax != 0) {
|
||||
assert(esa->size == eax);
|
||||
--
|
||||
2.48.0
|
||||
|
||||
@ -0,0 +1,83 @@
|
||||
From 6fd15c104cb9475311f68156ebf3603d406b90fa Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Bonzini <pbonzini@redhat.com>
|
||||
Date: Thu, 31 Oct 2024 16:52:28 +0800
|
||||
Subject: [PATCH 03/11] target/i386: return bool from x86_cpu_filter_features
|
||||
|
||||
RH-Author: Paolo Bonzini <pbonzini@redhat.com>
|
||||
RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
|
||||
RH-Jira: RHEL-30316 RHEL-45111
|
||||
RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
|
||||
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
||||
RH-Commit: [3/9] a5cd846d3ade44b289d99b2742323f421fe30f8b (bonzini/rhel-qemu-kvm)
|
||||
|
||||
Prepare for filtering non-boolean features such as AVX10 version.
|
||||
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
|
||||
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
|
||||
Link: https://lore.kernel.org/r/20241031085233.425388-4-tao1.su@linux.intel.com
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
(cherry picked from commit 3507c6f04606593711408a6d26141bdbceff9377)
|
||||
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||
---
|
||||
target/i386/cpu.c | 20 +++++++++++---------
|
||||
1 file changed, 11 insertions(+), 9 deletions(-)
|
||||
|
||||
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
||||
index 4e240ab181..982d9bd7f6 100644
|
||||
--- a/target/i386/cpu.c
|
||||
+++ b/target/i386/cpu.c
|
||||
@@ -5837,7 +5837,7 @@ static void x86_cpu_parse_featurestr(const char *typename, char *features,
|
||||
}
|
||||
}
|
||||
|
||||
-static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
|
||||
+static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose);
|
||||
|
||||
/* Build a list with the name of all features on a feature word array */
|
||||
static void x86_cpu_list_feature_names(FeatureWordArray features,
|
||||
@@ -7542,9 +7542,9 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
|
||||
* Finishes initialization of CPUID data, filters CPU feature
|
||||
* words based on host availability of each feature.
|
||||
*
|
||||
- * Returns: 0 if all flags are supported by the host, non-zero otherwise.
|
||||
+ * Returns: true if any flag is not supported by the host, false otherwise.
|
||||
*/
|
||||
-static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
|
||||
+static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose)
|
||||
{
|
||||
CPUX86State *env = &cpu->env;
|
||||
FeatureWord w;
|
||||
@@ -7596,6 +7596,8 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
|
||||
mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
|
||||
}
|
||||
}
|
||||
+
|
||||
+ return x86_cpu_have_filtered_features(cpu);
|
||||
}
|
||||
|
||||
static void x86_cpu_hyperv_realize(X86CPU *cpu)
|
||||
@@ -7693,14 +7695,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
|
||||
}
|
||||
}
|
||||
|
||||
- x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
|
||||
-
|
||||
- if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
|
||||
- error_setg(&local_err,
|
||||
- accel_uses_host_cpuid() ?
|
||||
+ if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) {
|
||||
+ if (cpu->enforce_cpuid) {
|
||||
+ error_setg(&local_err,
|
||||
+ accel_uses_host_cpuid() ?
|
||||
"Host doesn't support requested features" :
|
||||
"TCG doesn't support requested features");
|
||||
- goto out;
|
||||
+ goto out;
|
||||
+ }
|
||||
}
|
||||
|
||||
/* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
|
||||
--
|
||||
2.48.0
|
||||
|
||||
48
kvm-tests-qtest-disable-most-pauth-tests.patch
Normal file
48
kvm-tests-qtest-disable-most-pauth-tests.patch
Normal file
@ -0,0 +1,48 @@
|
||||
From 2cd838efaf2345497efab21fee689ff43d511f1c Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Ott <sebott@redhat.com>
|
||||
Date: Thu, 23 Jan 2025 08:12:35 -0500
|
||||
Subject: [PATCH 11/11] tests/qtest: disable most pauth tests
|
||||
|
||||
RH-Author: Sebastian Ott <sebott@redhat.com>
|
||||
RH-MergeRequest: 330: arm: disable pauth for virt-rhel9*
|
||||
RH-Jira: RHEL-75782
|
||||
RH-Acked-by: Eric Auger <eric.auger@redhat.com>
|
||||
RH-Acked-by: Kashyap Chamarthy <None>
|
||||
RH-Acked-by: Gavin Shan <gshan@redhat.com>
|
||||
RH-Commit: [2/2] 373738aec33bf2dcaa47563b3c06595b21dca5be (seott1/cos-qemu-kvm)
|
||||
|
||||
Since pauth is disabled for virt-rhel9* machine types (aliased via virt)
|
||||
the following assertions will trigger and need to be disabled as well:
|
||||
assert_has_feature_enabled(qts, cpu_type, "pauth");
|
||||
assert_set_feature(qts, cpu_type, "pauth-impdef", true);
|
||||
assert_set_feature(qts, cpu_type, "pauth-qarma3", true);
|
||||
|
||||
Signed-off-by: Sebastian Ott <sebott@redhat.com>
|
||||
JIRA: https://issues.redhat.com/browse/RHEL-75782
|
||||
---
|
||||
tests/qtest/arm-cpu-features.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
|
||||
index 3016e6233c..6b680578a6 100644
|
||||
--- a/tests/qtest/arm-cpu-features.c
|
||||
+++ b/tests/qtest/arm-cpu-features.c
|
||||
@@ -416,6 +416,7 @@ static void sve_tests_sve_off_kvm(const void *data)
|
||||
|
||||
static void pauth_tests_default(QTestState *qts, const char *cpu_type)
|
||||
{
|
||||
+#if 0 /* Disabled for Red Hat Enterprise Linux */
|
||||
assert_has_feature_enabled(qts, cpu_type, "pauth");
|
||||
assert_has_feature_disabled(qts, cpu_type, "pauth-impdef");
|
||||
assert_has_feature_disabled(qts, cpu_type, "pauth-qarma3");
|
||||
@@ -425,6 +426,7 @@ static void pauth_tests_default(QTestState *qts, const char *cpu_type)
|
||||
assert_set_feature(qts, cpu_type, "pauth-impdef", false);
|
||||
assert_set_feature(qts, cpu_type, "pauth-qarma3", true);
|
||||
assert_set_feature(qts, cpu_type, "pauth-qarma3", false);
|
||||
+#endif /* disabled for RHEL */
|
||||
assert_error(qts, cpu_type,
|
||||
"cannot enable pauth-impdef or pauth-qarma3 without pauth",
|
||||
"{ 'pauth': false, 'pauth-impdef': true }");
|
||||
--
|
||||
2.48.0
|
||||
|
||||
@ -149,7 +149,7 @@ Obsoletes: %{name}-block-ssh <= %{epoch}:%{version} \
|
||||
Summary: QEMU is a machine emulator and virtualizer
|
||||
Name: qemu-kvm
|
||||
Version: 9.1.0
|
||||
Release: 11%{?rcrel}%{?dist}%{?cc_suffix}
|
||||
Release: 12%{?rcrel}%{?dist}%{?cc_suffix}
|
||||
# Epoch because we pushed a qemu-1.0 package. AIUI this can't ever be dropped
|
||||
# Epoch 15 used for RHEL 8
|
||||
# Epoch 17 used for RHEL 9 (due to release versioning offset in RHEL 8.5)
|
||||
@ -352,6 +352,37 @@ Patch105: kvm-qemu-ga-Optimize-freeze-hook-script-logic-of-logging.patch
|
||||
Patch106: kvm-qga-Add-log-to-guest-fsfreeze-thaw-command.patch
|
||||
# For RHEL-65616 - Failed to hot add PCIe device behind xio3130 downstream port
|
||||
Patch107: kvm-pci-ensure-valid-link-status-bits-for-downstream-por.patch
|
||||
# For RHEL-30316 - [Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support
|
||||
# For RHEL-45111 - [Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4
|
||||
Patch108: kvm-target-i386-cpu-set-correct-supported-XCR0-features-.patch
|
||||
# For RHEL-30316 - [Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support
|
||||
# For RHEL-45111 - [Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4
|
||||
Patch109: kvm-target-i386-do-not-rely-on-ExtSaveArea-for-accelerat.patch
|
||||
# For RHEL-30316 - [Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support
|
||||
# For RHEL-45111 - [Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4
|
||||
Patch110: kvm-target-i386-return-bool-from-x86_cpu_filter_features.patch
|
||||
# For RHEL-30316 - [Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support
|
||||
# For RHEL-45111 - [Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4
|
||||
Patch111: kvm-target-i386-add-AVX10-feature-and-AVX10-version-prop.patch
|
||||
# For RHEL-30316 - [Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support
|
||||
# For RHEL-45111 - [Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4
|
||||
Patch112: kvm-target-i386-add-CPUID.24-features-for-AVX10.patch
|
||||
# For RHEL-30316 - [Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support
|
||||
# For RHEL-45111 - [Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4
|
||||
Patch113: kvm-target-i386-Add-feature-dependencies-for-AVX10.patch
|
||||
# For RHEL-30316 - [Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support
|
||||
# For RHEL-45111 - [Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4
|
||||
Patch114: kvm-target-i386-Add-AVX512-state-when-AVX10-is-supported.patch
|
||||
# For RHEL-30316 - [Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support
|
||||
# For RHEL-45111 - [Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4
|
||||
Patch115: kvm-target-i386-Introduce-GraniteRapids-v2-model.patch
|
||||
# For RHEL-30316 - [Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support
|
||||
# For RHEL-45111 - [Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4
|
||||
Patch116: kvm-target-i386-add-sha512-sm3-sm4-feature-bits.patch
|
||||
# For RHEL-75782 - [Nvidia "Grace"] Lack of "PAuth" CPU feature results in live migration failure from RHEL 9.6 to 10
|
||||
Patch117: kvm-arm-disable-pauth-for-virt-rhel9.patch
|
||||
# For RHEL-75782 - [Nvidia "Grace"] Lack of "PAuth" CPU feature results in live migration failure from RHEL 9.6 to 10
|
||||
Patch118: kvm-tests-qtest-disable-most-pauth-tests.patch
|
||||
|
||||
%if %{have_clang}
|
||||
BuildRequires: clang
|
||||
@ -1418,6 +1449,25 @@ useradd -r -u 107 -g qemu -G kvm -d / -s /sbin/nologin \
|
||||
%endif
|
||||
|
||||
%changelog
|
||||
* Mon Jan 27 2025 Jon Maloy <jmaloy@redhat.com> - 9.1.0-12
|
||||
- kvm-target-i386-cpu-set-correct-supported-XCR0-features-.patch [RHEL-30316 RHEL-45111]
|
||||
- kvm-target-i386-do-not-rely-on-ExtSaveArea-for-accelerat.patch [RHEL-30316 RHEL-45111]
|
||||
- kvm-target-i386-return-bool-from-x86_cpu_filter_features.patch [RHEL-30316 RHEL-45111]
|
||||
- kvm-target-i386-add-AVX10-feature-and-AVX10-version-prop.patch [RHEL-30316 RHEL-45111]
|
||||
- kvm-target-i386-add-CPUID.24-features-for-AVX10.patch [RHEL-30316 RHEL-45111]
|
||||
- kvm-target-i386-Add-feature-dependencies-for-AVX10.patch [RHEL-30316 RHEL-45111]
|
||||
- kvm-target-i386-Add-AVX512-state-when-AVX10-is-supported.patch [RHEL-30316 RHEL-45111]
|
||||
- kvm-target-i386-Introduce-GraniteRapids-v2-model.patch [RHEL-30316 RHEL-45111]
|
||||
- kvm-target-i386-add-sha512-sm3-sm4-feature-bits.patch [RHEL-30316 RHEL-45111]
|
||||
- kvm-arm-disable-pauth-for-virt-rhel9.patch [RHEL-75782]
|
||||
- kvm-tests-qtest-disable-most-pauth-tests.patch [RHEL-75782]
|
||||
- Resolves: RHEL-30316
|
||||
([Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support)
|
||||
- Resolves: RHEL-45111
|
||||
([Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4)
|
||||
- Resolves: RHEL-75782
|
||||
([Nvidia "Grace"] Lack of "PAuth" CPU feature results in live migration failure from RHEL 9.6 to 10)
|
||||
|
||||
* Tue Jan 21 2025 Jon Maloy <jmaloy@redhat.com> - 9.1.0-11
|
||||
- kvm-pci-ensure-valid-link-status-bits-for-downstream-por.patch [RHEL-65616]
|
||||
- Resolves: RHEL-65616
|
||||
|
||||
Loading…
Reference in New Issue
Block a user