cfbebe833a
- kvm-target-i386-cpu-set-correct-supported-XCR0-features-.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-do-not-rely-on-ExtSaveArea-for-accelerat.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-return-bool-from-x86_cpu_filter_features.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-AVX10-feature-and-AVX10-version-prop.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-CPUID.24-features-for-AVX10.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Add-feature-dependencies-for-AVX10.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Add-AVX512-state-when-AVX10-is-supported.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Introduce-GraniteRapids-v2-model.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-sha512-sm3-sm4-feature-bits.patch [RHEL-30316 RHEL-45111] - kvm-arm-disable-pauth-for-virt-rhel9.patch [RHEL-75782] - kvm-tests-qtest-disable-most-pauth-tests.patch [RHEL-75782] - Resolves: RHEL-30316 ([Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support) - Resolves: RHEL-45111 ([Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4) - Resolves: RHEL-75782 ([Nvidia "Grace"] Lack of "PAuth" CPU feature results in live migration failure from RHEL 9.6 to 10)
92 lines
3.4 KiB
Diff
92 lines
3.4 KiB
Diff
From 4d68991ce4c1bbc6acf74d249c8cea504560780f Mon Sep 17 00:00:00 2001
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From: Tao Su <tao1.su@linux.intel.com>
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Date: Thu, 31 Oct 2024 16:52:30 +0800
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Subject: [PATCH 05/11] target/i386: add CPUID.24 features for AVX10
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
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RH-Jira: RHEL-30316 RHEL-45111
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [5/9] e70e79b79037c77df17a028b7451b92bde042c0e (bonzini/rhel-qemu-kvm)
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Introduce features for the supported vector bit lengths.
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Link: https://lore.kernel.org/r/20241028024512.156724-3-tao1.su@linux.intel.com
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Link: https://lore.kernel.org/r/20241028024512.156724-4-tao1.su@linux.intel.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Tested-by: Xuelian Guo <xuelian.guo@intel.com>
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Link: https://lore.kernel.org/r/20241031085233.425388-6-tao1.su@linux.intel.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 2d055b8fe11ee567c2ae8047311fd83697e494b6)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/cpu.c | 15 +++++++++++++++
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target/i386/cpu.h | 8 ++++++++
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2 files changed, 23 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 6c041ec5af..b6021be50d 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -902,6 +902,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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#define TCG_SGX_12_0_EAX_FEATURES 0
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#define TCG_SGX_12_0_EBX_FEATURES 0
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#define TCG_SGX_12_1_EAX_FEATURES 0
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+#define TCG_24_0_EBX_FEATURES 0
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#if defined CONFIG_USER_ONLY
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#define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \
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@@ -1167,6 +1168,20 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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},
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.tcg_features = TCG_7_2_EDX_FEATURES,
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},
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+ [FEAT_24_0_EBX] = {
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+ .type = CPUID_FEATURE_WORD,
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+ .feat_names = {
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+ [16] = "avx10-128",
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+ [17] = "avx10-256",
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+ [18] = "avx10-512",
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+ },
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+ .cpuid = {
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+ .eax = 0x24,
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+ .needs_ecx = true, .ecx = 0,
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+ .reg = R_EBX,
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+ },
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+ .tcg_features = TCG_24_0_EBX_FEATURES,
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+ },
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[FEAT_8000_0007_EDX] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 591113349d..c60290b8d5 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -666,6 +666,7 @@ typedef enum FeatureWord {
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FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */
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FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */
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FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */
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+ FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */
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FEATURE_WORDS,
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} FeatureWord;
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@@ -990,6 +991,13 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
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/* Packets which contain IP payload have LIP values */
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#define CPUID_14_0_ECX_LIP (1U << 31)
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+/* AVX10 128-bit vector support is present */
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+#define CPUID_24_0_EBX_AVX10_128 (1U << 16)
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+/* AVX10 256-bit vector support is present */
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+#define CPUID_24_0_EBX_AVX10_256 (1U << 17)
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+/* AVX10 512-bit vector support is present */
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+#define CPUID_24_0_EBX_AVX10_512 (1U << 18)
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+
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/* RAS Features */
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#define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0)
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#define CPUID_8000_0007_EBX_SUCCOR (1U << 1)
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--
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2.48.0
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