cfbebe833a
- kvm-target-i386-cpu-set-correct-supported-XCR0-features-.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-do-not-rely-on-ExtSaveArea-for-accelerat.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-return-bool-from-x86_cpu_filter_features.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-AVX10-feature-and-AVX10-version-prop.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-CPUID.24-features-for-AVX10.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Add-feature-dependencies-for-AVX10.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Add-AVX512-state-when-AVX10-is-supported.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-Introduce-GraniteRapids-v2-model.patch [RHEL-30316 RHEL-45111] - kvm-target-i386-add-sha512-sm3-sm4-feature-bits.patch [RHEL-30316 RHEL-45111] - kvm-arm-disable-pauth-for-virt-rhel9.patch [RHEL-75782] - kvm-tests-qtest-disable-most-pauth-tests.patch [RHEL-75782] - Resolves: RHEL-30316 ([Intel 9.6 FEAT] [GNR] Virt-QEMU: Add AVX10.1 instruction support) - Resolves: RHEL-45111 ([Intel 9.6 FEAT] [CWF][DMR] Virt-QEMU: Advertise new instructions SHA2-512NI, SM3, and SM4) - Resolves: RHEL-75782 ([Nvidia "Grace"] Lack of "PAuth" CPU feature results in live migration failure from RHEL 9.6 to 10)
90 lines
3.8 KiB
Diff
90 lines
3.8 KiB
Diff
From eaa0a5dae408cb2848fcd2a8fe3999cba992ddef Mon Sep 17 00:00:00 2001
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From: Tao Su <tao1.su@linux.intel.com>
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Date: Thu, 31 Oct 2024 16:52:31 +0800
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Subject: [PATCH 06/11] target/i386: Add feature dependencies for AVX10
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets.
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RH-Jira: RHEL-30316 RHEL-45111
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [6/9] cbe290c488128b5b5a8f11b29d90399fb6172c57 (bonzini/rhel-qemu-kvm)
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Since the highest supported vector length for a processor implies that
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all lesser vector lengths are also supported, add the dependencies of
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the supported vector lengths. If all vector lengths aren't supported,
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clear AVX10 enable bit as well.
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Note that the order of AVX10 related dependencies should be kept as:
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CPUID_24_0_EBX_AVX10_128 -> CPUID_24_0_EBX_AVX10_256,
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CPUID_24_0_EBX_AVX10_256 -> CPUID_24_0_EBX_AVX10_512,
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CPUID_24_0_EBX_AVX10_VL_MASK -> CPUID_7_1_EDX_AVX10,
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CPUID_7_1_EDX_AVX10 -> CPUID_24_0_EBX,
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so that prevent user from setting weird CPUID combinations, e.g. 256-bits
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and 512-bits are supported but 128-bits is not, no vector lengths are
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supported but AVX10 enable bit is still set.
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Since AVX10_128 will be reserved as 1, adding these dependencies has the
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bonus that when user sets -cpu host,-avx10-128, CPUID_7_1_EDX_AVX10 and
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CPUID_24_0_EBX will be disabled automatically.
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Tested-by: Xuelian Guo <xuelian.guo@intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Link: https://lore.kernel.org/r/20241028024512.156724-5-tao1.su@linux.intel.com
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Link: https://lore.kernel.org/r/20241031085233.425388-7-tao1.su@linux.intel.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 150ab84b2d0083e6af344cca70290614d4fe568d)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/cpu.c | 16 ++++++++++++++++
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target/i386/cpu.h | 4 ++++
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2 files changed, 20 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index b6021be50d..71d1f362e2 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1766,6 +1766,22 @@ static FeatureDep feature_dependencies[] = {
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.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX },
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.to = { FEAT_SGX_12_1_EAX, ~0ull },
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},
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+ {
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+ .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 },
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+ .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 },
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+ },
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+ {
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+ .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 },
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+ .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 },
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+ },
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+ {
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+ .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK },
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+ .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
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+ },
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+ {
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+ .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
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+ .to = { FEAT_24_0_EBX, ~0ull },
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+ },
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};
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typedef struct X86RegisterInfo32 {
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index c60290b8d5..4da9ed5930 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -997,6 +997,10 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
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#define CPUID_24_0_EBX_AVX10_256 (1U << 17)
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/* AVX10 512-bit vector support is present */
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#define CPUID_24_0_EBX_AVX10_512 (1U << 18)
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+/* AVX10 vector length support mask */
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+#define CPUID_24_0_EBX_AVX10_VL_MASK (CPUID_24_0_EBX_AVX10_128 | \
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+ CPUID_24_0_EBX_AVX10_256 | \
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+ CPUID_24_0_EBX_AVX10_512)
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/* RAS Features */
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#define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0)
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--
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2.48.0
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