import pciutils-3.7.0-1.el8
This commit is contained in:
CentOS Sources
parent
31159a1b07
commit
e51829b5ba
2
.gitignore
vendored
2
.gitignore
vendored
@ -1 +1 @@
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SOURCES/pciutils-3.6.4.tar.xz
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SOURCES/pciutils-3.7.0.tar.xz
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@ -1 +1 @@
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977b33f6beb8bbfd72a1ca4ac19ee50771b5924f SOURCES/pciutils-3.6.4.tar.xz
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f7d6860ffe405b4ebb23b013866a64c9f80c2fa3 SOURCES/pciutils-3.7.0.tar.xz
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444
SOURCES/pciutils-3.7.0-decodercec.patch
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444
SOURCES/pciutils-3.7.0-decodercec.patch
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@ -0,0 +1,444 @@
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From e12bd01eea67ca8cf539263124843ba281eb6ecc Mon Sep 17 00:00:00 2001
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From: Sean V Kelley <sean.v.kelley@linux.intel.com>
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Date: Wed, 24 Jun 2020 15:39:40 -0700
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Subject: pciutils: Add decode support for RCECs
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Root Complex Event Collectors provide support for terminating error
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and PME messages from RCiEPs. This patch provides basic decoding for
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the lspci RCEC Endpoint Association Extended Capability. See PCIe 5.0-1,
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sec 7.9.10 for further details.
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Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
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Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
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---
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lib/header.h | 8 +-
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ls-ecaps.c | 59 +++++++++++-
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setpci.c | 2 +-
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tests/cap-rcec | 299 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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4 files changed, 364 insertions(+), 4 deletions(-)
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create mode 100644 tests/cap-rcec
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diff --git a/lib/header.h b/lib/header.h
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index 472816e..57a9343 100644
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--- a/lib/header.h
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+++ b/lib/header.h
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@@ -219,7 +219,7 @@
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#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */
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#define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
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#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
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-#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
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+#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
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#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
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#define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */
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#define PCI_EXT_CAP_ID_RCRB 0x0a /* Root Complex Register Block */
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@@ -1048,6 +1048,12 @@
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#define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64-bit) */
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#define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */
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+/* Root Complex Event Collector Endpoint Association */
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+#define PCI_RCEC_EP_CAP_VER(reg) (((reg) >> 16) & 0xf)
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+#define PCI_RCEC_BUSN_REG_VER 0x02 /* as per PCIe sec 7.9.10.1 */
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+#define PCI_RCEC_RCIEP_BMAP 0x0004 /* as per PCIe sec 7.9.10.2 */
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+#define PCI_RCEC_BUSN_REG 0x0008 /* as per PCIe sec 7.9.10.3 */
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+
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/* PCIe Vendor-Specific Capability */
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#define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */
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#define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */
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diff --git a/ls-ecaps.c b/ls-ecaps.c
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index e71209e..99c55ff 100644
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--- a/ls-ecaps.c
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+++ b/ls-ecaps.c
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@@ -634,6 +634,61 @@ cap_rclink(struct device *d, int where)
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}
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}
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+static void
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+cap_rcec(struct device *d, int where)
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+{
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+ printf("Root Complex Event Collector Endpoint Association\n");
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+ if (verbose < 2)
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+ return;
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+
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+ if (!config_fetch(d, where, 12))
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+ return;
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+
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+ u32 hdr = get_conf_long(d, where);
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+ byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr);
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+ u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP);
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+ printf("\t\tRCiEPBitmap: ");
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+ if (bmap)
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+ {
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+ int prevmatched=0;
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+ int adjcount=0;
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+ int prevdev=0;
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+ printf("RCiEP at Device(s):");
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+ for (int dev=0; dev < 32; dev++)
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+ {
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+ if (BITS(bmap, dev, 1))
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+ {
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+ if (!adjcount)
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+ printf("%s %u", (prevmatched) ? "," : "", dev);
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+ adjcount++;
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+ prevdev=dev;
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+ prevmatched=1;
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+ }
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+ else
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+ {
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+ if (adjcount > 1)
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+ printf("-%u", prevdev);
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+ adjcount=0;
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+ }
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+ }
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+ }
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+ else
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+ printf("%s", (verbose > 2) ? "00000000 [none]" : "[none]");
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+ printf("\n");
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+
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+ if (cap_ver < PCI_RCEC_BUSN_REG_VER)
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+ return;
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+
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+ u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG);
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+ u8 lastbusn = BITS(busn, 16, 8);
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+ u8 nextbusn = BITS(busn, 8, 8);
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+
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+ if ((lastbusn == 0x00) && (nextbusn == 0xff))
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+ printf("\t\tAssociatedBusNumbers: %s\n", (verbose > 2) ? "ff-00 [none]" : "[none]");
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+ else
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+ printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn );
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+}
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+
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static void
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cap_dvsec_cxl(struct device *d, int where)
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{
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@@ -991,8 +1046,8 @@ show_ext_caps(struct device *d, int type)
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case PCI_EXT_CAP_ID_RCILINK:
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printf("Root Complex Internal Link <?>\n");
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break;
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- case PCI_EXT_CAP_ID_RCECOLL:
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- printf("Root Complex Event Collector <?>\n");
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+ case PCI_EXT_CAP_ID_RCEC:
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+ cap_rcec(d, where);
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break;
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case PCI_EXT_CAP_ID_MFVC:
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printf("Multi-Function Virtual Channel <?>\n");
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diff --git a/setpci.c b/setpci.c
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index 90ca726..2cb70fa 100644
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--- a/setpci.c
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+++ b/setpci.c
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@@ -350,7 +350,7 @@ static const struct reg_name pci_reg_names[] = {
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{ 0x20004, 0, 0, "ECAP_PB" },
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{ 0x20005, 0, 0, "ECAP_RCLINK" },
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{ 0x20006, 0, 0, "ECAP_RCILINK" },
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- { 0x20007, 0, 0, "ECAP_RCECOLL" },
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+ { 0x20007, 0, 0, "ECAP_RCEC" },
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{ 0x20008, 0, 0, "ECAP_MFVC" },
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{ 0x20009, 0, 0, "ECAP_VC2" },
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{ 0x2000a, 0, 0, "ECAP_RBCB" },
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diff --git a/tests/cap-rcec b/tests/cap-rcec
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new file mode 100644
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index 0000000..836d9a1
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--- /dev/null
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+++ b/tests/cap-rcec
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@@ -0,0 +1,299 @@
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+6a:00.4 Generic system peripheral [0807]: Intel Corporation Device 0b23
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+ Subsystem: Intel Corporation Device 0000
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+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
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+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
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+ Interrupt: pin A routed to IRQ 255
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+ NUMA node: 0
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+ Capabilities: [40] Express (v2) Root Complex Event Collector, MSI 00
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+ DevCap: MaxPayload 512 bytes, PhantFunc 0
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+ ExtTag- RBE-
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+ DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq-
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+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
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+ MaxPayload 128 bytes, MaxReadReq 128 bytes
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+ DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
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+ RootCap: CRSVisible-
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+ RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna- CRSVisible-
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+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
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+ DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR-
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+ 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
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+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
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+ FRS-
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+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- OBFF Disabled,
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+ Capabilities: [80] Power Management version 3
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+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
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+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
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+ Capabilities: [90] MSI: Enable- Count=1/1 Maskable+ 64bit-
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+ Address: 00000000 Data: 0000
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+ Masking: 00000000 Pending: 00000000
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+ Capabilities: [100 v1] Advanced Error Reporting
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+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
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+ UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
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+ UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
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+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
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+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
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+ AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn-
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+ MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
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+ HeaderLog: 00000000 00000000 00000000 00000000
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+ RootCmd: CERptEn- NFERptEn- FERptEn-
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+ RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
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+ FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
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+ ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
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+ Capabilities: [160 v2] Root Complex Event Collector Endpoint Association
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+ RCiEPBitmap: RCiEP at Device(s): 1, 6, 8-10, 12, 15
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+ AssociatedBusNumbers: 02-08
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+00: 86 80 23 0b 00 01 10 00 00 00 07 08 00 00 00 00
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+40: 10 80 a2 00 02 00 00 00 07 00 00 00 00 00 00 00
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
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|
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|
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
--
|
||||
cgit 1.2.3-1.el7
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Name: pciutils
|
||||
Version: 3.6.4
|
||||
Release: 2%{?dist}
|
||||
Version: 3.7.0
|
||||
Release: 1%{?dist}
|
||||
Source: https://mirrors.edge.kernel.org/pub/software/utils/pciutils/%{name}-%{version}.tar.xz
|
||||
Source1: multilibconfigh
|
||||
|
||||
@ -11,6 +11,9 @@ Patch1: pciutils-2.2.1-idpath.patch
|
||||
Patch2: pciutils-dir-d.patch
|
||||
Patch4: pciutils-3.5.6-freefix.patch
|
||||
|
||||
# from upstream, for pciutils <= 3.7.0
|
||||
Patch5: pciutils-3.7.0-decodercec.patch
|
||||
|
||||
License: GPLv2+
|
||||
URL: http://atrey.karlin.mff.cuni.cz/~mj/pciutils.shtml
|
||||
ExclusiveOS: Linux
|
||||
@ -55,6 +58,7 @@ devices connected to the PCI bus.
|
||||
%patch1 -p1 -b .idpath
|
||||
%patch2 -p1 -b .dird
|
||||
%patch4 -p1 -b .freefix
|
||||
%patch5 -p1 -b .decodercec
|
||||
|
||||
%build
|
||||
make SHARED="no" ZLIB="no" LIBKMOD=yes STRIP="" OPT="$RPM_OPT_FLAGS" LDFLAGS="$RPM_LD_FLAGS" PREFIX="/usr" IDSDIR="/usr/share/hwdata" PCI_IDS="pci.ids" %{?_smp_mflags}
|
||||
@ -114,6 +118,10 @@ install -p lib/libpci.pc $RPM_BUILD_ROOT%{_libdir}/pkgconfig
|
||||
%{_includedir}/pci
|
||||
|
||||
%changelog
|
||||
* Fri Oct 30 2020 Michal Hlavinka <mhlavink@redhat.com> - 3.7.0-1
|
||||
- pciutils updated to 3.7.0, add support for basic DVSEC and CXL DVSEC (#1856436)
|
||||
- add support for RCEC Associated Endpoint (#1856440)
|
||||
|
||||
* Wed May 06 2020 Michal Hlavinka <mhlavink@redhat.com> - 3.6.4-2
|
||||
- rebuild package
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user