add support for cxl1.1 device link status information (#RHEL-29162)
Resolves: RHEL-29162
This commit is contained in:
Michal Hlavinka
parent
9be460d239
commit
560491f67e
146
pciutils-3.7.0-cxllinkstatus.patch
Normal file
146
pciutils-3.7.0-cxllinkstatus.patch
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@ -0,0 +1,146 @@
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diff -up pciutils-3.7.0/lib/pci.h.cxxsup pciutils-3.7.0/lib/pci.h
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--- pciutils-3.7.0/lib/pci.h.cxxsup 2024-11-02 17:31:00.588568039 +0100
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+++ pciutils-3.7.0/lib/pci.h 2024-11-02 17:31:21.090755810 +0100
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@@ -142,6 +142,9 @@ struct pci_dev {
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pciaddr_t flags[6]; /* PCI_IORESOURCE_* flags for regions */
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pciaddr_t rom_flags; /* PCI_IORESOURCE_* flags for expansion ROM */
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int domain; /* PCI domain (host bridge) */
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+ u32 rcd_link_cap; /* Link Capabilities register for RCD */
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+ u16 rcd_link_status; /* Link Status register for RCD */
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+ u16 rcd_link_ctrl; /* Link Control register for RCD */
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/* Fields used internally */
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struct pci_access *access;
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@@ -206,6 +209,7 @@ char *pci_get_string_property(struct pci
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#define PCI_FILL_DT_NODE 0x2000 /* Device tree node */
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#define PCI_FILL_IOMMU_GROUP 0x4000
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#define PCI_FILL_RESCAN 0x00010000
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+#define PCI_FILL_RCD_LNK 0x00200000 /* CXL RCD Link status properties */
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void pci_setup_cache(struct pci_dev *, u8 *cache, int len) PCI_ABI;
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diff -up pciutils-3.7.0/lib/sysfs.c.cxxsup pciutils-3.7.0/lib/sysfs.c
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--- pciutils-3.7.0/lib/sysfs.c.cxxsup 2024-11-02 17:31:00.588568039 +0100
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+++ pciutils-3.7.0/lib/sysfs.c 2024-11-02 17:31:15.374703459 +0100
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@@ -376,6 +376,18 @@ sysfs_fill_info(struct pci_dev *d, unsig
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done |= PCI_FILL_DT_NODE;
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}
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+ if (flags & PCI_FILL_RCD_LNK)
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+ {
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+ char buf[OBJBUFSIZE];
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+ if (sysfs_get_string(d, "rcd_link_cap", buf, 0))
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+ d->rcd_link_cap = strtoul(buf, NULL, 16);
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+ if (sysfs_get_string(d, "rcd_link_ctrl", buf, 0))
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+ d->rcd_link_ctrl = strtoul(buf, NULL, 16);
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+ if (sysfs_get_string(d, "rcd_link_status", buf, 0))
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+ d->rcd_link_status = strtoul(buf, NULL, 16);
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+ done |= PCI_FILL_RCD_LNK;
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+ }
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+
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return done | pci_generic_fill_info(d, flags & ~done);
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}
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diff -up pciutils-3.7.0/ls-caps.c.cxxsup pciutils-3.7.0/ls-caps.c
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--- pciutils-3.7.0/ls-caps.c.cxxsup 2024-11-02 17:31:00.587568030 +0100
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+++ pciutils-3.7.0/ls-caps.c 2024-11-02 17:31:00.589568049 +0100
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@@ -8,6 +8,7 @@
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#include <stdio.h>
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#include <string.h>
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+#include <stdlib.h>
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#include "lspci.h"
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@@ -1336,6 +1337,68 @@ static void cap_express_slot2(struct dev
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/* No capabilities that require this field in PCIe rev2.0 spec. */
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}
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+static void cap_express_link_rcd(struct device *d)
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+{
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+ u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
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+ u16 w;
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+ struct pci_dev *pdev = d->dev;
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+
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+ if (!pdev->rcd_link_cap)
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+ return;
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+ t = pdev->rcd_link_cap;
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+ aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
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+ cap_speed = t & PCI_EXP_LNKCAP_SPEED;
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+ cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
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+ printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
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+ t >> 24,
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+ link_speed(cap_speed), cap_width,
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+ aspm_support(aspm));
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+ if (aspm) {
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+ printf(", Exit Latency ");
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+ if (aspm & 1)
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+ printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
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+ if (aspm & 2)
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+ printf("%sL1 %s", (aspm & 1) ? ", " : "",
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+ latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
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+ }
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+ printf("\n");
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+ printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
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+ FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
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+ FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
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+ FLAG(t, PCI_EXP_LNKCAP_DLLA),
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+ FLAG(t, PCI_EXP_LNKCAP_LBNC),
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+ FLAG(t, PCI_EXP_LNKCAP_AOC));
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+
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+ w = pdev->rcd_link_ctrl;
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+ printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
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+ printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
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+ FLAG(w, PCI_EXP_LNKCTL_DISABLE),
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+ FLAG(w, PCI_EXP_LNKCTL_CLOCK),
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+ FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
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+ FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
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+ FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
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+ FLAG(w, PCI_EXP_LNKCTL_BWMIE),
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+ FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
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+
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+ w = pdev->rcd_link_status;
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+ sta_speed = w & PCI_EXP_LNKSTA_SPEED;
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+ sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
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+ printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n",
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+ link_speed(sta_speed),
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+ link_compare(sta_speed, cap_speed),
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+ sta_width,
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+ link_compare(sta_width, cap_width));
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+ printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
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+ FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
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+ FLAG(w, PCI_EXP_LNKSTA_TRAIN),
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+ FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
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+ FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
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+ FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
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+ FLAG(w, PCI_EXP_LNKSTA_AUTBW));
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+
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+ return;
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+}
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+
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static int
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cap_express(struct device *d, int where, int cap)
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{
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@@ -1400,6 +1463,9 @@ cap_express(struct device *d, int where,
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cap_express_dev(d, where, type);
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if (link)
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cap_express_link(d, where, type);
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+ else if (d->dev->rcd_link_cap)
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+ cap_express_link_rcd(d);
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+
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if (slot)
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cap_express_slot(d, where);
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if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
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diff -up pciutils-3.7.0/lspci.c.cxxsup pciutils-3.7.0/lspci.c
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--- pciutils-3.7.0/lspci.c.cxxsup 2024-11-02 17:31:00.589568049 +0100
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+++ pciutils-3.7.0/lspci.c 2024-11-02 17:31:25.268794076 +0100
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@@ -730,7 +730,8 @@ show_verbose(struct device *d)
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show_terse(d);
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pci_fill_info(p, PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES |
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- PCI_FILL_PHYS_SLOT | PCI_FILL_NUMA_NODE | PCI_FILL_DT_NODE | PCI_FILL_IOMMU_GROUP);
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+ PCI_FILL_PHYS_SLOT | PCI_FILL_NUMA_NODE | PCI_FILL_DT_NODE | PCI_FILL_IOMMU_GROUP |
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+ PCI_FILL_RCD_LNK);
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irq = p->irq;
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switch (htype)
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@ -1,6 +1,6 @@
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Name: pciutils
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Version: 3.7.0
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Release: 6%{?dist}
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Release: 7%{?dist}
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Summary: PCI bus related utilities
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License: GPLv2+
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URL: https://mj.ucw.cz/sw/pciutils/
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@ -21,6 +21,9 @@ Patch3: pciutils-3.7.0-decodercec.patch
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Patch4: pciutils-3.7.0-pcie6datarate1of2.patch
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Patch5: pciutils-3.7.0-pcie6datarate2of2.patch
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#cxl1.1 device link status, from upstream, for < 3.13, #RHEL-29162
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Patch6: pciutils-3.7.0-cxllinkstatus.patch
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Requires: hwdata
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Requires: %{name}-libs = %{version}-%{release}
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BuildRequires: gcc make sed kmod-devel
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@ -54,7 +57,13 @@ This package contains a static library for inspecting and setting
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devices connected to the PCI bus.
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%prep
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%autosetup -p1
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%autosetup -p1 -N
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%patch -P 1 -p 1
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%patch -P 2 -p 1
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%patch -P 3 -p 1
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%patch -P 4 -p 1
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%patch -P 5 -p 1
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%patch -P 6 -p 1 -b .cxxsup
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%build
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%make_build SHARED="no" ZLIB="no" LIBKMOD=yes STRIP="" OPT="$RPM_OPT_FLAGS" LDFLAGS="$RPM_LD_FLAGS" PREFIX="/usr" LIBDIR="%{_libdir}" IDSDIR="/usr/share/hwdata" PCI_IDS="pci.ids"
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@ -106,6 +115,9 @@ install -p -m 644 lib/libpci.pc $RPM_BUILD_ROOT%{_libdir}/pkgconfig
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%{_mandir}/man7/*
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%changelog
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* Sat Nov 02 2024 Michal Hlavinka <mhlavink@redhat.com> - 3.7.0-7
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- add support for cxl1.1 device link status information (#RHEL-29162)
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* Thu Oct 31 2024 Michal Hlavinka <mhlavink@redhat.com> - 3.7.0-6
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- add PCIe 6.0 data rate (64 GT/s) support (#RHEL-61959)
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