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pciutils/pciutils-3.7.0-decodercec.patch

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Merged update from upstream sources This is an automated DistroBaker update from upstream sources. If you do not know what this is about or would like to opt out, contact the OSCI team. Source: https://src.fedoraproject.org/rpms/pciutils.git#533570a84050300e03404a8772a1c8b6dde123e5
2020-10-30 11:53:39 +00:00
From e12bd01eea67ca8cf539263124843ba281eb6ecc Mon Sep 17 00:00:00 2001
From: Sean V Kelley <sean.v.kelley@linux.intel.com>
Date: Wed, 24 Jun 2020 15:39:40 -0700
Subject: pciutils: Add decode support for RCECs
Root Complex Event Collectors provide support for terminating error
and PME messages from RCiEPs. This patch provides basic decoding for
the lspci RCEC Endpoint Association Extended Capability. See PCIe 5.0-1,
sec 7.9.10 for further details.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
---
lib/header.h | 8 +-
ls-ecaps.c | 59 +++++++++++-
setpci.c | 2 +-
tests/cap-rcec | 299 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 364 insertions(+), 4 deletions(-)
create mode 100644 tests/cap-rcec
diff --git a/lib/header.h b/lib/header.h
index 472816e..57a9343 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -219,7 +219,7 @@
#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */
#define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
-#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
+#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
#define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */
#define PCI_EXT_CAP_ID_RCRB 0x0a /* Root Complex Register Block */
@@ -1048,6 +1048,12 @@
#define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64-bit) */
#define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */
+/* Root Complex Event Collector Endpoint Association */
+#define PCI_RCEC_EP_CAP_VER(reg) (((reg) >> 16) & 0xf)
+#define PCI_RCEC_BUSN_REG_VER 0x02 /* as per PCIe sec 7.9.10.1 */
+#define PCI_RCEC_RCIEP_BMAP 0x0004 /* as per PCIe sec 7.9.10.2 */
+#define PCI_RCEC_BUSN_REG 0x0008 /* as per PCIe sec 7.9.10.3 */
+
/* PCIe Vendor-Specific Capability */
#define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */
#define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */
diff --git a/ls-ecaps.c b/ls-ecaps.c
index e71209e..99c55ff 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -634,6 +634,61 @@ cap_rclink(struct device *d, int where)
}
}
+static void
+cap_rcec(struct device *d, int where)
+{
+ printf("Root Complex Event Collector Endpoint Association\n");
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where, 12))
+ return;
+
+ u32 hdr = get_conf_long(d, where);
+ byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr);
+ u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP);
+ printf("\t\tRCiEPBitmap: ");
+ if (bmap)
+ {
+ int prevmatched=0;
+ int adjcount=0;
+ int prevdev=0;
+ printf("RCiEP at Device(s):");
+ for (int dev=0; dev < 32; dev++)
+ {
+ if (BITS(bmap, dev, 1))
+ {
+ if (!adjcount)
+ printf("%s %u", (prevmatched) ? "," : "", dev);
+ adjcount++;
+ prevdev=dev;
+ prevmatched=1;
+ }
+ else
+ {
+ if (adjcount > 1)
+ printf("-%u", prevdev);
+ adjcount=0;
+ }
+ }
+ }
+ else
+ printf("%s", (verbose > 2) ? "00000000 [none]" : "[none]");
+ printf("\n");
+
+ if (cap_ver < PCI_RCEC_BUSN_REG_VER)
+ return;
+
+ u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG);
+ u8 lastbusn = BITS(busn, 16, 8);
+ u8 nextbusn = BITS(busn, 8, 8);
+
+ if ((lastbusn == 0x00) && (nextbusn == 0xff))
+ printf("\t\tAssociatedBusNumbers: %s\n", (verbose > 2) ? "ff-00 [none]" : "[none]");
+ else
+ printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn );
+}
+
static void
cap_dvsec_cxl(struct device *d, int where)
{
@@ -991,8 +1046,8 @@ show_ext_caps(struct device *d, int type)
case PCI_EXT_CAP_ID_RCILINK:
printf("Root Complex Internal Link <?>\n");
break;
- case PCI_EXT_CAP_ID_RCECOLL:
- printf("Root Complex Event Collector <?>\n");
+ case PCI_EXT_CAP_ID_RCEC:
+ cap_rcec(d, where);
break;
case PCI_EXT_CAP_ID_MFVC:
printf("Multi-Function Virtual Channel <?>\n");
diff --git a/setpci.c b/setpci.c
index 90ca726..2cb70fa 100644
--- a/setpci.c
+++ b/setpci.c
@@ -350,7 +350,7 @@ static const struct reg_name pci_reg_names[] = {
{ 0x20004, 0, 0, "ECAP_PB" },
{ 0x20005, 0, 0, "ECAP_RCLINK" },
{ 0x20006, 0, 0, "ECAP_RCILINK" },
- { 0x20007, 0, 0, "ECAP_RCECOLL" },
+ { 0x20007, 0, 0, "ECAP_RCEC" },
{ 0x20008, 0, 0, "ECAP_MFVC" },
{ 0x20009, 0, 0, "ECAP_VC2" },
{ 0x2000a, 0, 0, "ECAP_RBCB" },
diff --git a/tests/cap-rcec b/tests/cap-rcec
new file mode 100644
index 0000000..836d9a1
--- /dev/null
+++ b/tests/cap-rcec
@@ -0,0 +1,299 @@
+6a:00.4 Generic system peripheral [0807]: Intel Corporation Device 0b23
+ Subsystem: Intel Corporation Device 0000
+ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Interrupt: pin A routed to IRQ 255
+ NUMA node: 0
+ Capabilities: [40] Express (v2) Root Complex Event Collector, MSI 00
+ DevCap: MaxPayload 512 bytes, PhantFunc 0
+ ExtTag- RBE-
+ DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq-
+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 128 bytes
+ DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
+ RootCap: CRSVisible-
+ RootCtl: ErrCorrectable+ ErrNon-Fatal+ ErrFatal+ PMEIntEna- CRSVisible-
+ RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR-
+ 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- OBFF Disabled,
+ Capabilities: [80] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [90] MSI: Enable- Count=1/1 Maskable+ 64bit-
+ Address: 00000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [100 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP+ SDES- TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+ AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn-
+ MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+ HeaderLog: 00000000 00000000 00000000 00000000
+ RootCmd: CERptEn- NFERptEn- FERptEn-
+ RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
+ FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
+ ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
+ Capabilities: [160 v2] Root Complex Event Collector Endpoint Association
+ RCiEPBitmap: RCiEP at Device(s): 1, 6, 8-10, 12, 15
+ AssociatedBusNumbers: 02-08
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--
cgit 1.2.3-1.el7
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