3967519628
Rebased papi from version 6.0.0 to 7.2.0. Updated the license tag to BSD-3-Clause and modified the Source0 URL to remove the -noiozone suffix. Removed old patches (papi-python3.patch, papi-config.patch, papi-lto.patch, papi-rhbz1923967.patch, papi-arm64fastread.patch, papi-701eventupdate.patch, papi-thread_init.patch, papi-71eventupdate.patch) and added new patches (papi-avail-path-fix.patch, papi-revert-event-depr.patch, papi-revert-arm-test.patch). Updated the configure line to remove --with-shlib option and modified chrpath command to use find for scrubbing rpath/runpath from binaries. Added *.hpp files to the devel package. Resolves: RHEL-121673 This commit was created by Jotnar, a Red Hat Enterprise Linux software maintenance AI agent. Assisted-by: Jotnar
72 lines
3.5 KiB
Diff
72 lines
3.5 KiB
Diff
From 1292085076f57da533cfa5ff1259b2c5103ca614 Mon Sep 17 00:00:00 2001
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From: Aaron Merey <amerey@redhat.com>
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Date: Tue, 15 Jul 2025 20:20:20 -0400
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Subject: [PATCH] Revert "Updating papi_events.csv to support addition of
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L1I_CACHE and deprecation of L1I_CACHE_ACCESS in libpfm4."
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This reverts commit 6b2745ddc924183f968f066b2d48eade8c816b29.
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---
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src/papi_events.csv | 20 ++++++++++----------
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1 file changed, 10 insertions(+), 10 deletions(-)
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index 2706af696..5e095933a 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -2290,8 +2290,8 @@ PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
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PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
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PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
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PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
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-PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
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-PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
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+PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
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+PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL
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PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
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PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS
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PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR
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@@ -2325,8 +2325,8 @@ PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
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PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
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PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
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PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
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-PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
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-PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
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+PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
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+PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL
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PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
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PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS
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PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR
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@@ -2360,8 +2360,8 @@ PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
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PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
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PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
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PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
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-PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
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-PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
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+PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
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+PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL
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PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
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PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS
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PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR
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@@ -2438,15 +2438,15 @@ PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_CACHE,L1D_CACHE_REFILL
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PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
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PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
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PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
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-PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
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-PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
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+PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
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+PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL
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PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
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#NOT_IMPLEMENTED,PAPI_L1_ICR,Level 1 instruction cache reads
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#NOT_IMPLEMENTED,PAPI_L1_ICW,Level 1 instruction cache writes
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#NOT_IMPLEMENTED,PAPI_L1_LDM,Level 1 load misses
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#NOT_IMPLEMENTED,PAPI_L1_STM,Level 1 store misses
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-PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE
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-PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE,L1I_CACHE_REFILL
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+PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE_ACCESS
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+PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE_ACCESS,L1I_CACHE_REFILL
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PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D_CACHE_REFILL,L1I_CACHE_REFILL
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#NOT_IMPLEMENTED,PAPI_L1_TCR,Level 1 total cache reads
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#NOT_IMPLEMENTED,PAPI_L1_TCW,Level 1 total cache writes
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--
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2.50.0
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