From 1292085076f57da533cfa5ff1259b2c5103ca614 Mon Sep 17 00:00:00 2001 From: Aaron Merey Date: Tue, 15 Jul 2025 20:20:20 -0400 Subject: [PATCH] Revert "Updating papi_events.csv to support addition of L1I_CACHE and deprecation of L1I_CACHE_ACCESS in libpfm4." This reverts commit 6b2745ddc924183f968f066b2d48eade8c816b29. --- src/papi_events.csv | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/papi_events.csv b/src/papi_events.csv index 2706af696..5e095933a 100644 --- a/src/papi_events.csv +++ b/src/papi_events.csv @@ -2290,8 +2290,8 @@ PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR -PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE -PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL +PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS +PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR @@ -2325,8 +2325,8 @@ PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR -PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE -PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL +PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS +PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR @@ -2360,8 +2360,8 @@ PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR -PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE -PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL +PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS +PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR @@ -2438,15 +2438,15 @@ PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_CACHE,L1D_CACHE_REFILL PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR -PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE -PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL +PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS +PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL #NOT_IMPLEMENTED,PAPI_L1_ICR,Level 1 instruction cache reads #NOT_IMPLEMENTED,PAPI_L1_ICW,Level 1 instruction cache writes #NOT_IMPLEMENTED,PAPI_L1_LDM,Level 1 load misses #NOT_IMPLEMENTED,PAPI_L1_STM,Level 1 store misses -PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE -PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE,L1I_CACHE_REFILL +PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE_ACCESS +PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE_ACCESS,L1I_CACHE_REFILL PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D_CACHE_REFILL,L1I_CACHE_REFILL #NOT_IMPLEMENTED,PAPI_L1_TCR,Level 1 total cache reads #NOT_IMPLEMENTED,PAPI_L1_TCW,Level 1 total cache writes -- 2.50.0