Tool to transform and deploy CPU microcode update for x86.
- Update Intel CPU microcode to microcode-20250211 release, addresses CVE-2023-34440, CVE-2023-43758, CVE-2024-24582, CVE-2024-28047, CVE-2024-28127, CVE-2024-29214, CVE-2024-31068, CVE-2024-31157, CVE-2024-37020, CVE-2024-39279, CVE-2024-39355, CVE-2024-36293: - Addition of 06-bf-06/0x07 microcode (in intel-ucode/06-97-02) at revision 0x38; - Addition of 06-bf-07/0x07 microcode (in intel-ucode/06-97-02) at revision 0x38; - Addition of 06-bf-06/0x07 microcode (in intel-ucode/06-97-05) at revision 0x38; - Addition of 06-bf-07/0x07 microcode (in intel-ucode/06-97-05) at revision 0x38; - Addition of 06-af-03/0x01 (SRF-SP C0) microcode at revision 0x3000330; - Addition of 06-b7-04/0x32 microcode (in intel-ucode/06-b7-01) at revision 0x12c; - Addition of 06-bf-06/0x07 microcode (in intel-ucode/06-bf-02) at revision 0x38; - Addition of 06-bf-07/0x07 microcode (in intel-ucode/06-bf-02) at revision 0x38; - Addition of 06-bf-06/0x07 microcode (in intel-ucode/06-bf-05) at revision 0x38; - Addition of 06-bf-07/0x07 microcode (in intel-ucode/06-bf-05) at revision 0x38; - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode (in intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0a) from revision 0xf8 up to 0xfa; - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode (in intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0d) from revision 0x100 up to 0x102; - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd0003e7 up to 0xd0003f5; - Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x10002b0 up to 0x10002c0; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-05) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-05) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-05) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-05) from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-05) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-06) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-06) from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-06) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-06/0x10 microcode from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-06) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-06) from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-06) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-07) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-07) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-07) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-07) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-08) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-08) from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-08) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-08) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-08) from revision 0x2b000603 up to 0x2b000620; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision 0x2c000390 up to 0x2c0003e0; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision 0x2b000603 up to 0x2b000620; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision 0x37 up to 0x38; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x37 up to 0x38; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x37 up to 0x38; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x37 up to 0x38; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x37 up to 0x38; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x37 up to 0x38; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x37 up to 0x38; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x37 up to 0x38; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x435 up to 0x436; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x435 up to 0x436; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x435 up to 0x436; - Update of 06-9a-04/0x40 (AZB A0) microcode from revision 0x7 up to 0x9; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x435 up to 0x436; - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x62 up to 0x63; - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x12b up to 0x12c; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision 0x4123 up to 0x4124; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-02) from revision 0x4123 up to 0x4124; - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) from revision 0x4123 up to 0x4124; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-03) from revision 0x4123 up to 0x4124; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4123 up to 0x4124; - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) from revision 0x4123 up to 0x4124; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-08) from revision 0x4123 up to 0x4124; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-08) from revision 0x4123 up to 0x4124; - Update of 06-ba-08/0xe0 microcode from revision 0x4123 up to 0x4124; - Update of 06-be-00/0x19 (ADL-N A0) microcode from revision 0x1a up to 0x1c; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x37 up to 0x38; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x37 up to 0x38; - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x37 up to 0x38; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) from revision 0x37 up to 0x38; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x37 up to 0x38; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x37 up to 0x38; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) from revision 0x37 up to 0x38; - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x37 up to 0x38; - Update of 06-cf-01/0x87 (EMR-SP A0) microcode from revision 0x21000283 up to 0x21000291; - Update of 06-cf-02/0x87 (EMR-SP A1) microcode (in intel-ucode/06-cf-01) from revision 0x21000283 up to 0x21000291; - Update of 06-cf-01/0x87 (EMR-SP A0) microcode (in intel-ucode/06-cf-02) from revision 0x21000283 up to 0x21000291; - Update of 06-cf-02/0x87 (EMR-SP A1) microcode from revision 0x21000283 up to 0x21000291. * .gitignore: Replace /microcode-20241112.tar.gz entry with /microcode-20250211.tar.gz. * 0001-releasenote.md-cleanup-eliminated-usage-of-U-0080.patch: New file. * 0002-releasenote.md-remove-excess-Release-Notes-headers.patch: Likewise. * 0003-releasenote.md-sort-the-entries-of-the-20230808-rele.patch: Likewise. * 0004-releasenote.md-fix-incorrect-platform-mask-for-RPL-H.patch: Likewise. * 0005-releasenote.md-fix-stepping-for-RPL-S.patch: Likewise. * 0006-releasenote.md-add-missing-06-ba-03-e0-to-the-new-mi.patch: Likewise. * 0007-releasenote.md-remove-the-duplicating-06-9e-0c-22-re.patch: Likewise. * 0008-releasenote.md-fix-old-revisions-for-06-8e-09-10-and.patch: Likewise. * 0009-releasenote.md-add-old-revisions-for-06-be-00-11-06-.patch: Likewise. * 0010-releasenote.md-eliminate-trailing-white-space.patch: Likewise. * 0011-releasenote.md-add-information-about-updates-and-rem.patch: Likewise. * 0012-releasenote.md-add-information-about-06-ba-08-microc.patch: Likewise. * 0013-releasenote.md-fix-whitespace-in-microcode-20240531-.patch: Likewise. * 0014-releasenote.md-use-None-for-the-empty-list-of-new-pl.patch: Likewise. * 0015-releasenote.md-add-missing-old-revision-in-microcode.patch: Likewise. * 0016-releasenote.md-use-new-lines-consistently.patch: Likewise. * 0101-releasenote.md-drop-Removed-Platforms-from-microcode.patch; likewise. * 06-8e-9e-0x-0xca_readme: Add a checksum for revision 0xfa of 06-9e-0a microcode and for revision 0x102 od 06-9e-0d microcode. * 06-8e-9e-0x-dell_readme: Likewise. * codenames.list: Add an entry for CPU signature a06f3/01 (SRF-SP). * microcode_ctl.spec (%intel_ucode_version): Bump to 20250211. (Patch0001, Patch0002, Patch0003, Patch0004, Patch0005, Patch0006, Patch0007, Patch0008, Patch0009, Patch0010, Patch0011, Patch0012, Patch0013, Patch0014, Patch0015, Patch0016, Patch0101): New patches. (%prep): Apply them. (%build): Copy 06-8f-08 to 06-8f-05 and 06-8f-06, copy 06-ba-02 to 06-ba-08, to avoid microcode removal mid-stream. (%changelog): Add a record. * sources: Replace microcode-20241112.tar.gz record with microcode-20250211.tar.gz. Resolves: RHEL-79182 Resolves: RHEL-79186 Resolves: RHEL-79187 Resolves: RHEL-79242 Resolves: RHEL-79243 Resolves: RHEL-79246 Resolves: RHEL-79251 Resolves: RHEL-79252 Signed-off-by: Eugene Syromiatnikov <esyr@redhat.com> |
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.gitignore | ||
01-microcode.conf | ||
06-2d-07_config | ||
06-2d-07_disclaimer | ||
06-2d-07_readme | ||
06-4e-03_config | ||
06-4e-03_disclaimer | ||
06-4e-03_readme | ||
06-4f-01_config | ||
06-4f-01_disclaimer | ||
06-4f-01_readme | ||
06-5e-03_config | ||
06-5e-03_disclaimer | ||
06-5e-03_readme | ||
06-8c-01_config | ||
06-8c-01_disclaimer | ||
06-8c-01_readme | ||
06-8e-9e-0x-0xca_config | ||
06-8e-9e-0x-0xca_disclaimer | ||
06-8e-9e-0x-0xca_readme | ||
06-8e-9e-0x-dell_config | ||
06-8e-9e-0x-dell_disclaimer | ||
06-8e-9e-0x-dell_readme | ||
06-55-04_config | ||
06-55-04_disclaimer | ||
06-55-04_readme | ||
99-microcode-override.conf | ||
0001-releasenote.md-cleanup-eliminated-usage-of-U-0080.patch | ||
0002-releasenote.md-remove-excess-Release-Notes-headers.patch | ||
0003-releasenote.md-sort-the-entries-of-the-20230808-rele.patch | ||
0004-releasenote.md-fix-incorrect-platform-mask-for-RPL-H.patch | ||
0005-releasenote.md-fix-stepping-for-RPL-S.patch | ||
0006-releasenote.md-add-missing-06-ba-03-e0-to-the-new-mi.patch | ||
0007-releasenote.md-remove-the-duplicating-06-9e-0c-22-re.patch | ||
0008-releasenote.md-fix-old-revisions-for-06-8e-09-10-and.patch | ||
0009-releasenote.md-add-old-revisions-for-06-be-00-11-06-.patch | ||
0010-releasenote.md-eliminate-trailing-white-space.patch | ||
0011-releasenote.md-add-information-about-updates-and-rem.patch | ||
0012-releasenote.md-add-information-about-06-ba-08-microc.patch | ||
0013-releasenote.md-fix-whitespace-in-microcode-20240531-.patch | ||
0014-releasenote.md-use-None-for-the-empty-list-of-new-pl.patch | ||
0015-releasenote.md-add-missing-old-revision-in-microcode.patch | ||
0016-releasenote.md-use-new-lines-consistently.patch | ||
0101-releasenote.md-drop-Removed-Platforms-from-microcode.patch | ||
check_caveats | ||
codenames.list | ||
dracut_99microcode_ctl-fw_dir_override_module_init.sh | ||
gating.yaml | ||
gen_provides.sh | ||
gen_updates2.py | ||
intel_config | ||
intel_disclaimer | ||
intel_readme | ||
microcode_ctl.spec | ||
microcode.service | ||
README | ||
README.caveats | ||
reload_microcode | ||
sources | ||
update_ucode |
The microcode_ctl package contains microcode files (vendor-provided binary data and/or code in proprietary format that affects behaviour of a device) for Intel CPUs that may be loaded into the CPU during boot. This directory contains information regarding various aspects of the provided microcode files and their usage. * LICENSE.intel-ucode "license" file from the Intel x86 CPU microcode archive. * README This file. * README.caveats Caveats (mechanism for enabling/disabling usage of sets of microcode files based on caveat configuration and user preferences) documentation. Also contains general information about microcode update behaviour and links with additional information about the relevant microarchitectural vulnerabilities. * README.intel-ucode "README.md" file from the Intel x86 CPU microcode archive. * RELEASE_NOTES.intel-ucode "releasenote.md" file from the Intel x86 CPU microcode archive. * SECURITY.intel-ucode "security.md" file from the Intel x86 CPU microcode archive. * SUMMARY.intel-ucode Information about supplied microcode files extracted from their headers, in a table form. Columns have the following meaning: * "Path": path to the microcode file under one of the following directories: * /usr/share/microcode_ctl/ucode_with_caveats/intel * /usr/share/microcode_ctl/ucode_with_caveats * /usr/share/microcode_ctl * /lib/firmware * /etc/firmware * "Offset": offset of the microcode blob within the micocode file in bytes. * "Ext. Offset": offset of the extended signature header within the microcode file in bytes. * "Data Size": size of microcode data in bytes. 0 means 2000 bytes. * "Total Size": size of microcode blob in bytes, incuding headers. 0 means 2048 bytes. * "CPUID": CPU ID signature (in format returned by the CPUID instruction). * "Platform ID Mask": mask of suitable Platform IDs (provided in bits 52..50 of MSR 0x17). * "Revision": microcode revision. * "Date": microcode creation date. * "Checksum": sum (in base 1<< 32) of all 32-bit values comprising the microcode (from Offset up to Offset + Total Size). * "Codenames": list of known CPU codenames associated with the CPUID and Platform ID Mask combination. Please refer to README.cavets, section "Microcode file structure" for additional information regarding microcode header fields. * caveats Directory that contains readme files for each specific caveat.