.gitignore

@@ -1,7 +1,7 @@
-SOURCES/06-2d-07
+/microcode-20190918.tar.gz
-SOURCES/06-4e-03
+/microcode-20191115.tar.gz
-SOURCES/06-55-04
+/microcode-20230808.tar.gz
-SOURCES/06-5e-03
+/06-2d-07
-SOURCES/microcode-20190918.tar.gz
+/06-4e-03
-SOURCES/microcode-20191115.tar.gz
+/06-55-04
-SOURCES/microcode-20231009.tar.gz
+/06-5e-03

.microcode_ctl.metadata

@@ -1,7 +0,0 @@
-bcf2173cd3dd499c37defbc2533703cfa6ec2430 SOURCES/06-2d-07
-06432a25053c823b0e2a6b8e84e2e2023ee3d43e SOURCES/06-4e-03
-2e405644a145de0f55517b6a9de118eec8ec1e5a SOURCES/06-55-04
-86c60ee7d5d0d7115a4962c1c61ceecb0fd3a95a SOURCES/06-5e-03
-bc20d6789e6614b9d9f88ee321ab82bed220f26f SOURCES/microcode-20190918.tar.gz
-774636f4d440623b0ee6a2dad65260e81208074d SOURCES/microcode-20191115.tar.gz
-bdbc8d6488cf197476253cb9bc50532cc76d91a1 SOURCES/microcode-20231009.tar.gz

06-8c-01_readme

@@ -16,7 +16,6 @@ microcode revisions in question are listed below:
  * 06-8c-01, revision 0xa6: fdcf89e3a15a20df8aeee215b78bf5d13d731044
  * 06-8c-01, revision 0xaa: cf84883f6b3184690c25ccade0b10fa839ac8657
  * 06-8c-01, revision 0xac: b9f342e564a0be372ed1f4709263bf811feb022a
- * 06-8c-01, revision 0xb4: 6596bb8696cde85538bb833d090f0b7a42d6ae14
 
 Please contact your system vendor for a BIOS/firmware update that contains
 the latest microcode version.  For the information regarding microcode versions

SOURCES/0011-releasenote.md-add-stub-release-notes-for-microcode-.patch

@@ -1,62 +0,0 @@
-From f8d6bf8bd8f9ca011c9e0703ece03b2a128b263a Mon Sep 17 00:00:00 2001
-From: Eugene Syromiatnikov <esyr@redhat.com>
-Date: Mon, 6 Nov 2023 12:59:23 +0100
-Subject: [PATCH] releasenote.md: add stub release notes for microcode-20231009
-
-Signed-off-by: Eugene Syromiatnikov <esyr@redhat.com>
----
- releasenote.md | 40 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 40 insertions(+)
-
-diff --git a/releasenote.md b/releasenote.md
-index 429105c..050cfb4 100644
---- a/releasenote.md
-+++ b/releasenote.md
-@@ -1,4 +1,44 @@
- # Release Notes
-+## microcode-20231009
-+
-+### Purpose
-+
-+- Security updates for [INTEL-SA-00950](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00950.html)
-+
-+- Update for functional issues.
-+
-+### New Platforms
-+
-+### Updated Platforms
-+
-+| Processor      | Stepping | F-M-S/PI    | Old Ver  | New Ver  | Products
-+|:---------------|:---------|:------------|:---------|:---------|:---------
-+| ADL            | C0       | 06-97-02/07 | 0000002e | 00000032 | Core Gen12
-+| ADL            | C0       | 06-97-05/07 | 0000002e | 00000032 | Core Gen12
-+| ADL            | C0       | 06-bf-02/07 | 0000002e | 00000032 | Core Gen12
-+| ADL            | C0       | 06-bf-05/07 | 0000002e | 00000032 | Core Gen12
-+| ADL            | L0       | 06-9a-03/80 | 0000042c | 00000430 | Core Gen12
-+| ADL            | L0       | 06-9a-04/80 | 0000042c | 00000430 | Core Gen12
-+| ADL-N          | A0       | 06-be-00/11 | 00000011 | 00000012 | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E
-+| AZB            | A0       | 06-9a-04/40 | 00000004 | 00000005 | Intel(R) Atom(R) C1100
-+| ICL-D          | B0       | 06-6c-01/10 | 01000230 | 01000268 | Xeon D-17xx, D-27xx
-+| ICL-U/Y        | D1       | 06-7e-05/80 | 000000bc | 000000c2 | Core Gen10 Mobile
-+| ICX-SP         | Dx/M1    | 06-6a-06/87 | 0d0003a5 | 0d0003b9 | Xeon Scalable Gen3
-+| RKL-S          | B0       | 06-a7-01/02 | 00000059 | 0000005d | Core Gen11
-+| RPL-H/P/PX 6+8 | J0       | 06-ba-02/e0 | 00004119 | 0000411c | Core Gen13
-+| RPL-S          | B0       | 06-b7-01/32 | 00000119 | 0000011d | Core Gen13
-+| RPL-U 2+8      | Q0       | 06-ba-03/e0 | 00004119 | 0000411c | Core Gen13
-+| SPR-HBM        | B1       | 06-8f-05/10 | 2c000271 | 2c000290 | Xeon Max
-+| SPR-HBM        | B3       | 06-8f-08/10 | 2c000271 | 2c000290 | Xeon Max
-+| SPR-SP         | E2       | 06-8f-05/87 | 2b0004b1 | 2b0004d0 | Xeon Scalable Gen4
-+| SPR-SP         | E3       | 06-8f-06/87 | 2b0004b1 | 2b0004d0 | Xeon Scalable Gen4
-+| SPR-SP         | E4/S2    | 06-8f-07/87 | 2b0004b1 | 2b0004d0 | Xeon Scalable Gen4
-+| SPR-SP         | E5/S3    | 06-8f-08/87 | 2b0004b1 | 2b0004d0 | Xeon Scalable Gen4
-+| TGL            | B0/B1    | 06-8c-01/80 | 000000ac | 000000b4 | Core Gen11 Mobile
-+| TGL-H          | R0       | 06-8d-01/c2 | 00000046 | 0000004e | Core Gen11 Mobile
-+| TGL-R          | C0       | 06-8c-02/c2 | 0000002c | 00000034 | Core Gen11 Mobile
-+
-+
- ## [microcode-20230808](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20230808)
- 
- ### Purpose
--- 
-2.13.6
-

gating.yaml

@@ -0,0 +1,6 @@
+--- !Policy
+product_versions:
+  - rhel-8
+decision_context: osci_compose_gate
+rules:
+  - !PassingTestCaseRule {test_case_name: kernel-qe.kernel-ci.hardware-microcode_ctl.tier0.functional}

microcode_ctl.spec

@@ -1,4 +1,4 @@
-%define intel_ucode_version 20231009
+%define intel_ucode_version 20230808
 %global debug_package %{nil}
 
 %define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats
@@ -12,13 +12,12 @@
 
 Summary:        CPU microcode updates for Intel x86 processors
 Name:           microcode_ctl
-Version:        20230808
+Version:        %{intel_ucode_version}
-Release:        2.%{intel_ucode_version}.1%{?dist}
+Release:        2%{?dist}
 Epoch:          4
 License:        CC0 and Redistributable, no modification permitted
 URL:            https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files
-#Source0:        https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/microcode-%{intel_ucode_version}.tar.gz
+Source0:        https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/microcode-%{intel_ucode_version}.tar.gz
-Source0:        microcode-%{intel_ucode_version}.tar.gz
 
 # (Pre-MDS) revision 0x714 of 06-2d-07 microcode
 Source2:        https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/raw/microcode-20190514/intel-ucode/06-2d-07
@@ -133,7 +132,6 @@ Patch0007: 0007-releasenote.md-add-missing-06-ba-03-e0-to-the-new-mi.patch
 Patch0008: 0008-releasenote.md-remove-the-duplicating-06-9e-0c-22-re.patch
 Patch0009: 0009-releasenote.md-fix-old-revisions-for-06-8e-09-10-and.patch
 Patch0010: 0010-releasenote.md-add-old-revisions-for-06-be-00-11-06-.patch
-Patch0011: 0011-releasenote.md-add-stub-release-notes-for-microcode-.patch
 
 ExclusiveArch:  %{ix86} x86_64
 BuildRequires:  systemd-units
@@ -171,7 +169,6 @@ is no longer used for microcode upload and, as a result, no longer provided.
 %patch0008 -p1
 %patch0009 -p1
 %patch0010 -p1
-%patch0011 -p1
 
 %build
 # remove bogus *_DUPLICATE files with older microcode revisions
@@ -572,160 +569,6 @@ rm -rf %{buildroot}
 
 
 %changelog
-* Wed Nov 01 2023 Eugene Syromiatnikov <esyr@redhat.com> - 4:20230808-2.20231009.1
-- Update Intel CPU microcode to microcode-20231009 release, addresses
-  CVE-2023-23583 (RHEL-3684):
-  - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode (in
-    intel-06-8c-01/intel-ucode/06-8c-01) from revision 0xac up to 0xb4;
-  - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd0003a5
-    up to 0xd0003b9;
-  - Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x1000230
-    up to 0x1000268;
-  - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xbc
-    up to 0xc2;
-  - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x2c up
-    to 0x34;
-  - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x46 up
-    to 0x4e;
-  - Update of 06-8f-04/0x10 microcode from revision 0x2c000271 up to
-    0x2c000290;
-  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode from revision
-    0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
-    intel-ucode/06-8f-04) from revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
-    intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) from
-    revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
-    intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
-    intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
-    intel-ucode/06-8f-04) from revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
-    intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from
-    revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
-    intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision
-    0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b0004b1
-    up to 0x2b0004d0;
-  - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from
-    revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
-    intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
-    intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
-    intel-ucode/06-8f-05) from revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
-    intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from
-    revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
-    intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
-    intel-ucode/06-8f-06) from revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
-    intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-06/0x10 microcode from revision 0x2c000271 up to
-    0x2c000290;
-  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b0004b1
-    up to 0x2b0004d0;
-  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
-    intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
-    intel-ucode/06-8f-06) from revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
-    intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
-    intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
-    intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
-    intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision
-    0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
-    intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from
-    revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
-    intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
-    intel-ucode/06-8f-08) from revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
-    intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from
-    revision 0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
-    intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
-    intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision
-    0x2c000271 up to 0x2c000290;
-  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision
-    0x2b0004b1 up to 0x2b0004d0;
-  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision
-    0x2e up to 0x32;
-  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
-    intel-ucode/06-97-02) from revision 0x2e up to 0x32;
-  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
-    from revision 0x2e up to 0x32;
-  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
-    from revision 0x2e up to 0x32;
-  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
-    intel-ucode/06-97-05) from revision 0x2e up to 0x32;
-  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x2e
-    up to 0x32;
-  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
-    from revision 0x2e up to 0x32;
-  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
-    from revision 0x2e up to 0x32;
-  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision
-    0x42c up to 0x430;
-  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
-    intel-ucode/06-9a-03) from revision 0x42c up to 0x430;
-  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
-    intel-ucode/06-9a-04) from revision 0x42c up to 0x430;
-  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x42c
-    up to 0x430;
-  - Update of 06-9a-04/0x40 (AZB A0) microcode from revision 0x4 up
-    to 0x5;
-  - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x59 up
-    to 0x5d;
-  - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x119 up
-    to 0x11d;
-  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision
-    0x4119 up to 0x411c;
-  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
-    intel-ucode/06-ba-02) from revision 0x4119 up to 0x411c;
-  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
-    intel-ucode/06-ba-03) from revision 0x4119 up to 0x411c;
-  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4119
-    up to 0x411c;
-  - Update of 06-be-00/0x11 (ADL-N A0) microcode from revision 0x11 up
-    to 0x12;
-  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
-    intel-ucode/06-bf-02) from revision 0x2e up to 0x32;
-  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
-    intel-ucode/06-bf-02) from revision 0x2e up to 0x32;
-  - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x2e up
-    to 0x32;
-  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02)
-    from revision 0x2e up to 0x32;
-  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
-    intel-ucode/06-bf-05) from revision 0x2e up to 0x32;
-  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
-    intel-ucode/06-bf-05) from revision 0x2e up to 0x32;
-  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05)
-    from revision 0x2e up to 0x32;
-  - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x2e up
-    to 0x32.
-
 * Tue Aug 22 2023 Eugene Syromiatnikov <esyr@redhat.com> - 4:20230808-2
 - Add support for the new, more correct, variant of dracut's default
   $fw_dir path in dracut_99microcode_ctl-fw_dir_override_module_init.sh.

sources

@@ -0,0 +1,7 @@
+SHA512 (microcode-20190918.tar.gz) = 82e5212238d3e35470d139240d9157877ac252725598ec31bfe1763755681539a4ecdf24e04c4e4270215578a9ca3c063c8fc353accf99999c3d4ac2780a6e0c
+SHA512 (microcode-20191115.tar.gz) = 11014c16bde83ac290bc75e458242f5e64b8dffd49de2e938f61f4a09979cd5e80dd1a85d2ccbac067e4398dc3d93ef3583e4aa9b2e545ba46d26e65ec1e2881
+SHA512 (microcode-20230808.tar.gz) = 8316eb9d35b315e630c6c9fab1ba601b91e72cc42926ef14e7c2b77e7025d276ae06c143060f44cd1a873d3879c067d11ad82e1886c796e6be6bf466243ad85b
+SHA512 (06-2d-07) = 631ec8ad8ad3c9b32d9569689f673010d26c13c7cc377d66b8fc5150de52485076d1514ba867dfa4f468889a31d6701cd8a0789d465ad069d98c8ea0f5bd3204
+SHA512 (06-4e-03) = 248066b521bf512b5d8e4a8c7e921464ce52169c954d6e4ca580d8c172cd789519e22b4cf56c212e452b4191741f0202019f7061d322c9433b5af9ce5413b567
+SHA512 (06-55-04) = db2783cd62680510a7105e7c3fd9d5fffac6a33159ba811f4669f8afb9a5badde4c009bf1868e6a53eb3ac2286812404127bcd45fcbc65fe004788e25ae3e222
+SHA512 (06-5e-03) = 7841c1f27b10016943d448f49fc27e88c671cf68015a8d3fb13ef9f45fbe350cef4865389623c57ed655aac1898071b611a7757d9f166bc8e3f706df5247682c