.gitignore

@@ -1,9 +1,7 @@
-SOURCES/06-2d-07
-SOURCES/06-4e-03
-SOURCES/06-55-04
-SOURCES/06-55-06
-SOURCES/06-5e-03
-SOURCES/06-8f-08
-SOURCES/microcode-20190918.tar.gz
-SOURCES/microcode-20191115.tar.gz
-SOURCES/microcode-20250812.tar.gz
+/microcode-*.tar.gz
+/06-2d-07
+/06-4e-03
+/06-55-04
+/06-55-06
+/06-5e-03
+/06-8f-08

.microcode_ctl.metadata

@@ -1,9 +0,0 @@
-bcf2173cd3dd499c37defbc2533703cfa6ec2430 SOURCES/06-2d-07
-06432a25053c823b0e2a6b8e84e2e2023ee3d43e SOURCES/06-4e-03
-2e405644a145de0f55517b6a9de118eec8ec1e5a SOURCES/06-55-04
-01a4238bf65e14179cfc1bc592cce0666306e217 SOURCES/06-55-06
-86c60ee7d5d0d7115a4962c1c61ceecb0fd3a95a SOURCES/06-5e-03
-adf8b6aa2718ff16f3d19d34ec389270073d2b5e SOURCES/06-8f-08
-bc20d6789e6614b9d9f88ee321ab82bed220f26f SOURCES/microcode-20190918.tar.gz
-774636f4d440623b0ee6a2dad65260e81208074d SOURCES/microcode-20191115.tar.gz
-8ea689fb524531a4fa84a1830090d8c4bdb6162b SOURCES/microcode-20250812.tar.gz

0016-releasenote.md-use-new-lines-consistently.patch

@@ -19,14 +19,6 @@ diff --git a/releasenote.md b/releasenote.md
 index 0cdfa20..3c700b5 100644
 --- a/releasenote.md
 +++ b/releasenote.md
-@@ -156,6 +156,7 @@
- |:---------------|:---------|:------------|:---------|:---------|:---------
- | CFL-H/S        | P0       | 06-9e-0c/22 | 000000f6 | 000000f8 | Core Gen9
- 
-+
- ## [microcode-20241112](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20241112)
- 
- ### Purpose
 @@ -164,6 +165,7 @@
  - Security updates for [INTEL-SA-01079](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01079.html)
  - Updated security updates for [INTEL-SA-01097](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01097.html)

0017-releasenote.md-add-information-about-removal-of-CLX-.patch

@@ -31,7 +31,7 @@ index 3c700b5..d42e9ad 100644
 +| CLX-SP         | B0       | 06-55-06/bf | 04003605 |          | Xeon Scalable Gen2
 +| EMR-SP         | A0       | 06-cf-01/87 | 21000291 |          | Xeon Scalable Gen5
 +
- 
+ # Release Notes
  ## [microcode-20250211](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20250211)
  
 -- 

0101-releasenote.md-drop-Removed-Platforms-from-microcode.patch

@@ -17,7 +17,7 @@ diff --git a/releasenote.md b/releasenote.md
 index d42e9ad..e46f6f0 100644
 --- a/releasenote.md
 +++ b/releasenote.md
-@@ -85,13 +85,6 @@
+@@ -188,13 +188,6 @@
  | TWL            | N0       | 06-be-00/19 | 0000001c | 0000001d | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E
  | WHL-U          | V0       | 06-8e-0c/94 | 000000fc | 00000100 | Core Gen8 Mobile
  
@@ -28,10 +28,10 @@ index d42e9ad..e46f6f0 100644
 -| CLX-SP         | B0       | 06-55-06/bf | 04003605 |          | Xeon Scalable Gen2
 -| EMR-SP         | A0       | 06-cf-01/87 | 21000291 |          | Xeon Scalable Gen5
 -
- 
+ # Release Notes
  ## [microcode-20250211](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20250211)
  
-@@ -149,14 +142,6 @@
+@@ -252,14 +245,6 @@
  | SPR-SP         | E5/S3    | 06-8f-08/87 | 2b000603 | 2b000620 | Xeon Scalable Gen4
  | TWL            | N0       | 06-be-00/19 | 0000001a | 0000001c | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E
  

06-8f-08_config

@@ -1,5 +1,5 @@
 model GenuineIntel 06-8f-08
-path intel-ucode/06-87-08
+path intel-ucode/06-8f-08
 ## A possible way to disable 0x2b000603 and newer microcode on SPR-EE by default
 ## Based on https://cdrdv2.intel.com/v1/dl/getcontent/772415
 ## and https://cdrdv2.intel.com/v1/dl/getcontent/784461

gating.yaml

@@ -0,0 +1,6 @@
+--- !Policy
+product_versions:
+  - rhel-8
+decision_context: osci_compose_gate
+rules:
+  - !PassingTestCaseRule {test_case_name: kernel-qe.kernel-ci.hardware-microcode_ctl.tier0.functional}

microcode_ctl.spec

@@ -1,4 +1,4 @@
-%define intel_ucode_version 20250812
+%define intel_ucode_version 20251111
 %global debug_package %{nil}
 
 %define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats
@@ -636,6 +636,38 @@ rm -rf %{buildroot}
 
 
 %changelog
+* Mon Nov 24 2025 Denys Vlasenko <dvlasenk@redhat.com> - 4:20251111-1
+- Fix typo in /usr/share/microcode_ctl/ucode_with_caveats/intel-06-8f-08/config
+- Update Intel CPU microcode to microcode-20251111 release (RHEL-128250)
+- New microcode files (in hex):
+  06-ae-01: Granite Rapids-D: revision 1000273
+- Microcode files (/platform_mask shown) with revision updates (in hex):
+  06-8f-07/87: Sapphire Rapids: 2b000643 to 2b000650
+  06-8f-08/10: Sapphire Rapids with HBM: 2c000401 to 2c000410
+  06-8f-08/87: Sapphire Rapids: 2b000643 to 2b000650
+  06-97-02/07: Alder Lake: 003a to 003d
+  06-97-05/07: Alder Lake: 003a to 003d
+  06-9a-03/80: Alder Lake-L: 0437 to 043a
+  06-9a-04/80: Alder Lake-L: 0437 to 043a
+  06-9a-04/40: Arizona Beach (Atom C11xx): 000a to 000b
+  06-ad-01/95: Granite Rapids-X: 10003d0 to 10003f0
+  06-ad-01/20: Granite Rapids-X: a000100 to a000124
+  06-af-03/01: Crestmont (Sierra Forest): 3000362 to 3000382
+  06-b7-01/32: Raptor Lake: 012f to 0132
+  06-ba-02/e0: Raptor Lake-P: 4129 to 6133
+  06-ba-03/e0: Raptor Lake-P: 4129 to 6133
+  06-bd-01/80: Lunar Lake: 0123 to 0125
+  06-be-00/19: Gracemont (Alder Lake-N): 001d to 001e
+  06-bf-02/07: Raptor Lake-S: 003a to 003d
+  06-bf-05/07: Raptor Lake-S: 003a to 003d
+  06-c5-02/82: Arrow Lake-H: 0119 to 011a
+  06-c6-02/82: Arrow Lake: 0119 to 011a
+  06-cf-02/87: Emerald Rapids: 210002b3 to 210002c0
+- Fixes errata RPL070/ADL083/LNL047/ARL054/SPR154/EMR147:
+  "REP SCASB, REP CMPSB may return incorrect results when racing
+  memory access with another core or thread" on Raptor Lake,
+  Alder Lake, Lunar Lake, Arrow Lake, Sapphire Rapids, Emerald Rapids.
+
 * Wed Aug 20 2025 Denys Vlasenko <dvlasenk@redhat.com> - 4:20250812-1
 - Update Intel CPU microcode to microcode-20250812 release
   - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000404

sources

@@ -0,0 +1,9 @@
+SHA512 (microcode-20190918.tar.gz) = 82e5212238d3e35470d139240d9157877ac252725598ec31bfe1763755681539a4ecdf24e04c4e4270215578a9ca3c063c8fc353accf99999c3d4ac2780a6e0c
+SHA512 (microcode-20191115.tar.gz) = 11014c16bde83ac290bc75e458242f5e64b8dffd49de2e938f61f4a09979cd5e80dd1a85d2ccbac067e4398dc3d93ef3583e4aa9b2e545ba46d26e65ec1e2881
+SHA512 (microcode-20251111.tar.gz) = a11ded3158d761ae68258ca61a15014258d68ea28e9e9c94c125a49490a1df0f4b5c6cc37e97b42d84594760e455a1444feb2106e920ea6dd09934e545d92188
+SHA512 (06-2d-07) = 631ec8ad8ad3c9b32d9569689f673010d26c13c7cc377d66b8fc5150de52485076d1514ba867dfa4f468889a31d6701cd8a0789d465ad069d98c8ea0f5bd3204
+SHA512 (06-4e-03) = 248066b521bf512b5d8e4a8c7e921464ce52169c954d6e4ca580d8c172cd789519e22b4cf56c212e452b4191741f0202019f7061d322c9433b5af9ce5413b567
+SHA512 (06-55-04) = db2783cd62680510a7105e7c3fd9d5fffac6a33159ba811f4669f8afb9a5badde4c009bf1868e6a53eb3ac2286812404127bcd45fcbc65fe004788e25ae3e222
+SHA512 (06-55-06) = 0045a5a0cf88a91b1a0b544d5674cdf7be44467b4a160b28304b5a221d3de4fab3f99ad5ec2ebc15ad73a9ca938baba7d8c72164132ea189a7a4ed9b83306223
+SHA512 (06-5e-03) = 7841c1f27b10016943d448f49fc27e88c671cf68015a8d3fb13ef9f45fbe350cef4865389623c57ed655aac1898071b611a7757d9f166bc8e3f706df5247682c
+SHA512 (06-8f-08) = 972bde0bf664679891e4bb3740fd3e55fb5b36f288df29e2f5936e6e472a9f14f0c5be58e9f604d5e3f08c06d43bce7d749f66c07698f9cb885b7f016377bda7