update of vc4 patch set to fix ftb
This commit is contained in:
Peter Robinson
parent
11737d58ed
commit
eebf5854bf
@ -1,4 +1,4 @@
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From f050751c9ca1ceb5089fc2337b2dd2eeda1557b7 Mon Sep 17 00:00:00 2001
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From de31fe81a869c80b3cc08cb648640cf617e0d09c Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 15 Jun 2017 16:52:22 -0700
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Subject: [PATCH] vc4: Switch back to using a local copy of vc4_drm.h.
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@ -8,17 +8,19 @@ Follow intel's lead and drop our requirement for it.
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Generated from 056f4f02abb7e9e4a0cf0cda0211586df5e43842 of drm-misc-next
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(cherry picked from commit 8ffd5a0458bf6852afd0ac1e03b881e39e63f629)
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(cherry picked from commit 1facea3486e3dd4e4a6cf561a725b9c4312ca58a)
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---
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configure.ac | 2 -
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src/gallium/drivers/vc4/Makefile.am | 3 +-
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src/gallium/drivers/vc4/Makefile.sources | 1 +
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src/gallium/drivers/vc4/vc4_drm.h | 318 +++++++++++++++++++++++++++++++
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4 files changed, 320 insertions(+), 4 deletions(-)
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src/gallium/drivers/vc4/drm_fourcc.h | 379 +++++++++++++++++++++++++++++++
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src/gallium/drivers/vc4/vc4_drm.h | 318 ++++++++++++++++++++++++++
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5 files changed, 699 insertions(+), 4 deletions(-)
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create mode 100644 src/gallium/drivers/vc4/drm_fourcc.h
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create mode 100644 src/gallium/drivers/vc4/vc4_drm.h
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diff --git a/configure.ac b/configure.ac
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index 60ce75a58b..6fcda01e36 100644
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index b069f54155..81258715b5 100644
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--- a/configure.ac
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+++ b/configure.ac
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@@ -79,7 +79,6 @@ LIBDRM_INTEL_REQUIRED=2.4.75
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@ -70,6 +72,391 @@ index 10de343612..cb04cc9c0a 100644
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vc4_emit.c \
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vc4_fence.c \
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vc4_formats.c \
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diff --git a/src/gallium/drivers/vc4/drm_fourcc.h b/src/gallium/drivers/vc4/drm_fourcc.h
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new file mode 100644
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index 0000000000..7586c46f68
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--- /dev/null
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+++ b/src/gallium/drivers/vc4/drm_fourcc.h
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@@ -0,0 +1,379 @@
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+/*
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+ * Copyright 2011 Intel Corporation
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice (including the next
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+ * paragraph) shall be included in all copies or substantial portions of the
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+ * Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+#ifndef DRM_FOURCC_H
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+#define DRM_FOURCC_H
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+
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+#include "drm.h"
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+
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+#if defined(__cplusplus)
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+extern "C" {
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+#endif
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+
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+#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
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+ ((__u32)(c) << 16) | ((__u32)(d) << 24))
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+
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+#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
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+
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+/* color index */
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+#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
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+
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+/* 8 bpp Red */
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+#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
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+
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+/* 16 bpp Red */
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+#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
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+
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+/* 16 bpp RG */
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+#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
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+#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
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+
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+/* 32 bpp RG */
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+#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
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+#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
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+
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+/* 8 bpp RGB */
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+#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
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+#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
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+
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+/* 16 bpp RGB */
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+#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
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+#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
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+#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
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+#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
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+
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+#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
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+#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
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+#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
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+#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
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+
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+#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
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+#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
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+#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
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+#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
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+
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+#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
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+#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
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+#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
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+#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
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+
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+#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
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+#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
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+
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+/* 24 bpp RGB */
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+#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
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+#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
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+
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+/* 32 bpp RGB */
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+#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
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+#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
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+#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
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+#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
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+
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+#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
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+#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
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+#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
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+#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
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+
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+#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
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+#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
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+#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
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+#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
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+
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+#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
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+#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
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+#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
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+#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
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+
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+/* packed YCbCr */
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+#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
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+#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
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+#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
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+#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
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+
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+#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
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+
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+/*
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+ * 2 plane RGB + A
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+ * index 0 = RGB plane, same format as the corresponding non _A8 format has
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+ * index 1 = A plane, [7:0] A
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+ */
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+#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
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+#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
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+#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
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+#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
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+#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
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+#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
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+#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
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+#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
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+
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+/*
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+ * 2 plane YCbCr
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+ * index 0 = Y plane, [7:0] Y
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+ * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
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+ * or
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+ * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
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+ */
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+#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
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+#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
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+#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
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+#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
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+#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
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+#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
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+
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+/*
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+ * 3 plane YCbCr
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+ * index 0: Y plane, [7:0] Y
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+ * index 1: Cb plane, [7:0] Cb
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+ * index 2: Cr plane, [7:0] Cr
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+ * or
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+ * index 1: Cr plane, [7:0] Cr
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+ * index 2: Cb plane, [7:0] Cb
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+ */
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+#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
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+#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
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+#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
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+#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
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+#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
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+#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
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+#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
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+#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
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+#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
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+#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
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+
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+
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+/*
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+ * Format Modifiers:
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+ *
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+ * Format modifiers describe, typically, a re-ordering or modification
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+ * of the data in a plane of an FB. This can be used to express tiled/
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+ * swizzled formats, or compression, or a combination of the two.
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+ *
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+ * The upper 8 bits of the format modifier are a vendor-id as assigned
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+ * below. The lower 56 bits are assigned as vendor sees fit.
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+ */
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+
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+/* Vendor Ids: */
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+#define DRM_FORMAT_MOD_NONE 0
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+#define DRM_FORMAT_MOD_VENDOR_NONE 0
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+#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
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+#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
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+#define DRM_FORMAT_MOD_VENDOR_NV 0x03
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+#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
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+#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
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+#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
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+#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
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+/* add more to the end as needed */
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+
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+#define fourcc_mod_code(vendor, val) \
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+ ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
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+
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+/*
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+ * Format Modifier tokens:
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+ *
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+ * When adding a new token please document the layout with a code comment,
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+ * similar to the fourcc codes above. drm_fourcc.h is considered the
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+ * authoritative source for all of these.
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+ */
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+
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+/*
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+ * Linear Layout
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+ *
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+ * Just plain linear layout. Note that this is different from no specifying any
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+ * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
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+ * which tells the driver to also take driver-internal information into account
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+ * and so might actually result in a tiled framebuffer.
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+ */
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+#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
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+
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+/* Intel framebuffer modifiers */
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+
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+/*
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+ * Intel X-tiling layout
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+ *
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+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
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+ * in row-major layout. Within the tile bytes are laid out row-major, with
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+ * a platform-dependent stride. On top of that the memory can apply
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+ * platform-depending swizzling of some higher address bits into bit6.
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+ *
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+ * This format is highly platforms specific and not useful for cross-driver
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+ * sharing. It exists since on a given platform it does uniquely identify the
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+ * layout in a simple way for i915-specific userspace.
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+ */
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+#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
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+
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+/*
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+ * Intel Y-tiling layout
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+ *
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+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
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+ * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
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+ * chunks column-major, with a platform-dependent height. On top of that the
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+ * memory can apply platform-depending swizzling of some higher address bits
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+ * into bit6.
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+ *
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+ * This format is highly platforms specific and not useful for cross-driver
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+ * sharing. It exists since on a given platform it does uniquely identify the
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+ * layout in a simple way for i915-specific userspace.
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+ */
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+#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
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+
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+/*
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+ * Intel Yf-tiling layout
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+ *
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+ * This is a tiled layout using 4Kb tiles in row-major layout.
|
||||
+ * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
|
||||
+ * are arranged in four groups (two wide, two high) with column-major layout.
|
||||
+ * Each group therefore consits out of four 256 byte units, which are also laid
|
||||
+ * out as 2x2 column-major.
|
||||
+ * 256 byte units are made out of four 64 byte blocks of pixels, producing
|
||||
+ * either a square block or a 2:1 unit.
|
||||
+ * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
|
||||
+ * in pixel depends on the pixel depth.
|
||||
+ */
|
||||
+#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
|
||||
+
|
||||
+/*
|
||||
+ * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
|
||||
+ *
|
||||
+ * Macroblocks are laid in a Z-shape, and each pixel data is following the
|
||||
+ * standard NV12 style.
|
||||
+ * As for NV12, an image is the result of two frame buffers: one for Y,
|
||||
+ * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
|
||||
+ * Alignment requirements are (for each buffer):
|
||||
+ * - multiple of 128 pixels for the width
|
||||
+ * - multiple of 32 pixels for the height
|
||||
+ *
|
||||
+ * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
|
||||
+ */
|
||||
+#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
|
||||
+
|
||||
+/* Vivante framebuffer modifiers */
|
||||
+
|
||||
+/*
|
||||
+ * Vivante 4x4 tiling layout
|
||||
+ *
|
||||
+ * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
|
||||
+ * layout.
|
||||
+ */
|
||||
+#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
|
||||
+
|
||||
+/*
|
||||
+ * Vivante 64x64 super-tiling layout
|
||||
+ *
|
||||
+ * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
|
||||
+ * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
|
||||
+ * major layout.
|
||||
+ *
|
||||
+ * For more information: see
|
||||
+ * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
|
||||
+ */
|
||||
+#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
|
||||
+
|
||||
+/*
|
||||
+ * Vivante 4x4 tiling layout for dual-pipe
|
||||
+ *
|
||||
+ * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
|
||||
+ * different base address. Offsets from the base addresses are therefore halved
|
||||
+ * compared to the non-split tiled layout.
|
||||
+ */
|
||||
+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
|
||||
+
|
||||
+/*
|
||||
+ * Vivante 64x64 super-tiling layout for dual-pipe
|
||||
+ *
|
||||
+ * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
|
||||
+ * starts at a different base address. Offsets from the base addresses are
|
||||
+ * therefore halved compared to the non-split super-tiled layout.
|
||||
+ */
|
||||
+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
|
||||
+
|
||||
+/* NVIDIA Tegra frame buffer modifiers */
|
||||
+
|
||||
+/*
|
||||
+ * Some modifiers take parameters, for example the number of vertical GOBs in
|
||||
+ * a block. Reserve the lower 32 bits for parameters
|
||||
+ */
|
||||
+#define __fourcc_mod_tegra_mode_shift 32
|
||||
+#define fourcc_mod_tegra_code(val, params) \
|
||||
+ fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
|
||||
+#define fourcc_mod_tegra_mod(m) \
|
||||
+ (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
|
||||
+#define fourcc_mod_tegra_param(m) \
|
||||
+ (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
|
||||
+
|
||||
+/*
|
||||
+ * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
|
||||
+ *
|
||||
+ * Pixels are arranged in simple tiles of 16 x 16 bytes.
|
||||
+ */
|
||||
+#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
|
||||
+
|
||||
+/*
|
||||
+ * Tegra 16Bx2 Block Linear layout, used by TK1/TX1
|
||||
+ *
|
||||
+ * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
|
||||
+ * vertically by a power of 2 (1 to 32 GOBs) to form a block.
|
||||
+ *
|
||||
+ * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
|
||||
+ *
|
||||
+ * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
|
||||
+ * Valid values are:
|
||||
+ *
|
||||
+ * 0 == ONE_GOB
|
||||
+ * 1 == TWO_GOBS
|
||||
+ * 2 == FOUR_GOBS
|
||||
+ * 3 == EIGHT_GOBS
|
||||
+ * 4 == SIXTEEN_GOBS
|
||||
+ * 5 == THIRTYTWO_GOBS
|
||||
+ *
|
||||
+ * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
|
||||
+ * in full detail.
|
||||
+ */
|
||||
+#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
|
||||
+
|
||||
+/*
|
||||
+ * Broadcom VC4 "T" format
|
||||
+ *
|
||||
+ * This is the primary layout that the V3D GPU can texture from (it
|
||||
+ * can't do linear). The T format has:
|
||||
+ *
|
||||
+ * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
|
||||
+ * pixels at 32 bit depth.
|
||||
+ *
|
||||
+ * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
|
||||
+ * 16x16 pixels).
|
||||
+ *
|
||||
+ * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
|
||||
+ * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
|
||||
+ * they're (TR, BR, BL, TL), where bottom left is start of memory.
|
||||
+ *
|
||||
+ * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
|
||||
+ * tiles) or right-to-left (odd rows of 4k tiles).
|
||||
+ */
|
||||
+#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
|
||||
+
|
||||
+#if defined(__cplusplus)
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
+#endif /* DRM_FOURCC_H */
|
||||
diff --git a/src/gallium/drivers/vc4/vc4_drm.h b/src/gallium/drivers/vc4/vc4_drm.h
|
||||
new file mode 100644
|
||||
index 0000000000..0caeaf3a1f
|
||||
@ -394,7 +781,7 @@ index 0000000000..0caeaf3a1f
|
||||
+#endif
|
||||
+
|
||||
+#endif /* _VC4_DRM_H_ */
|
||||
From fbf7afbe460fced78885ee7b1a1ac59ca12c3274 Mon Sep 17 00:00:00 2001
|
||||
From 0670340bc6730e3de453e064b8a883a829900945 Mon Sep 17 00:00:00 2001
|
||||
From: Eric Anholt <eric@anholt.net>
|
||||
Date: Mon, 8 May 2017 16:43:06 -0700
|
||||
Subject: [PATCH] vc4: Drop the u_resource_vtbl no-op layer.
|
||||
@ -621,7 +1008,7 @@ index 2e00104e45..31ec19bcbe 100644
|
||||
/* Flag it as needing update of the contents from the parent. */
|
||||
clone->writes = shadow_parent->writes - 1;
|
||||
|
||||
From 732dfc93d34f655d9ff2da4091219ca3187bb0af Mon Sep 17 00:00:00 2001
|
||||
From 64a91342aeb0c4a795f2184e22b15cf3079fc6ca Mon Sep 17 00:00:00 2001
|
||||
From: Eric Anholt <eric@anholt.net>
|
||||
Date: Mon, 8 May 2017 16:46:59 -0700
|
||||
Subject: [PATCH] vc4: Drop pointless indirections around BO import/export.
|
||||
@ -821,7 +1208,7 @@ index 34d15381ae..0f80ffb346 100644
|
||||
|
||||
const void *
|
||||
vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
|
||||
From 1e842ccb60d9c07c28148d9b7ddf9347aabdaac8 Mon Sep 17 00:00:00 2001
|
||||
From 427bd8275b9d4bb7a52d4e0dd4881a91a96c9c5b Mon Sep 17 00:00:00 2001
|
||||
From: Eric Anholt <eric@anholt.net>
|
||||
Date: Mon, 5 Jun 2017 14:50:26 -0700
|
||||
Subject: [PATCH] vc4: Set shareable BOs as T tiled if possible.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user