Update to 23.3.2 and better fix for gen5 intel.

0001-intel-compiler-don-t-invert-if-s-on-gen5-or-older.patch

@@ -1,32 +0,0 @@
-From db083cf2381638f348e31c9a832e0a8821132e21 Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Thu, 21 Dec 2023 10:39:08 +1000
-Subject: [PATCH] intel/compiler: don't invert if's on gen5 or older
-
-I'm not sure why this works, but since opt_if was changed,
-gtk4-demo hasn't worked on gen4/5.
-
-I tried to track through some opt stages that might be dropping
-predicate_inverse or something, but can't spot anything yet.
-
-Fixes: 31b5f5a51f3a ("nir/opt_if: Simplify if's with general conditions")
----
- src/intel/compiler/brw_fs_nir.cpp | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
-index b9f7366763b..0e57c343b54 100644
---- a/src/intel/compiler/brw_fs_nir.cpp
-+++ b/src/intel/compiler/brw_fs_nir.cpp
-@@ -357,7 +357,7 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
-     * the source, but invert the predicate on the if instruction.
-     */
-    nir_alu_instr *cond = nir_src_as_alu_instr(if_stmt->condition);
--   if (cond != NULL && cond->op == nir_op_inot) {
-+   if (devinfo->ver > 5 && cond != NULL && cond->op == nir_op_inot) {
-       invert = true;
-       cond_reg = get_nir_src(cond->src[0].src);
-       cond_reg = offset(cond_reg, bld, cond->src[0].swizzle[0]);
--- 
-2.43.0
-

0001-intel-compiler-move-gen5-final-pass-to-actually-be-f.patch

@@ -1,52 +0,0 @@
-From e1b03c0d3dfb337c7f462ea7e146e727dbe35040 Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Mon, 18 Dec 2023 16:47:56 +1000
-Subject: [PATCH] intel/compiler: move gen5 final pass to actually be final
- pass
-
-This got broken by the register conversion, this pass needs to be
-after all the others.
-
-Fixes: ce75c3c3fea9 ("intel: Switch to intrinsic-based registers")
----
- src/intel/compiler/brw_nir.c | 17 +++++++++--------
- 1 file changed, 9 insertions(+), 8 deletions(-)
-
-diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
-index 8da98b0fbfd..c36269fd015 100644
---- a/src/intel/compiler/brw_nir.c
-+++ b/src/intel/compiler/brw_nir.c
-@@ -1753,14 +1753,6 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
-    if (OPT(nir_opt_rematerialize_compares))
-       OPT(nir_opt_dce);
- 
--   /* This is the last pass we run before we start emitting stuff.  It
--    * determines when we need to insert boolean resolves on Gen <= 5.  We
--    * run it last because it stashes data in instr->pass_flags and we don't
--    * want that to be squashed by other NIR passes.
--    */
--   if (devinfo->ver <= 5)
--      brw_nir_analyze_boolean_resolves(nir);
--
-    OPT(nir_opt_dce);
- 
-    /* The mesh stages require this pass to be called at the last minute,
-@@ -1773,6 +1765,15 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
-       brw_nir_adjust_payload(nir, compiler);
- 
-    nir_trivialize_registers(nir);
-+
-+   /* This is the last pass we run before we start emitting stuff.  It
-+    * determines when we need to insert boolean resolves on Gen <= 5.  We
-+    * run it last because it stashes data in instr->pass_flags and we don't
-+    * want that to be squashed by other NIR passes.
-+    */
-+   if (devinfo->ver <= 5)
-+      brw_nir_analyze_boolean_resolves(nir);
-+
-    nir_sweep(nir);
- 
-    if (unlikely(debug_enabled)) {
--- 
-2.43.0
-

0001-intel-compiler-reemit-boolean-resolve-for-inverted-i.patch

@@ -0,0 +1,37 @@
+From c59f3601b81bf38cbb7a2b77820f1d827f608339 Mon Sep 17 00:00:00 2001
+From: Dave Airlie <airlied@redhat.com>
+Date: Thu, 21 Dec 2023 10:39:08 +1000
+Subject: [PATCH] intel/compiler: reemit boolean resolve for inverted if on
+ gen5
+
+Gen5 adds some boolean conversion instructions after nir emits,
+but that nir srcs don't line up with them, so reemit the boolean
+conversion if we reemit the inot.
+
+Fixes: 31b5f5a51f3a ("nir/opt_if: Simplify if's with general conditions")
+---
+ src/intel/compiler/brw_fs_nir.cpp | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
+index b9f7366763b..5a4ec96e93f 100644
+--- a/src/intel/compiler/brw_fs_nir.cpp
++++ b/src/intel/compiler/brw_fs_nir.cpp
+@@ -361,6 +361,14 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
+       invert = true;
+       cond_reg = get_nir_src(cond->src[0].src);
+       cond_reg = offset(cond_reg, bld, cond->src[0].swizzle[0]);
++
++      if (devinfo->ver <= 5) {
++         /* redo boolean resolve on gen5 */
++         fs_reg masked = ntb.s.vgrf(glsl_int_type());
++         bld.AND(masked, cond_reg, brw_imm_d(1));
++         masked.negate = true;
++         bld.MOV(retype(cond_reg, BRW_REGISTER_TYPE_D), masked);
++      }
+    } else {
+       invert = false;
+       cond_reg = get_nir_src(if_stmt->condition);
+-- 
+2.43.0
+

mesa.spec

@@ -61,7 +61,7 @@
 
 Name:           mesa
 Summary:        Mesa graphics libraries
-%global ver 23.3.1
+%global ver 23.3.2
 Version:        %{lua:ver = string.gsub(rpm.expand("%{ver}"), "-", "~"); print(ver)}
 Release:        %autorelease
 License:        MIT AND BSD-3-Clause AND SGI-B-2.0
@@ -74,8 +74,7 @@ Source0:        https://archive.mesa3d.org/mesa-%{ver}.tar.xz
 Source1:        Mesa-MLAA-License-Clarification-Email.txt
 
 Patch10:        gnome-shell-glthread-disable.patch
-Patch11:        0001-intel-compiler-move-gen5-final-pass-to-actually-be-f.patch
+Patch11:        0001-intel-compiler-reemit-boolean-resolve-for-inverted-i.patch
-Patch12:        0001-intel-compiler-don-t-invert-if-s-on-gen5-or-older.patch
 
 BuildRequires:  meson >= 1.2.0
 BuildRequires:  gcc

sources

@@ -1 +1 @@
-SHA512 (mesa-23.3.1.tar.xz) = 0861fb5083e37439ad8cc0a0d8372a7c84d8665ea298dc784e2dd893162e20ae072f5ef0b860be88ecf74bc123714acbc1dec312e139b892ff40ef1887c5f4a5
+SHA512 (mesa-23.3.2.tar.xz) = 634d2b67ade2121de3f19f2cccd4bf7ceb2ac391b9366587ed1c2412444e010de8ec14a25529fdec1f43f943096422eb23cefcb8a89d2f8b20286850188b65c3