46 lines
1.5 KiB
Diff
46 lines
1.5 KiB
Diff
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From 83e65320012f327d2e8f1573443b2e20f059e76f Mon Sep 17 00:00:00 2001
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From: Rob Clark <robclark@freedesktop.org>
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Date: Tue, 20 Aug 2013 13:46:30 -0400
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Subject: [PATCH 06/17] freedreno/a3xx/compiler: fix CMP
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The 1st src to add.s needs (r) flag (repeat), otherwise it will end up:
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add.s dst.xyzw, tmp.xxxx -1
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instead of:
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add.s dst.xyzw, tmp.xyzw, -1
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Also, if we are using a temporary dst to avoid clobbering one of the src
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registers, we actually need to use that as the dst for the sel
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instruction.
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Signed-off-by: Rob Clark <robclark@freedesktop.org>
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---
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src/gallium/drivers/freedreno/a3xx/fd3_compiler.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c
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index eabe21c..07bede4 100644
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--- a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c
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+++ b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c
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@@ -790,13 +790,13 @@ trans_cmp(const struct instr_translater *t,
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
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instr->repeat = 3;
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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- add_src_reg(ctx, instr, &tmp_src, 0);
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+ add_src_reg(ctx, instr, &tmp_src, 0)->flags |= IR3_REG_R;
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ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
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/* sel.{f32,f16} dst, src2, tmp, src1 */
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instr = ir3_instr_create(ctx->ir, 3, ctx->so->half_precision ?
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OPC_SEL_F16 : OPC_SEL_F32);
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- vectorize(ctx, instr, &inst->Dst[0].Register, 3,
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+ vectorize(ctx, instr, dst, 3,
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&inst->Src[2].Register, 0,
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&tmp_src, 0,
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&inst->Src[1].Register, 0);
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--
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1.8.4.2
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