147 lines
5.3 KiB
Diff
147 lines
5.3 KiB
Diff
From 5f63c44c510f45953a6b2387799baac49da2ffb5 Mon Sep 17 00:00:00 2001
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From: Matt Roper <matthew.d.roper@intel.com>
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Date: Thu, 12 May 2016 07:06:06 -0700
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Subject: [PATCH 12/17] drm/i915/gen9: Allow watermark calculation on in-flight
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atomic state (v3)
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In an upcoming patch we'll move this calculation to the atomic 'check'
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phase so that the display update can be rejected early if no valid
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watermark programming is possible.
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v2:
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- Drop intel_pstate_for_cstate_plane() helper and add note about how
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the code needs to evolve in the future if we start allowing more than
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one pending commit against a CRTC. (Maarten)
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v3:
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- Only have skl_compute_wm_level calculate watermarks for enabled
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planes; we can just set the other planes on a CRTC to disabled
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without having to look at the plane state. This is important because
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despite our CRTC lock we can still have racing commits that modify
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a disabled plane's property without turning it on. (Maarten)
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Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Link: http://patchwork.freedesktop.org/patch/msgid/1463061971-19638-13-git-send-email-matthew.d.roper@intel.com
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---
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drivers/gpu/drm/i915/intel_pm.c | 61 ++++++++++++++++++++++++++++++++---------
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1 file changed, 48 insertions(+), 13 deletions(-)
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index 518178a..c9f050e 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -3327,23 +3327,56 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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return true;
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}
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-static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
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- struct skl_ddb_allocation *ddb,
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- struct intel_crtc_state *cstate,
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- int level,
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- struct skl_wm_level *result)
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+static int
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+skl_compute_wm_level(const struct drm_i915_private *dev_priv,
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+ struct skl_ddb_allocation *ddb,
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+ struct intel_crtc_state *cstate,
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+ int level,
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+ struct skl_wm_level *result)
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{
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struct drm_device *dev = dev_priv->dev;
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+ struct drm_atomic_state *state = cstate->base.state;
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struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
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+ struct drm_plane *plane;
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struct intel_plane *intel_plane;
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struct intel_plane_state *intel_pstate;
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uint16_t ddb_blocks;
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enum pipe pipe = intel_crtc->pipe;
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- for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
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+ /*
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+ * We'll only calculate watermarks for planes that are actually
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+ * enabled, so make sure all other planes are set as disabled.
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+ */
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+ memset(result, 0, sizeof(*result));
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+
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+ for_each_intel_plane_mask(dev, intel_plane, cstate->base.plane_mask) {
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int i = skl_wm_plane_id(intel_plane);
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- intel_pstate = to_intel_plane_state(intel_plane->base.state);
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+ plane = &intel_plane->base;
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+ intel_pstate = NULL;
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+ if (state)
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+ intel_pstate =
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+ intel_atomic_get_existing_plane_state(state,
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+ intel_plane);
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+
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+ /*
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+ * Note: If we start supporting multiple pending atomic commits
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+ * against the same planes/CRTC's in the future, plane->state
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+ * will no longer be the correct pre-state to use for the
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+ * calculations here and we'll need to change where we get the
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+ * 'unchanged' plane data from.
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+ *
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+ * For now this is fine because we only allow one queued commit
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+ * against a CRTC. Even if the plane isn't modified by this
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+ * transaction and we don't have a plane lock, we still have
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+ * the CRTC's lock, so we know that no other transactions are
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+ * racing with us to update it.
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+ */
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+ if (!intel_pstate)
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+ intel_pstate = to_intel_plane_state(plane->state);
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+
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+ WARN_ON(!intel_pstate->base.fb);
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+
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ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
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result->plane_en[i] = skl_compute_plane_wm(dev_priv,
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@@ -3354,6 +3387,8 @@ static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
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&result->plane_res_b[i],
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&result->plane_res_l[i]);
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}
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+
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+ return 0;
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}
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static uint32_t
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@@ -3648,14 +3683,14 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
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}
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}
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-static bool skl_update_pipe_wm(struct drm_crtc *crtc,
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+static bool skl_update_pipe_wm(struct drm_crtc_state *cstate,
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struct skl_ddb_allocation *ddb, /* out */
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struct skl_pipe_wm *pipe_wm /* out */)
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{
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- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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- struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
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+ struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
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+ struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
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- skl_build_pipe_wm(cstate, ddb, pipe_wm);
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+ skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
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if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
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return false;
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@@ -3695,7 +3730,7 @@ static void skl_update_other_pipe_wm(struct drm_device *dev,
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if (!intel_crtc->active)
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continue;
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- wm_changed = skl_update_pipe_wm(&intel_crtc->base,
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+ wm_changed = skl_update_pipe_wm(intel_crtc->base.state,
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&r->ddb, &pipe_wm);
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/*
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@@ -3813,7 +3848,7 @@ static void skl_update_wm(struct drm_crtc *crtc)
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skl_clear_wm(results, intel_crtc->pipe);
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- if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
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+ if (!skl_update_pipe_wm(crtc->state, &results->ddb, pipe_wm))
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return;
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skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
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--
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2.7.4
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