7d2c2f2d91
(rhbz 1305038) - Disable fbc on haswell by default (fdo#96461)
85 lines
3.2 KiB
Diff
85 lines
3.2 KiB
Diff
From 7207eecfcb3095442bce30227b551003edc7b908 Mon Sep 17 00:00:00 2001
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From: Matt Roper <matthew.d.roper@intel.com>
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Date: Thu, 12 May 2016 07:06:02 -0700
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Subject: [PATCH 08/17] drm/i915: Add distrust_bios_wm flag to dev_priv (v2)
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SKL-style platforms can't fully trust the watermark/DDB settings
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programmed by the BIOS and need to do extra sanitization on their first
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atomic update. Add a flag to dev_priv that is set during hardware
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readout and cleared at the end of the first commit.
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Note that for the somewhat common case where everything is turned off
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when the driver starts up, we don't need to bother with a recompute...we
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know exactly what the DDB should be (all zero's) so just setup the DDB
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directly in that case.
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v2:
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- Move clearing of distrust_bios_wm up below the swap_state call since
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it's a more natural / self-explanatory location. (Maarten)
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- Use dev_priv->active_crtcs to test whether any CRTC's are turned on
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during HW WM readout rather than trying to count the active CRTC's
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again ourselves. (Maarten)
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Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Link: http://patchwork.freedesktop.org/patch/msgid/1463061971-19638-9-git-send-email-matthew.d.roper@intel.com
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---
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drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
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drivers/gpu/drm/i915/intel_display.c | 1 +
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drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
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3 files changed, 16 insertions(+)
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diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
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index 611c128..e21960d 100644
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--- a/drivers/gpu/drm/i915/i915_drv.h
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+++ b/drivers/gpu/drm/i915/i915_drv.h
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@@ -1981,6 +1981,13 @@ struct drm_i915_private {
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* cstate->wm.need_postvbl_update.
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*/
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struct mutex wm_mutex;
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+
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+ /*
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+ * Set during HW readout of watermarks/DDB. Some platforms
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+ * need to know when we're still using BIOS-provided values
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+ * (which we don't fully trust).
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+ */
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+ bool distrust_bios_wm;
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} wm;
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struct i915_runtime_pm pm;
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index f26d1c5..a9d2e30 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -13621,6 +13621,7 @@ static int intel_atomic_commit(struct drm_device *dev,
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drm_atomic_helper_swap_state(dev, state);
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dev_priv->wm.config = intel_state->wm_config;
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+ dev_priv->wm.distrust_bios_wm = false;
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intel_shared_dpll_commit(state);
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if (intel_state->modeset) {
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index f009d43..a49faa7 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -4026,6 +4026,14 @@ void skl_wm_get_hw_state(struct drm_device *dev)
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
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skl_pipe_wm_get_hw_state(crtc);
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+ if (dev_priv->active_crtcs) {
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+ /* Fully recompute DDB on first atomic commit */
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+ dev_priv->wm.distrust_bios_wm = true;
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+ } else {
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+ /* Easy/common case; just sanitize DDB now if everything off */
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+ memset(ddb, 0, sizeof(*ddb));
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+ }
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+
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/* Calculate plane data rates */
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for_each_intel_crtc(dev, intel_crtc) {
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struct intel_crtc_state *cstate = intel_crtc->config;
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--
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2.7.4
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