303 lines
10 KiB
Diff
303 lines
10 KiB
Diff
From 664f87c5bfcc7798bd5b16e14792f1e9ba2956ea Mon Sep 17 00:00:00 2001
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From: Matt Roper <matthew.d.roper@intel.com>
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Date: Thu, 12 May 2016 15:11:40 -0700
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Subject: [PATCH 15/17] drm/i915/gen9: Calculate watermarks during atomic
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'check' (v2)
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Moving watermark calculation into the check phase will allow us to to
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reject display configurations for which there are no valid watermark
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values before we start trying to program the hardware (although those
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tests will come in a subsequent patch).
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Another advantage of moving this calculation to the check phase is that
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we can calculate the watermarks in a single shot as part of the atomic
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transaction. The watermark interfaces we inherited from our legacy
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modesetting days are a bit broken in the atomic design because they use
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per-crtc entry points but actually re-calculate and re-program something
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that is really more of a global state. That worked okay in the legacy
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modesetting world because operations only ever updated a single CRTC at
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a time. However in the atomic world, a transaction can involve multiple
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CRTC's, which means we wind up computing and programming the watermarks
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NxN times (where N is the number of CRTC's involved). With this patch
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we eliminate the redundant re-calculation of watermark data for atomic
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states (which was the cause of the WARN_ON(!wm_changed) problems that
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have plagued us for a while).
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We still need to work on the 'commit' side of watermark handling so that
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we aren't doing redundant NxN programming of watermarks, but that's
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content for future patches.
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v2:
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- Bail out of skl_write_wm_values() if the CRTC isn't active. Now that
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we set dirty_pipes to ~0 if the active pipes change (because
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we need to deal with DDB changes), we can now wind up here for
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disabled pipes, whereas we couldn't before.
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89055
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181
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Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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Tested-by: Daniel Stone <daniels@collabora.com>
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Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Link: http://patchwork.freedesktop.org/patch/msgid/1463091100-13747-1-git-send-email-matthew.d.roper@intel.com
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---
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drivers/gpu/drm/i915/intel_display.c | 2 +-
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drivers/gpu/drm/i915/intel_drv.h | 2 +-
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drivers/gpu/drm/i915/intel_pm.c | 140 +++++++++++++----------------------
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3 files changed, 54 insertions(+), 90 deletions(-)
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index 2190bac..a75daac 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -13627,7 +13627,7 @@ static int intel_atomic_commit(struct drm_device *dev,
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drm_atomic_helper_swap_state(dev, state);
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dev_priv->wm.config = intel_state->wm_config;
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dev_priv->wm.distrust_bios_wm = false;
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- dev_priv->wm.skl_results.ddb = intel_state->ddb;
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+ dev_priv->wm.skl_results = intel_state->wm_results;
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intel_shared_dpll_commit(state);
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if (intel_state->modeset) {
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diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
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index 2218290..ab0be7a 100644
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--- a/drivers/gpu/drm/i915/intel_drv.h
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+++ b/drivers/gpu/drm/i915/intel_drv.h
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@@ -314,7 +314,7 @@ struct intel_atomic_state {
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bool skip_intermediate_wm;
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/* Gen9+ only */
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- struct skl_ddb_allocation ddb;
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+ struct skl_wm_values wm_results;
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};
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struct intel_plane_state {
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index 342aa66..b072417 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -3221,23 +3221,6 @@ static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
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return ret;
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}
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-static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
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- const struct intel_crtc *intel_crtc)
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-{
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- struct drm_device *dev = intel_crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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- const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
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-
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- /*
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- * If ddb allocation of pipes changed, it may require recalculation of
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- * watermarks
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- */
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- if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
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- return true;
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-
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- return false;
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-}
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-
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static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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struct intel_crtc_state *cstate,
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struct intel_plane_state *intel_pstate,
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@@ -3533,6 +3516,8 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv,
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if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
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continue;
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+ if (!crtc->active)
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+ continue;
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I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
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@@ -3716,66 +3701,9 @@ static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
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else
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*changed = true;
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- intel_crtc->wm.active.skl = *pipe_wm;
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-
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return 0;
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}
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-static void skl_update_other_pipe_wm(struct drm_device *dev,
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- struct drm_crtc *crtc,
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- struct skl_wm_values *r)
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-{
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- struct intel_crtc *intel_crtc;
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- struct intel_crtc *this_crtc = to_intel_crtc(crtc);
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-
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- /*
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- * If the WM update hasn't changed the allocation for this_crtc (the
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- * crtc we are currently computing the new WM values for), other
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- * enabled crtcs will keep the same allocation and we don't need to
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- * recompute anything for them.
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- */
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- if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
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- return;
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-
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- /*
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- * Otherwise, because of this_crtc being freshly enabled/disabled, the
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- * other active pipes need new DDB allocation and WM values.
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- */
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- for_each_intel_crtc(dev, intel_crtc) {
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- struct skl_pipe_wm pipe_wm = {};
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- bool wm_changed;
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-
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- if (this_crtc->pipe == intel_crtc->pipe)
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- continue;
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-
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- if (!intel_crtc->active)
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- continue;
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-
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- skl_update_pipe_wm(intel_crtc->base.state,
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- &r->ddb, &pipe_wm, &wm_changed);
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-
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- /*
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- * If we end up re-computing the other pipe WM values, it's
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- * because it was really needed, so we expect the WM values to
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- * be different.
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- */
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- WARN_ON(!wm_changed);
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-
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- skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
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- r->dirty_pipes |= drm_crtc_mask(&intel_crtc->base);
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- }
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-}
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-
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-static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
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-{
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- watermarks->wm_linetime[pipe] = 0;
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- memset(watermarks->plane[pipe], 0,
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- sizeof(uint32_t) * 8 * I915_MAX_PLANES);
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- memset(watermarks->plane_trans[pipe],
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- 0, sizeof(uint32_t) * I915_MAX_PLANES);
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- watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
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-}
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-
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static int
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skl_compute_ddb(struct drm_atomic_state *state)
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{
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@@ -3783,6 +3711,7 @@ skl_compute_ddb(struct drm_atomic_state *state)
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
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struct intel_crtc *intel_crtc;
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+ struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
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unsigned realloc_pipes = dev_priv->active_crtcs;
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int ret;
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@@ -3808,8 +3737,10 @@ skl_compute_ddb(struct drm_atomic_state *state)
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* any other display updates race with this transaction, so we need
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* to grab the lock on *all* CRTC's.
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*/
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- if (intel_state->active_pipe_changes)
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+ if (intel_state->active_pipe_changes) {
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realloc_pipes = ~0;
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+ intel_state->wm_results.dirty_pipes = ~0;
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+ }
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for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
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struct intel_crtc_state *cstate;
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@@ -3818,7 +3749,7 @@ skl_compute_ddb(struct drm_atomic_state *state)
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if (IS_ERR(cstate))
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return PTR_ERR(cstate);
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- ret = skl_allocate_pipe_ddb(cstate, &intel_state->ddb);
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+ ret = skl_allocate_pipe_ddb(cstate, ddb);
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if (ret)
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return ret;
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}
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@@ -3831,8 +3762,11 @@ skl_compute_wm(struct drm_atomic_state *state)
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{
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struct drm_crtc *crtc;
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struct drm_crtc_state *cstate;
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- int ret, i;
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+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
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+ struct skl_wm_values *results = &intel_state->wm_results;
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+ struct skl_pipe_wm *pipe_wm;
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bool changed = false;
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+ int ret, i;
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/*
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* If this transaction isn't actually touching any CRTC's, don't
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@@ -3847,10 +3781,45 @@ skl_compute_wm(struct drm_atomic_state *state)
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if (!changed)
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return 0;
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+ /* Clear all dirty flags */
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+ results->dirty_pipes = 0;
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+
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ret = skl_compute_ddb(state);
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if (ret)
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return ret;
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+ /*
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+ * Calculate WM's for all pipes that are part of this transaction.
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+ * Note that the DDB allocation above may have added more CRTC's that
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+ * weren't otherwise being modified (and set bits in dirty_pipes) if
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+ * pipe allocations had to change.
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+ *
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+ * FIXME: Now that we're doing this in the atomic check phase, we
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+ * should allow skl_update_pipe_wm() to return failure in cases where
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+ * no suitable watermark values can be found.
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+ */
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+ for_each_crtc_in_state(state, crtc, cstate, i) {
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+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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+ struct intel_crtc_state *intel_cstate =
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+ to_intel_crtc_state(cstate);
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+
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+ pipe_wm = &intel_cstate->wm.skl.optimal;
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+ ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
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+ &changed);
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+ if (ret)
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+ return ret;
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+
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+ if (changed)
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+ results->dirty_pipes |= drm_crtc_mask(crtc);
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+
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+ if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
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+ /* This pipe's WM's did not change */
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+ continue;
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+
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+ intel_cstate->update_wm_pre = true;
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+ skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
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+ }
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+
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return 0;
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}
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@@ -3862,26 +3831,21 @@ static void skl_update_wm(struct drm_crtc *crtc)
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struct skl_wm_values *results = &dev_priv->wm.skl_results;
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struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
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struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
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- bool wm_changed;
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-
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- /* Clear all dirty flags */
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- results->dirty_pipes = 0;
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- skl_clear_wm(results, intel_crtc->pipe);
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-
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- skl_update_pipe_wm(crtc->state, &results->ddb, pipe_wm, &wm_changed);
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- if (!wm_changed)
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+ if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
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return;
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- skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
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- results->dirty_pipes |= drm_crtc_mask(&intel_crtc->base);
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+ intel_crtc->wm.active.skl = *pipe_wm;
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+
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+ mutex_lock(&dev_priv->wm.wm_mutex);
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- skl_update_other_pipe_wm(dev, crtc, results);
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skl_write_wm_values(dev_priv, results);
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skl_flush_wm_values(dev_priv, results);
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/* store the new configuration */
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dev_priv->wm.skl_hw = *results;
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+
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+ mutex_unlock(&dev_priv->wm.wm_mutex);
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}
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static void ilk_compute_wm_config(struct drm_device *dev,
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--
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2.7.4
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