205 lines
7.0 KiB
Diff
205 lines
7.0 KiB
Diff
From be60f2176911a4ac8e0450ab51f11c235a4984de Mon Sep 17 00:00:00 2001
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From: Matt Roper <matthew.d.roper@intel.com>
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Date: Thu, 12 May 2016 07:05:57 -0700
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Subject: [PATCH 03/17] drm/i915/gen9: Cache plane data rates in CRTC state
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This will be important when we start calculating CRTC data rates for
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in-flight CRTC states since it will allow us to calculate the total data
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rate without needing to grab the plane state for any planes that aren't
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updated by the transaction.
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Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Link: http://patchwork.freedesktop.org/patch/msgid/1463061971-19638-4-git-send-email-matthew.d.roper@intel.com
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---
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drivers/gpu/drm/i915/intel_drv.h | 4 ++
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drivers/gpu/drm/i915/intel_pm.c | 92 ++++++++++++++++++++++++++--------------
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2 files changed, 63 insertions(+), 33 deletions(-)
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diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
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index 5a186bf..6a95696 100644
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--- a/drivers/gpu/drm/i915/intel_drv.h
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+++ b/drivers/gpu/drm/i915/intel_drv.h
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@@ -427,6 +427,10 @@ struct intel_crtc_wm_state {
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struct {
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/* gen9+ only needs 1-step wm programming */
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struct skl_pipe_wm optimal;
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+
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+ /* cached plane data rate */
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+ unsigned plane_data_rate[I915_MAX_PLANES];
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+ unsigned plane_y_data_rate[I915_MAX_PLANES];
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} skl;
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};
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index e15cb2a..6835614 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -2940,6 +2940,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
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struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
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struct drm_framebuffer *fb = pstate->fb;
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uint32_t width = 0, height = 0;
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+ unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
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+
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+ if (!intel_pstate->visible)
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+ return 0;
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+ if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
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+ return 0;
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+ if (y && format != DRM_FORMAT_NV12)
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+ return 0;
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width = drm_rect_width(&intel_pstate->src) >> 16;
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height = drm_rect_height(&intel_pstate->src) >> 16;
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@@ -2948,17 +2956,17 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
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swap(width, height);
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/* for planar format */
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- if (fb->pixel_format == DRM_FORMAT_NV12) {
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+ if (format == DRM_FORMAT_NV12) {
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if (y) /* y-plane data rate */
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return width * height *
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- drm_format_plane_cpp(fb->pixel_format, 0);
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+ drm_format_plane_cpp(format, 0);
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else /* uv-plane data rate */
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return (width / 2) * (height / 2) *
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- drm_format_plane_cpp(fb->pixel_format, 1);
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+ drm_format_plane_cpp(format, 1);
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}
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/* for packed formats */
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- return width * height * drm_format_plane_cpp(fb->pixel_format, 0);
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+ return width * height * drm_format_plane_cpp(format, 0);
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}
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/*
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@@ -2967,32 +2975,34 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
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* 3 * 4096 * 8192 * 4 < 2^32
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*/
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static unsigned int
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-skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
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+skl_get_total_relative_data_rate(struct intel_crtc_state *cstate)
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
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struct drm_device *dev = intel_crtc->base.dev;
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const struct intel_plane *intel_plane;
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- unsigned int total_data_rate = 0;
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+ unsigned int rate, total_data_rate = 0;
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+ /* Calculate and cache data rate for each plane */
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for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
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const struct drm_plane_state *pstate = intel_plane->base.state;
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+ int id = skl_wm_plane_id(intel_plane);
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- if (pstate->fb == NULL)
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- continue;
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+ /* packed/uv */
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+ rate = skl_plane_relative_data_rate(cstate, pstate, 0);
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+ cstate->wm.skl.plane_data_rate[id] = rate;
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- if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
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- continue;
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+ /* y-plane */
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+ rate = skl_plane_relative_data_rate(cstate, pstate, 1);
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+ cstate->wm.skl.plane_y_data_rate[id] = rate;
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+ }
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- /* packed/uv */
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- total_data_rate += skl_plane_relative_data_rate(cstate,
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- pstate,
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- 0);
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+ /* Calculate CRTC's total data rate from cached values */
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+ for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
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+ int id = skl_wm_plane_id(intel_plane);
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- if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
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- /* y-plane */
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- total_data_rate += skl_plane_relative_data_rate(cstate,
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- pstate,
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- 1);
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+ /* packed/uv */
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+ total_data_rate += cstate->wm.skl.plane_data_rate[id];
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+ total_data_rate += cstate->wm.skl.plane_y_data_rate[id];
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}
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return total_data_rate;
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@@ -3056,6 +3066,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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* FIXME: we may not allocate every single block here.
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*/
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total_data_rate = skl_get_total_relative_data_rate(cstate);
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+ if (total_data_rate == 0)
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+ return;
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start = alloc->start;
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for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
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@@ -3070,7 +3082,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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if (plane->type == DRM_PLANE_TYPE_CURSOR)
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continue;
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- data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
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+ data_rate = cstate->wm.skl.plane_data_rate[id];
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/*
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* allocation for (packed formats) or (uv-plane part of planar format):
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@@ -3089,20 +3101,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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/*
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* allocation for y_plane part of planar format:
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*/
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- if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
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- y_data_rate = skl_plane_relative_data_rate(cstate,
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- pstate,
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- 1);
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- y_plane_blocks = y_minimum[id];
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- y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
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- total_data_rate);
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-
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- ddb->y_plane[pipe][id].start = start;
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- ddb->y_plane[pipe][id].end = start + y_plane_blocks;
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-
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- start += y_plane_blocks;
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- }
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+ y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
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+
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+ y_plane_blocks = y_minimum[id];
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+ y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
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+ total_data_rate);
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+ ddb->y_plane[pipe][id].start = start;
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+ ddb->y_plane[pipe][id].end = start + y_plane_blocks;
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+
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+ start += y_plane_blocks;
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}
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}
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@@ -3879,10 +3887,28 @@ void skl_wm_get_hw_state(struct drm_device *dev)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
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struct drm_crtc *crtc;
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+ struct intel_crtc *intel_crtc;
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skl_ddb_get_hw_state(dev_priv, ddb);
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
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skl_pipe_wm_get_hw_state(crtc);
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+
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+ /* Calculate plane data rates */
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+ for_each_intel_crtc(dev, intel_crtc) {
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+ struct intel_crtc_state *cstate = intel_crtc->config;
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+ struct intel_plane *intel_plane;
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+
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+ for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
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+ const struct drm_plane_state *pstate =
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+ intel_plane->base.state;
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+ int id = skl_wm_plane_id(intel_plane);
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+
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+ cstate->wm.skl.plane_data_rate[id] =
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+ skl_plane_relative_data_rate(cstate, pstate, 0);
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+ cstate->wm.skl.plane_y_data_rate[id] =
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+ skl_plane_relative_data_rate(cstate, pstate, 1);
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+ }
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+ }
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}
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static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
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--
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2.7.4
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