48 lines
1.9 KiB
Diff
48 lines
1.9 KiB
Diff
From patchwork Sat Sep 23 06:17:40 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: PCI: tegra: Use different MSI target address for Tegra20
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From: Thierry Reding <thierry.reding@gmail.com>
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X-Patchwork-Id: 9967397
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Message-Id: <20170923061740.6012-1-treding@nvidia.com>
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To: Bjorn Helgaas <bhelgaas@google.com>
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Cc: Thierry Reding <thierry.reding@gmail.com>,
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Jonathan Hunter <jonathanh@nvidia.com>,
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linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org
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Date: Fri, 22 Sep 2017 23:17:40 -0700
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The Tegra20 PCIe controller has a different address range for MSI, so
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select a different target address.
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Fixes: d7bd554f27c9 ("PCI: tegra: Do not allocate MSI target memory")
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Signed-off-by: Thierry Reding <treding@nvidia.com>
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---
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drivers/pci/host/pci-tegra.c | 12 +++++++++++-
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1 file changed, 11 insertions(+), 1 deletion(-)
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diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
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index e8e1ddbaabc9..5b02ea59524b 100644
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--- a/drivers/pci/host/pci-tegra.c
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+++ b/drivers/pci/host/pci-tegra.c
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@@ -1563,8 +1563,18 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
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* none of the Tegra SoCs that contain this PCI host bridge can
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* address more than 16 GiB of system memory, the last 4 KiB of
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* these 1012 GiB is a good candidate.
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+ *
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+ * Unfortunately, Tegra20 is slightly different in that the physical
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+ * address for this MSI region is limited to the lower 32 bits of the
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+ * address map, so the address that we pick is going to have to be
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+ * located somewhere within the region addressable by the CPU and
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+ * on-SoC controllers. To be on the safe side, we select an address
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+ * from a region that is marked unused (0xf0010000 - 0xfffeffff).
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*/
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- msi->phys = 0xfcfffff000;
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+ if (soc->msi_base_shift > 0)
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+ msi->phys = 0xfcfffff000;
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+ else
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+ msi->phys = 0x00f0010000;
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afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
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afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);
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