57 lines
1.8 KiB
Diff
57 lines
1.8 KiB
Diff
From 52994c256df36fda9a715697431cba9daecb6b11 Mon Sep 17 00:00:00 2001
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From: Thomas Gleixner <tglx@linutronix.de>
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Date: Wed, 3 Jan 2018 15:57:59 +0100
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Subject: x86/pti: Make sure the user/kernel PTEs match
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Meelis reported that his K8 Athlon64 emits MCE warnings when PTI is
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enabled:
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[Hardware Error]: Error Addr: 0x0000ffff81e000e0
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[Hardware Error]: MC1 Error: L1 TLB multimatch.
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[Hardware Error]: cache level: L1, tx: INSN
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The address is in the entry area, which is mapped into kernel _AND_ user
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space. That's special because we switch CR3 while we are executing
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there.
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User mapping:
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0xffffffff81e00000-0xffffffff82000000 2M ro PSE GLB x pmd
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Kernel mapping:
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0xffffffff81000000-0xffffffff82000000 16M ro PSE x pmd
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So the K8 is complaining that the TLB entries differ. They differ in the
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GLB bit.
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Drop the GLB bit when installing the user shared mapping.
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Fixes: 6dc72c3cbca0 ("x86/mm/pti: Share entry text PMD")
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Reported-by: Meelis Roos <mroos@linux.ee>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Tested-by: Meelis Roos <mroos@linux.ee>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Tom Lendacky <thomas.lendacky@amd.com>
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Cc: stable@vger.kernel.org
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Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801031407180.1957@nanos
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---
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arch/x86/mm/pti.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c
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index bce8aea..2da28ba 100644
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--- a/arch/x86/mm/pti.c
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+++ b/arch/x86/mm/pti.c
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@@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(void)
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static void __init pti_clone_entry_text(void)
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{
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pti_clone_pmds((unsigned long) __entry_text_start,
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- (unsigned long) __irqentry_text_end, _PAGE_RW);
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+ (unsigned long) __irqentry_text_end,
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+ _PAGE_RW | _PAGE_GLOBAL);
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}
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/*
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--
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cgit v1.1
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