131 lines
4.1 KiB
Diff
131 lines
4.1 KiB
Diff
From caf38f4702a75c7ba13d5d80d902812c5faa8501 Mon Sep 17 00:00:00 2001
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From: Joel Fernandes <joelf@ti.com>
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Date: Thu, 27 Jun 2013 20:18:52 -0500
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Subject: [PATCH 10/13] DMA: EDMA: Add support for Cyclic DMA
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Using the PaRAM configuration function that we split for reuse by the
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different DMA types, we implement Cyclic DMA support.
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For the cyclic case, we pass different configuration paramters to this
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function, and add all the Cyclic-specific code separately.
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Callbacks are handled transparently as usual by the virt-dma layer.
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Linking is handled the same way as the slave SG case.
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Signed-off-by: Joel Fernandes <joelf@ti.com>
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---
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drivers/dma/edma.c | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 85 insertions(+)
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diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
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index 87b7e2b..cec9a12 100644
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--- a/drivers/dma/edma.c
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+++ b/drivers/dma/edma.c
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@@ -321,6 +321,88 @@ static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset,
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return absync;
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}
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+static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
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+ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
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+ size_t period_len, enum dma_transfer_direction direction, unsigned long flags,
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+ void *context)
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+{
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+ struct edma_chan *echan = to_edma_chan(chan);
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+ struct device *dev = chan->device->dev;
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+ struct edma_desc *edesc;
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+ dma_addr_t src_addr, dst_addr;
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+ enum dma_slave_buswidth dev_width;
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+ u32 burst;
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+ int i, ret, nr_periods;
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+
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+ if (unlikely(!echan || !buf_len || !period_len))
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+ return NULL;
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+
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+ if (direction == DMA_DEV_TO_MEM) {
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+ src_addr = echan->cfg.src_addr;
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+ dst_addr = buf_addr;
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+ dev_width = echan->cfg.src_addr_width;
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+ burst = echan->cfg.src_maxburst;
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+ } else if (direction == DMA_MEM_TO_DEV) {
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+ src_addr = buf_addr;
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+ dst_addr = echan->cfg.dst_addr;
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+ dev_width = echan->cfg.dst_addr_width;
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+ burst = echan->cfg.dst_maxburst;
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+ } else {
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+ dev_err(dev, "%s: bad direction?\n", __func__);
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+ return NULL;
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+ }
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+
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+ if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
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+ dev_err(dev, "Undefined slave buswidth\n");
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+ return NULL;
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+ }
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+
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+ if(unlikely(period_len % buf_len)) {
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+ dev_err(dev, "Period should be multiple of Buf length\n");
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+ return NULL;
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+ }
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+
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+ nr_periods = period_len / buf_len;
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+
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+ edesc = kzalloc(sizeof(*edesc) + nr_periods *
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+ sizeof(edesc->pset[0]), GFP_ATOMIC);
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+ if (!edesc) {
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+ dev_dbg(dev, "Failed to allocate a descriptor\n");
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+ return NULL;
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+ }
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+
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+ edesc->pset_nr = nr_periods;
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+
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+ for(i = 0; i < nr_periods; i++) {
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+ /* Allocate a PaRAM slot, if needed */
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+ if (echan->slot[i] < 0) {
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+ echan->slot[i] =
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+ edma_alloc_slot(EDMA_CTLR(echan->ch_num),
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+ EDMA_SLOT_ANY);
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+ if (echan->slot[i] < 0) {
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+ dev_err(dev, "Failed to allocate slot\n");
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+ return NULL;
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+ }
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+ }
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+
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+ if (direction == DMA_DEV_TO_MEM)
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+ dst_addr += period_len;
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+ else
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+ src_addr += period_len;
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+
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+ ret = edma_config_pset(chan, &edesc->pset[i], src_addr, dst_addr,
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+ burst, dev_width, period_len, direction);
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+ if(ret < 0)
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+ return NULL;
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+
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+ edesc->absync = ret;
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+ if (i == nr_periods - 1)
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+ edesc->pset[i].opt |= TCINTEN;
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+ }
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+ /* TODO tx_flags (last parameter) needs to be investigated...\n" */
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+ return vchan_tx_prep(&echan->vchan, &edesc->vdesc, 0);
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+}
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+
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static struct dma_async_tx_descriptor *edma_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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@@ -424,6 +506,8 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
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edesc = echan->edesc;
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if (edesc) {
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edma_execute(echan);
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+ /* Note: that desc->callback must be setup by EDMA users so that
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+ the virt-dma layer calls their callback on vchan_cookie_complete() */
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vchan_cookie_complete(&edesc->vdesc);
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}
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@@ -605,6 +689,7 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
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struct device *dev)
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{
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dma->device_prep_slave_sg = edma_prep_slave_sg;
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+ dma->device_prep_dma_cyclic = edma_prep_dma_cyclic;
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dma->device_alloc_chan_resources = edma_alloc_chan_resources;
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dma->device_free_chan_resources = edma_free_chan_resources;
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dma->device_issue_pending = edma_issue_pending;
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--
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1.8.2.1
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