c1d5388741
* Thu May 28 2020 CKI@GitLab <cki-project@redhat.com> [5.7.0-0.rc7.20200528gitb0c3ba31be3e.1]
- b0c3ba31be3e rebase
- Updated changelog for the release based on 444fc5cde643 ("CKI@GitLab")
Resolves: rhbz#
Signed-off-by: Justin M. Forbes <jforbes@fedoraproject.org>
114 lines
3.7 KiB
Diff
114 lines
3.7 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Ben Skeggs <bskeggs@redhat.com>
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Date: Thu, 30 Apr 2020 14:08:53 +1000
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Subject: [PATCH] device: use regular PRI accessors in chipset detection
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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---
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.../gpu/drm/nouveau/nvkm/engine/device/base.c | 31 ++++++++-----------
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1 file changed, 13 insertions(+), 18 deletions(-)
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diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
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index f977dddcd809..5b90c2a1bf3d 100644
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--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
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+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
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@@ -2925,9 +2925,9 @@ nvkm_device_del(struct nvkm_device **pdevice)
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}
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static inline bool
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-nvkm_device_endianness(void __iomem *pri)
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+nvkm_device_endianness(struct nvkm_device *device)
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{
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- u32 boot1 = ioread32_native(pri + 0x000004) & 0x01000001;
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+ u32 boot1 = nvkm_rd32(device, 0x000004) & 0x01000001;
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#ifdef __BIG_ENDIAN
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if (!boot1)
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return false;
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@@ -2949,7 +2949,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
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struct nvkm_subdev *subdev;
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u64 mmio_base, mmio_size;
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u32 boot0, boot1, strap;
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- void __iomem *map = NULL;
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int ret = -EEXIST, i;
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unsigned chipset;
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@@ -2976,8 +2975,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
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mmio_size = device->func->resource_size(device, 0);
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if (detect || mmio) {
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- map = ioremap(mmio_base, mmio_size);
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- if (map == NULL) {
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+ device->pri = ioremap(mmio_base, mmio_size);
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+ if (device->pri == NULL) {
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nvdev_error(device, "unable to map PRI\n");
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ret = -ENOMEM;
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goto done;
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@@ -2987,10 +2986,10 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
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/* identify the chipset, and determine classes of subdev/engines */
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if (detect) {
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/* switch mmio to cpu's native endianness */
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- if (!nvkm_device_endianness(map)) {
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- iowrite32_native(0x01000001, map + 0x000004);
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- ioread32_native(map);
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- if (!nvkm_device_endianness(map)) {
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+ if (!nvkm_device_endianness(device)) {
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+ nvkm_wr32(device, 0x000004, 0x01000001);
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+ nvkm_rd32(device, 0x000000);
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+ if (!nvkm_device_endianness(device)) {
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nvdev_error(device,
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"GPU not supported on big-endian\n");
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ret = -ENOSYS;
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@@ -2998,7 +2997,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
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}
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}
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- boot0 = ioread32_native(map + 0x000000);
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+ boot0 = nvkm_rd32(device, 0x000000);
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/* chipset can be overridden for devel/testing purposes */
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chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0);
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@@ -3157,7 +3156,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
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device->chip->name, boot0);
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/* vGPU detection */
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- boot1 = ioread32_native(map + 0x000004);
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+ boot1 = nvkm_rd32(device, 0x0000004);
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if (device->card_type >= TU100 && (boot1 & 0x00030000)) {
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nvdev_info(device, "vGPUs are not supported\n");
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ret = -ENODEV;
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@@ -3165,7 +3164,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
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}
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/* read strapping information */
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- strap = ioread32_native(map + 0x101000);
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+ strap = nvkm_rd32(device, 0x101000);
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/* determine frequency of timing crystal */
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if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
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@@ -3187,10 +3186,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
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if (!device->name)
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device->name = device->chip->name;
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- if (mmio) {
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- device->pri = map;
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- }
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-
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mutex_init(&device->mutex);
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for (i = 0; i < NVKM_SUBDEV_NR; i++) {
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@@ -3278,9 +3273,9 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
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ret = 0;
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done:
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- if (map && (!mmio || ret)) {
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+ if (device->pri && (!mmio || ret)) {
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+ iounmap(device->pri);
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device->pri = NULL;
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- iounmap(map);
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}
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mutex_unlock(&nv_devices_mutex);
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return ret;
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--
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2.26.2
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