Andrew Lukoshko
ca61dd79c6
Add the RHEL 687.11.1..687.12.1 backports (1198-1252) sourced from centos-stream-9 and upstream stable, on top of 687.10.1. Bump to 5.14.0-687.12.1.
81 lines
3.3 KiB
Diff
81 lines
3.3 KiB
Diff
From 56a643aed0f0af5c29ebb4593d4917b78344dd48 Mon Sep 17 00:00:00 2001
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From: Petr Oros <poros@redhat.com>
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Date: Mon, 27 Apr 2026 22:22:19 -0700
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Subject: [PATCH] ice: fix missing SMA pin initialization in DPLL subsystem
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The DPLL SMA/U.FL pin redesign introduced ice_dpll_sw_pin_frequency_get()
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which gates frequency reporting on the pin's active flag. This flag is
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determined by ice_dpll_sw_pins_update() from the PCA9575 GPIO expander
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state. Before the redesign, SMA pins were exposed as direct HW
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input/output pins and ice_dpll_frequency_get() returned the CGU
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frequency unconditionally — the PCA9575 state was never consulted.
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The PCA9575 powers on with all outputs high, setting ICE_SMA1_DIR_EN,
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ICE_SMA1_TX_EN, ICE_SMA2_DIR_EN and ICE_SMA2_TX_EN. Nothing in the
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driver writes the register during initialization, so
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ice_dpll_sw_pins_update() sees all pins as inactive and
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ice_dpll_sw_pin_frequency_get() permanently returns 0 Hz for every
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SW pin.
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Fix this by writing a default SMA configuration in
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ice_dpll_init_info_sw_pins(): clear all SMA bits, then set SMA1 and
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SMA2 as active inputs (DIR_EN=0) with U.FL1 output and U.FL2 input
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disabled. Each SMA/U.FL pair shares a physical signal path so only
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one pin per pair can be active at a time. U.FL pins still report
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frequency 0 after this fix: U.FL1 (output-only) is disabled by
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ICE_SMA1_TX_EN which keeps the TX output buffer off, and U.FL2
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(input-only) is disabled by ICE_SMA2_UFL2_RX_DIS. They can be
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activated by changing the corresponding SMA pin direction via dpll
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netlink.
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Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
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Signed-off-by: Petr Oros <poros@redhat.com>
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Reviewed-by: Ivan Vecera <ivecera@redhat.com>
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Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
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Tested-by: Alexander Nowlin <alexander.nowlin@intel.com>
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Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
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Link: https://patch.msgid.link/20260427-jk-iwl-net-petr-oros-fixes-v1-7-cdcb48303fd8@intel.com
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
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index 62f75701d652..498ec2c045f3 100644
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--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
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+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
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@@ -4014,6 +4014,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf)
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struct ice_dpll_pin *pin;
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u32 phase_adj_max, caps;
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int i, ret;
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+ u8 data;
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if (pf->hw.device_id == ICE_DEV_ID_E810C_QSFP)
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input_idx_offset = ICE_E810_RCLK_PINS_NUM;
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@@ -4073,6 +4074,22 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf)
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}
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ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max);
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}
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+
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+ /* Initialize the SMA control register to a known-good default state.
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+ * Without this write the PCA9575 GPIO expander retains its power-on
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+ * default (all outputs high) which makes all SW pins appear inactive.
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+ * Set SMA1 and SMA2 as active inputs, disable U.FL1 output and
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+ * U.FL2 input.
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+ */
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+ ret = ice_read_sma_ctrl(&pf->hw, &data);
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+ if (ret)
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+ return ret;
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+ data &= ~ICE_ALL_SMA_MASK;
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+ data |= ICE_SMA1_TX_EN | ICE_SMA2_TX_EN | ICE_SMA2_UFL2_RX_DIS;
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+ ret = ice_write_sma_ctrl(&pf->hw, data);
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+ if (ret)
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+ return ret;
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+
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ret = ice_dpll_pin_state_update(pf, pin, ICE_DPLL_PIN_TYPE_SOFTWARE,
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NULL);
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if (ret)
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--
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2.50.1 (Apple Git-155)
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