Andrew Lukoshko
f6916a8ae1
Add the RHEL 211.19.1..211.20.1 backports (1245-1287) from centos-stream-10 and upstream, on top of 211.18.1, plus the dpll RHEL kABI adaptation (1287). RHEL now ships the smb cifs.spnego fix too; the existing ahead-fix 1105 is byte-identical, so RHEL's redundant copy is omitted. Bump to 211.20.1.
326 lines
10 KiB
Diff
326 lines
10 KiB
Diff
From ef38c6a6c3f4e6f931e21f54c88741a1a0c84f27 Mon Sep 17 00:00:00 2001
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From: Ivan Vecera <ivecera@redhat.com>
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Date: Wed, 29 Apr 2026 14:55:45 +0200
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Subject: [PATCH] dpll: zl3073x: add ref-sync pair support
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JIRA: https://issues.redhat.com/browse/RHEL-157828
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commit 14f269ae699869ddaca7c29c9c6c52288e3bfb73
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Author: Ivan Vecera <ivecera@redhat.com>
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Date: Wed Apr 8 12:27:16 2026 +0200
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dpll: zl3073x: add ref-sync pair support
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Add support for ref-sync pair registration using the 'ref-sync-sources'
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phandle property from device tree. A ref-sync pair consists of a clock
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reference and a low-frequency sync signal where the DPLL locks to the
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clock reference but phase-aligns to the sync reference.
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The implementation:
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- Stores fwnode handle in zl3073x_dpll_pin during pin registration
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- Adds ref_sync_get/set callbacks to read and write the sync control
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mode and pair registers
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- Validates ref-sync frequency constraints: sync signal must be 8 kHz
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or less, clock reference must be 1 kHz or more and higher than sync
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- Excludes sync source from automatic reference selection by setting
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its priority to NONE on connect; on disconnect the priority is left
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as NONE and the user must explicitly make the pin selectable again
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- Iterates ref-sync-sources phandles to register declared pairings
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via dpll_pin_ref_sync_pair_add()
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Reviewed-by: Petr Oros <poros@redhat.com>
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Reviewed-by: Prathosh Satish <Prathosh.Satish@microchip.com>
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Signed-off-by: Ivan Vecera <ivecera@redhat.com>
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Link: https://patch.msgid.link/20260408102716.443099-6-ivecera@redhat.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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(cherry picked from commit 14f269ae699869ddaca7c29c9c6c52288e3bfb73)
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Assisted-by: Patchpal
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Signed-off-by: Ivan Vecera <ivecera@redhat.com>
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diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c
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index a151be700e6e..55195dcd21d6 100644
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--- a/drivers/dpll/zl3073x/dpll.c
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+++ b/drivers/dpll/zl3073x/dpll.c
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@@ -13,6 +13,7 @@
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#include <linux/module.h>
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#include <linux/netlink.h>
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#include <linux/platform_device.h>
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+#include <linux/property.h>
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#include <linux/slab.h>
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#include <linux/sprintf.h>
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@@ -30,6 +31,7 @@
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* @dpll: DPLL the pin is registered to
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* @dpll_pin: pointer to registered dpll_pin
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* @tracker: tracking object for the acquired reference
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+ * @fwnode: firmware node handle
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* @label: package label
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* @dir: pin direction
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* @id: pin id
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@@ -46,6 +48,7 @@ struct zl3073x_dpll_pin {
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struct zl3073x_dpll *dpll;
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struct dpll_pin *dpll_pin;
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dpll_tracker tracker;
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+ struct fwnode_handle *fwnode;
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char label[8];
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enum dpll_pin_direction dir;
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u8 id;
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@@ -186,6 +189,109 @@ zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin,
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return zl3073x_ref_state_set(zldev, ref_id, &ref);
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}
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+static int
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+zl3073x_dpll_input_pin_ref_sync_get(const struct dpll_pin *dpll_pin,
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+ void *pin_priv,
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+ const struct dpll_pin *ref_sync_pin,
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+ void *ref_sync_pin_priv,
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+ enum dpll_pin_state *state,
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+ struct netlink_ext_ack *extack)
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+{
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+ struct zl3073x_dpll_pin *sync_pin = ref_sync_pin_priv;
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+ struct zl3073x_dpll_pin *pin = pin_priv;
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+ struct zl3073x_dpll *zldpll = pin->dpll;
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+ struct zl3073x_dev *zldev = zldpll->dev;
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+ const struct zl3073x_ref *ref;
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+ u8 ref_id, mode, pair;
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+
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+ ref_id = zl3073x_input_pin_ref_get(pin->id);
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+ ref = zl3073x_ref_state_get(zldev, ref_id);
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+ mode = zl3073x_ref_sync_mode_get(ref);
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+ pair = zl3073x_ref_sync_pair_get(ref);
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+
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+ if (mode == ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR &&
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+ pair == zl3073x_input_pin_ref_get(sync_pin->id))
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+ *state = DPLL_PIN_STATE_CONNECTED;
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+ else
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+ *state = DPLL_PIN_STATE_DISCONNECTED;
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+
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+ return 0;
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+}
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+
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+static int
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+zl3073x_dpll_input_pin_ref_sync_set(const struct dpll_pin *dpll_pin,
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+ void *pin_priv,
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+ const struct dpll_pin *ref_sync_pin,
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+ void *ref_sync_pin_priv,
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+ const enum dpll_pin_state state,
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+ struct netlink_ext_ack *extack)
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+{
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+ struct zl3073x_dpll_pin *sync_pin = ref_sync_pin_priv;
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+ struct zl3073x_dpll_pin *pin = pin_priv;
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+ struct zl3073x_dpll *zldpll = pin->dpll;
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+ struct zl3073x_dev *zldev = zldpll->dev;
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+ u8 mode, ref_id, sync_ref_id;
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+ struct zl3073x_chan chan;
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+ struct zl3073x_ref ref;
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+ int rc;
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+
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+ ref_id = zl3073x_input_pin_ref_get(pin->id);
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+ sync_ref_id = zl3073x_input_pin_ref_get(sync_pin->id);
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+ ref = *zl3073x_ref_state_get(zldev, ref_id);
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+
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+ if (state == DPLL_PIN_STATE_CONNECTED) {
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+ const struct zl3073x_ref *sync_ref;
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+ u32 ref_freq, sync_freq;
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+
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+ sync_ref = zl3073x_ref_state_get(zldev, sync_ref_id);
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+ ref_freq = zl3073x_ref_freq_get(&ref);
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+ sync_freq = zl3073x_ref_freq_get(sync_ref);
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+
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+ /* Sync signal must be 8 kHz or less and clock reference
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+ * must be 1 kHz or more and higher than the sync signal.
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+ */
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+ if (sync_freq > 8000) {
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+ NL_SET_ERR_MSG(extack,
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+ "sync frequency must be 8 kHz or less");
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+ return -EINVAL;
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+ }
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+ if (ref_freq < 1000) {
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+ NL_SET_ERR_MSG(extack,
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+ "clock frequency must be 1 kHz or more");
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+ return -EINVAL;
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+ }
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+ if (ref_freq <= sync_freq) {
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+ NL_SET_ERR_MSG(extack,
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+ "clock frequency must be higher than sync frequency");
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+ return -EINVAL;
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+ }
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+
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+ zl3073x_ref_sync_pair_set(&ref, sync_ref_id);
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+ mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR;
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+ } else {
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+ mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF;
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+ }
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+
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+ zl3073x_ref_sync_mode_set(&ref, mode);
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+
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+ rc = zl3073x_ref_state_set(zldev, ref_id, &ref);
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+ if (rc)
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+ return rc;
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+
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+ /* Exclude sync source from automatic reference selection by setting
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+ * its priority to NONE. On disconnect the priority is left as NONE
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+ * and the user must explicitly make the pin selectable again.
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+ */
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+ if (state == DPLL_PIN_STATE_CONNECTED) {
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+ chan = *zl3073x_chan_state_get(zldev, zldpll->id);
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+ zl3073x_chan_ref_prio_set(&chan, sync_ref_id,
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+ ZL_DPLL_REF_PRIO_NONE);
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+ return zl3073x_chan_state_set(zldev, zldpll->id, &chan);
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+ }
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+
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+ return 0;
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+}
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+
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static int
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zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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@@ -1147,6 +1253,8 @@ static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = {
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.phase_adjust_set = zl3073x_dpll_input_pin_phase_adjust_set,
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.prio_get = zl3073x_dpll_input_pin_prio_get,
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.prio_set = zl3073x_dpll_input_pin_prio_set,
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+ .ref_sync_get = zl3073x_dpll_input_pin_ref_sync_get,
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+ .ref_sync_set = zl3073x_dpll_input_pin_ref_sync_set,
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.state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get,
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.state_on_dpll_set = zl3073x_dpll_input_pin_state_on_dpll_set,
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};
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@@ -1239,8 +1347,11 @@ zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index)
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if (IS_ERR(props))
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return PTR_ERR(props);
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- /* Save package label, esync capability and phase adjust granularity */
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+ /* Save package label, fwnode, esync capability and phase adjust
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+ * granularity.
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+ */
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strscpy(pin->label, props->package_label);
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+ pin->fwnode = fwnode_handle_get(props->fwnode);
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pin->esync_control = props->esync_control;
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pin->phase_gran = props->dpll_props.phase_gran;
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@@ -1285,6 +1396,8 @@ zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index)
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dpll_pin_put(pin->dpll_pin, &pin->tracker);
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pin->dpll_pin = NULL;
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err_pin_get:
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+ fwnode_handle_put(pin->fwnode);
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+ pin->fwnode = NULL;
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zl3073x_pin_props_put(props);
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return rc;
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@@ -1314,6 +1427,9 @@ zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin)
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dpll_pin_put(pin->dpll_pin, &pin->tracker);
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pin->dpll_pin = NULL;
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+
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+ fwnode_handle_put(pin->fwnode);
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+ pin->fwnode = NULL;
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}
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/**
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@@ -1827,6 +1943,88 @@ zl3073x_dpll_free(struct zl3073x_dpll *zldpll)
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kfree(zldpll);
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}
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+/**
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+ * zl3073x_dpll_ref_sync_pair_register - register ref_sync pairs for a pin
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+ * @pin: pointer to zl3073x_dpll_pin structure
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+ *
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+ * Iterates 'ref-sync-sources' phandles in the pin's firmware node and
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+ * registers each declared pairing.
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+ *
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+ * Return: 0 on success, <0 on error
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+ */
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+static int
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+zl3073x_dpll_ref_sync_pair_register(struct zl3073x_dpll_pin *pin)
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+{
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+ struct zl3073x_dev *zldev = pin->dpll->dev;
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+ struct fwnode_handle *fwnode;
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+ struct dpll_pin *sync_pin;
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+ dpll_tracker tracker;
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+ int n, rc;
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+
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+ for (n = 0; ; n++) {
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+ /* Get n'th ref-sync source */
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+ fwnode = fwnode_find_reference(pin->fwnode, "ref-sync-sources",
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+ n);
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+ if (IS_ERR(fwnode)) {
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+ rc = PTR_ERR(fwnode);
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+ break;
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+ }
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+
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+ /* Find associated dpll pin */
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+ sync_pin = fwnode_dpll_pin_find(fwnode, &tracker);
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+ fwnode_handle_put(fwnode);
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+ if (!sync_pin) {
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+ dev_warn(zldev->dev, "%s: ref-sync source %d not found",
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+ pin->label, n);
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+ continue;
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+ }
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+
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+ /* Register new ref-sync pair */
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+ rc = dpll_pin_ref_sync_pair_add(pin->dpll_pin, sync_pin);
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+ dpll_pin_put(sync_pin, &tracker);
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+
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+ /* -EBUSY means pairing already exists from another DPLL's
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+ * registration.
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+ */
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+ if (rc && rc != -EBUSY) {
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+ dev_err(zldev->dev,
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+ "%s: failed to add ref-sync source %d: %pe",
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+ pin->label, n, ERR_PTR(rc));
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+ break;
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+ }
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+ }
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+
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+ return rc != -ENOENT ? rc : 0;
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+}
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+
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+/**
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+ * zl3073x_dpll_ref_sync_pairs_register - register ref_sync pairs for a DPLL
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+ * @zldpll: pointer to zl3073x_dpll structure
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+ *
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+ * Iterates all registered input pins of the given DPLL and establishes
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+ * ref_sync pairings declared by 'ref-sync-sources' phandles in the
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+ * device tree.
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+ *
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+ * Return: 0 on success, <0 on error
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+ */
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+static int
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+zl3073x_dpll_ref_sync_pairs_register(struct zl3073x_dpll *zldpll)
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+{
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+ struct zl3073x_dpll_pin *pin;
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+ int rc;
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+
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+ list_for_each_entry(pin, &zldpll->pins, list) {
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+ if (!zl3073x_dpll_is_input_pin(pin) || !pin->fwnode)
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+ continue;
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+
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+ rc = zl3073x_dpll_ref_sync_pair_register(pin);
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+ if (rc)
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+ return rc;
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+ }
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+
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+ return 0;
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+}
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+
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/**
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* zl3073x_dpll_register - register DPLL device and all its pins
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* @zldpll: pointer to zl3073x_dpll structure
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@@ -1850,6 +2048,13 @@ zl3073x_dpll_register(struct zl3073x_dpll *zldpll)
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return rc;
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}
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+ rc = zl3073x_dpll_ref_sync_pairs_register(zldpll);
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+ if (rc) {
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+ zl3073x_dpll_pins_unregister(zldpll);
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+ zl3073x_dpll_device_unregister(zldpll);
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+ return rc;
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+ }
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+
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return 0;
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}
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--
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2.50.1 (Apple Git-155)
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