Linux v4.15-rc8
This commit is contained in:
Laura Abbott
parent
56578f5c35
commit
825a0e7a9c
@ -1,66 +0,0 @@
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From e4d0e84e490790798691aaa0f2e598637f1867ec Mon Sep 17 00:00:00 2001
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From: Tom Lendacky <thomas.lendacky@amd.com>
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Date: Mon, 8 Jan 2018 16:09:21 -0600
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Subject: [PATCH 1/2] x86/cpu/AMD: Make LFENCE a serializing instruction
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To aid in speculation control, make LFENCE a serializing instruction
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since it has less overhead than MFENCE. This is done by setting bit 1
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of MSR 0xc0011029 (DE_CFG). Some families that support LFENCE do not
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have this MSR. For these families, the LFENCE instruction is already
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serializing.
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Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Reviewed-by: Borislav Petkov <bp@suse.de>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Tim Chen <tim.c.chen@linux.intel.com>
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Cc: Dave Hansen <dave.hansen@intel.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Dan Williams <dan.j.williams@intel.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org>
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Cc: David Woodhouse <dwmw@amazon.co.uk>
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Cc: Paul Turner <pjt@google.com>
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Link: https://lkml.kernel.org/r/20180108220921.12580.71694.stgit@tlendack-t1.amdoffice.net
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---
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arch/x86/include/asm/msr-index.h | 2 ++
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arch/x86/kernel/cpu/amd.c | 10 ++++++++++
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2 files changed, 12 insertions(+)
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diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
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index ab022618a50a..1e7d710fef43 100644
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -352,6 +352,8 @@
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#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
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#define FAM10H_MMIO_CONF_BASE_SHIFT 20
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#define MSR_FAM10H_NODE_ID 0xc001100c
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+#define MSR_F10H_DECFG 0xc0011029
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+#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
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/* K8 MSRs */
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#define MSR_K8_TOP_MEM1 0xc001001a
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diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
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index bcb75dc97d44..5b438d81beb2 100644
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--- a/arch/x86/kernel/cpu/amd.c
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+++ b/arch/x86/kernel/cpu/amd.c
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@@ -829,6 +829,16 @@ static void init_amd(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_K8);
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if (cpu_has(c, X86_FEATURE_XMM2)) {
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+ /*
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+ * A serializing LFENCE has less overhead than MFENCE, so
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+ * use it for execution serialization. On families which
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+ * don't have that MSR, LFENCE is already serializing.
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+ * msr_set_bit() uses the safe accessors, too, even if the MSR
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+ * is not present.
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+ */
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+ msr_set_bit(MSR_F10H_DECFG,
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+ MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
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+
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/* MFENCE stops RDTSC speculation */
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set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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}
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--
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2.14.3
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@ -1,58 +0,0 @@
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From 99c6fa2511d8a683e61468be91b83f85452115fa Mon Sep 17 00:00:00 2001
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From: David Woodhouse <dwmw@amazon.co.uk>
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Date: Sat, 6 Jan 2018 11:49:23 +0000
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Subject: [PATCH 1/2] x86/cpufeatures: Add X86_BUG_SPECTRE_V[12]
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Add the bug bits for spectre v1/2 and force them unconditionally for all
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cpus.
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Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: gnomes@lxorguk.ukuu.org.uk
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Cc: Rik van Riel <riel@redhat.com>
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Cc: Andi Kleen <ak@linux.intel.com>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Jiri Kosina <jikos@kernel.org>
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Cc: Andy Lutomirski <luto@amacapital.net>
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Cc: Dave Hansen <dave.hansen@intel.com>
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Cc: Kees Cook <keescook@google.com>
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Cc: Tim Chen <tim.c.chen@linux.intel.com>
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Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org>
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Cc: Paul Turner <pjt@google.com>
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Cc: stable@vger.kernel.org
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Link: https://lkml.kernel.org/r/1515239374-23361-2-git-send-email-dwmw@amazon.co.uk
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---
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arch/x86/include/asm/cpufeatures.h | 2 ++
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arch/x86/kernel/cpu/common.c | 3 +++
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2 files changed, 5 insertions(+)
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diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
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index 21ac898df2d8..1641c2f96363 100644
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -342,5 +342,7 @@
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#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
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#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */
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#define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */
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+#define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */
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+#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
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#endif /* _ASM_X86_CPUFEATURES_H */
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diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
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index 2d3bd2215e5b..372ba3fb400f 100644
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--- a/arch/x86/kernel/cpu/common.c
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+++ b/arch/x86/kernel/cpu/common.c
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@@ -902,6 +902,9 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
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if (c->x86_vendor != X86_VENDOR_AMD)
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setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
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+ setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
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+ setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
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+
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fpu__init_system(c);
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#ifdef CONFIG_X86_32
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--
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2.14.3
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@ -1,154 +0,0 @@
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From 87590ce6e373d1a5401f6539f0c59ef92dd924a9 Mon Sep 17 00:00:00 2001
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From: Thomas Gleixner <tglx@linutronix.de>
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Date: Sun, 7 Jan 2018 22:48:00 +0100
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Subject: [PATCH 2/2] sysfs/cpu: Add vulnerability folder
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As the meltdown/spectre problem affects several CPU architectures, it makes
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sense to have common way to express whether a system is affected by a
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particular vulnerability or not. If affected the way to express the
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mitigation should be common as well.
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Create /sys/devices/system/cpu/vulnerabilities folder and files for
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meltdown, spectre_v1 and spectre_v2.
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Allow architectures to override the show function.
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: Dave Hansen <dave.hansen@intel.com>
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Cc: Linus Torvalds <torvalds@linuxfoundation.org>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: David Woodhouse <dwmw@amazon.co.uk>
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Link: https://lkml.kernel.org/r/20180107214913.096657732@linutronix.de
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---
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Documentation/ABI/testing/sysfs-devices-system-cpu | 16 ++++++++
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drivers/base/Kconfig | 3 ++
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drivers/base/cpu.c | 48 ++++++++++++++++++++++
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include/linux/cpu.h | 7 ++++
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4 files changed, 74 insertions(+)
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diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
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index f3d5817c4ef0..bd3a88e16d8b 100644
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--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
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+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
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@@ -373,3 +373,19 @@ Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
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Description: information about CPUs heterogeneity.
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cpu_capacity: capacity of cpu#.
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+
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+What: /sys/devices/system/cpu/vulnerabilities
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+ /sys/devices/system/cpu/vulnerabilities/meltdown
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+ /sys/devices/system/cpu/vulnerabilities/spectre_v1
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+ /sys/devices/system/cpu/vulnerabilities/spectre_v2
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+Date: Januar 2018
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+Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
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+Description: Information about CPU vulnerabilities
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+
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+ The files are named after the code names of CPU
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+ vulnerabilities. The output of those files reflects the
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+ state of the CPUs in the system. Possible output values:
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+
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+ "Not affected" CPU is not affected by the vulnerability
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+ "Vulnerable" CPU is affected and no mitigation in effect
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+ "Mitigation: $M" CPU is affetcted and mitigation $M is in effect
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diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
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index 2f6614c9a229..37a71fd9043f 100644
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--- a/drivers/base/Kconfig
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+++ b/drivers/base/Kconfig
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@@ -235,6 +235,9 @@ config GENERIC_CPU_DEVICES
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config GENERIC_CPU_AUTOPROBE
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bool
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+config GENERIC_CPU_VULNERABILITIES
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+ bool
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+
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config SOC_BUS
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bool
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select GLOB
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diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
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index 321cd7b4d817..825964efda1d 100644
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--- a/drivers/base/cpu.c
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+++ b/drivers/base/cpu.c
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@@ -501,10 +501,58 @@ static void __init cpu_dev_register_generic(void)
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#endif
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}
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+#ifdef CONFIG_GENERIC_CPU_VULNERABILITIES
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+
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+ssize_t __weak cpu_show_meltdown(struct device *dev,
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+ struct device_attribute *attr, char *buf)
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+{
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+ return sprintf(buf, "Not affected\n");
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+}
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+
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+ssize_t __weak cpu_show_spectre_v1(struct device *dev,
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+ struct device_attribute *attr, char *buf)
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+{
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+ return sprintf(buf, "Not affected\n");
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+}
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+
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+ssize_t __weak cpu_show_spectre_v2(struct device *dev,
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+ struct device_attribute *attr, char *buf)
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+{
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+ return sprintf(buf, "Not affected\n");
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+}
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+
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+static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL);
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+static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL);
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+static DEVICE_ATTR(spectre_v2, 0444, cpu_show_spectre_v2, NULL);
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+
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+static struct attribute *cpu_root_vulnerabilities_attrs[] = {
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+ &dev_attr_meltdown.attr,
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+ &dev_attr_spectre_v1.attr,
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+ &dev_attr_spectre_v2.attr,
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+ NULL
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+};
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+
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+static const struct attribute_group cpu_root_vulnerabilities_group = {
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+ .name = "vulnerabilities",
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+ .attrs = cpu_root_vulnerabilities_attrs,
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+};
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+
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+static void __init cpu_register_vulnerabilities(void)
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+{
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+ if (sysfs_create_group(&cpu_subsys.dev_root->kobj,
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+ &cpu_root_vulnerabilities_group))
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+ pr_err("Unable to register CPU vulnerabilities\n");
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+}
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+
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+#else
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+static inline void cpu_register_vulnerabilities(void) { }
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+#endif
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+
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void __init cpu_dev_init(void)
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{
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if (subsys_system_register(&cpu_subsys, cpu_root_attr_groups))
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panic("Failed to register CPU subsystem");
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cpu_dev_register_generic();
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+ cpu_register_vulnerabilities();
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}
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diff --git a/include/linux/cpu.h b/include/linux/cpu.h
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index 938ea8ae0ba4..c816e6f2730c 100644
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--- a/include/linux/cpu.h
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+++ b/include/linux/cpu.h
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@@ -47,6 +47,13 @@ extern void cpu_remove_dev_attr(struct device_attribute *attr);
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extern int cpu_add_dev_attr_group(struct attribute_group *attrs);
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extern void cpu_remove_dev_attr_group(struct attribute_group *attrs);
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+extern ssize_t cpu_show_meltdown(struct device *dev,
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+ struct device_attribute *attr, char *buf);
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+extern ssize_t cpu_show_spectre_v1(struct device *dev,
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+ struct device_attribute *attr, char *buf);
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+extern ssize_t cpu_show_spectre_v2(struct device *dev,
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+ struct device_attribute *attr, char *buf);
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+
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extern __printf(4, 5)
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struct device *cpu_device_create(struct device *parent, void *drvdata,
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const struct attribute_group **groups,
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--
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2.14.3
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@ -1,82 +0,0 @@
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From 9c6a73c75864ad9fa49e5fa6513e4c4071c0e29f Mon Sep 17 00:00:00 2001
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From: Tom Lendacky <thomas.lendacky@amd.com>
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Date: Mon, 8 Jan 2018 16:09:32 -0600
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Subject: [PATCH 2/2] x86/cpu/AMD: Use LFENCE_RDTSC in preference to
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MFENCE_RDTSC
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With LFENCE now a serializing instruction, use LFENCE_RDTSC in preference
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to MFENCE_RDTSC. However, since the kernel could be running under a
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hypervisor that does not support writing that MSR, read the MSR back and
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verify that the bit has been set successfully. If the MSR can be read
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and the bit is set, then set the LFENCE_RDTSC feature, otherwise set the
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MFENCE_RDTSC feature.
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Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Reviewed-by: Borislav Petkov <bp@suse.de>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Tim Chen <tim.c.chen@linux.intel.com>
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Cc: Dave Hansen <dave.hansen@intel.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Dan Williams <dan.j.williams@intel.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org>
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Cc: David Woodhouse <dwmw@amazon.co.uk>
|
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Cc: Paul Turner <pjt@google.com>
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Link: https://lkml.kernel.org/r/20180108220932.12580.52458.stgit@tlendack-t1.amdoffice.net
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---
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arch/x86/include/asm/msr-index.h | 1 +
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arch/x86/kernel/cpu/amd.c | 18 ++++++++++++++++--
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2 files changed, 17 insertions(+), 2 deletions(-)
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diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
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index 1e7d710fef43..fa11fb1fa570 100644
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -354,6 +354,7 @@
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#define MSR_FAM10H_NODE_ID 0xc001100c
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#define MSR_F10H_DECFG 0xc0011029
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#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
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+#define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
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/* K8 MSRs */
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#define MSR_K8_TOP_MEM1 0xc001001a
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diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
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index 5b438d81beb2..ea831c858195 100644
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--- a/arch/x86/kernel/cpu/amd.c
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+++ b/arch/x86/kernel/cpu/amd.c
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@@ -829,6 +829,9 @@ static void init_amd(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_K8);
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if (cpu_has(c, X86_FEATURE_XMM2)) {
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+ unsigned long long val;
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+ int ret;
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+
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/*
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* A serializing LFENCE has less overhead than MFENCE, so
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* use it for execution serialization. On families which
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@@ -839,8 +842,19 @@ static void init_amd(struct cpuinfo_x86 *c)
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msr_set_bit(MSR_F10H_DECFG,
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MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
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- /* MFENCE stops RDTSC speculation */
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- set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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+ /*
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+ * Verify that the MSR write was successful (could be running
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+ * under a hypervisor) and only then assume that LFENCE is
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+ * serializing.
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+ */
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+ ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
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+ if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
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+ /* A serializing LFENCE stops RDTSC speculation */
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+ set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
|
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+ } else {
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+ /* MFENCE stops RDTSC speculation */
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+ set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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+ }
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}
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/*
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--
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2.14.3
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@ -1,33 +0,0 @@
|
||||
From e5d5c9682aa02a6b9c0c6bd446d433b924441679 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
|
||||
Date: Tue, 28 Nov 2017 10:02:35 +0100
|
||||
Subject: [PATCH 3/3] x86/PCI: limit the size of the 64bit BAR to 256GB
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
This avoids problems with Xen which hides some memory resources from the
|
||||
OS and potentially also allows memory hotplug while this fixup is
|
||||
enabled.
|
||||
|
||||
Signed-off-by: Christian König <christian.koenig@amd.com>
|
||||
---
|
||||
arch/x86/pci/fixup.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
|
||||
index c817ab85dc82..149adbc7f2a3 100644
|
||||
--- a/arch/x86/pci/fixup.c
|
||||
+++ b/arch/x86/pci/fixup.c
|
||||
@@ -701,7 +701,7 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
|
||||
res->name = "PCI Bus 0000:00";
|
||||
res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |
|
||||
IORESOURCE_MEM_64 | IORESOURCE_WINDOW;
|
||||
- res->start = 0x100000000ull;
|
||||
+ res->start = 0xbd00000000ull;
|
||||
res->end = 0xfd00000000ull - 1;
|
||||
|
||||
/* Just grab the free area behind system memory for this */
|
||||
--
|
||||
2.11.0
|
||||
|
||||
15
kernel.spec
15
kernel.spec
@ -67,9 +67,9 @@ Summary: The Linux kernel
|
||||
# The next upstream release sublevel (base_sublevel+1)
|
||||
%define upstream_sublevel %(echo $((%{base_sublevel} + 1)))
|
||||
# The rc snapshot level
|
||||
%global rcrev 7
|
||||
%global rcrev 8
|
||||
# The git snapshot level
|
||||
%define gitrev 4
|
||||
%define gitrev 0
|
||||
# Set rpm version accordingly
|
||||
%define rpmversion 4.%{upstream_sublevel}.0
|
||||
%endif
|
||||
@ -619,9 +619,6 @@ Patch630: 0001-HID-multitouch-Properly-deal-with-Win8-PTP-reports-w.patch
|
||||
Patch631: 0002-HID-multitouch-Only-look-at-non-touch-fields-in-firs.patch
|
||||
Patch632: 0003-HID-multitouch-Combine-all-left-button-events-in-a-f.patch
|
||||
|
||||
# Reported upstream
|
||||
Patch635: 0003-x86-PCI-limit-the-size-of-the-64bit-BAR-to-256GB.patch
|
||||
|
||||
# Make SATA link powermanagement policy configurable for:
|
||||
# https://fedoraproject.org/wiki/Changes/ImprovedLaptopBatteryLife
|
||||
# Queued upstream for merging into 4.16
|
||||
@ -637,11 +634,6 @@ Patch641: 0001-Bluetooth-btusb-Disable-autosuspend-on-QCA-Rome-devi.patch
|
||||
|
||||
# Speculative Execution patches
|
||||
Patch642: prevent-bounds-check-bypass-via-speculative-execution.patch
|
||||
Patch643: 0001-x86-cpufeatures-Add-X86_BUG_SPECTRE_V-12.patch
|
||||
Patch644: 0002-sysfs-cpu-Add-vulnerability-folder.patch
|
||||
Patch645: 0001-x86-cpu-AMD-Make-LFENCE-a-serializing-instruction.patch
|
||||
Patch646: 0002-x86-cpu-AMD-Use-LFENCE_RDTSC-in-preference-to-MFENCE.patch
|
||||
Patch647: retpoline.patch
|
||||
|
||||
|
||||
# END OF PATCH DEFINITIONS
|
||||
@ -1902,6 +1894,9 @@ fi
|
||||
#
|
||||
#
|
||||
%changelog
|
||||
* Mon Jan 15 2018 Laura Abbott <labbott@redhat.com> - 4.15.0-0.rc8.git0.1
|
||||
- Linux v4.15-rc8
|
||||
|
||||
* Mon Jan 15 2018 Laura Abbott <labbott@redhat.com>
|
||||
- Disable debugging options.
|
||||
|
||||
|
||||
1480
retpoline.patch
1480
retpoline.patch
File diff suppressed because it is too large
Load Diff
3
sources
3
sources
@ -1,4 +1,3 @@
|
||||
SHA512 (linux-4.14.tar.xz) = 77e43a02d766c3d73b7e25c4aafb2e931d6b16e870510c22cef0cdb05c3acb7952b8908ebad12b10ef982c6efbe286364b1544586e715cf38390e483927904d8
|
||||
SHA512 (perf-man-4.14.tar.gz) = 76a9d8adc284cdffd4b3fbb060e7f9a14109267707ce1d03f4c3239cd70d8d164f697da3a0f90a363fbcac42a61d3c378afbcc2a86f112c501b9cb5ce74ef9f8
|
||||
SHA512 (patch-4.15-rc7.xz) = 1c9c74917f5bc5e259d4b918d429d606419f4564ae15f754ef01404234f53d02c8782db0bcce75bf8103510231e723df2fa4a8c8cca8ea4db458b585c0e01570
|
||||
SHA512 (patch-4.15-rc7-git4.xz) = c3d84079ff6b6ea9163a2e6e3d7d6cfef6729f37ecded5eba0b0ee37fe39c4b6ca1e5bfd8e37aab50bd212e5e868384cfc49890738bd4a57ef90888ab7eb8170
|
||||
SHA512 (patch-4.15-rc8.xz) = 1a70ada185b738586ca79cf7497582a3d0198746cebac028fc8e7558d00984e089242e1f3c48cec80eb2baf0ba1b519873a73dd418c9c209dd5568f0c5604634
|
||||
|
||||
Loading…
Reference in New Issue
Block a user