Fix USB on Raspberry Pi (and possibly other dwc2 devices
This commit is contained in:
Peter Robinson
parent
7bea88339b
commit
0878a20964
@ -1,301 +0,0 @@
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From patchwork Mon Oct 9 12:00:51 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [PATCHv4,
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2/2] phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800
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From: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
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X-Patchwork-Id: 9992809
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Message-Id: <1507550451-21324-3-git-send-email-andrzej.p@samsung.com>
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To: linux-samsung-soc@vger.kernel.org, linux-usb@vger.kernel.org,
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linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
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Cc: Mark Rutland <mark.rutland@arm.com>, Felipe Balbi <balbi@kernel.org>,
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Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
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Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
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Russell King <linux@armlinux.org.uk>,
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Krzysztof Kozlowski <krzk@kernel.org>,
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Kishon Vijay Abraham I <kishon@ti.com>,
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Rob Herring <robh+dt@kernel.org>, Kukjin Kim <kgene@kernel.org>,
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Andrzej Pietrasiewicz <andrzej.p@samsung.com>,
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Marek Szyprowski <m.szyprowski@samsung.com>
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Date: Mon, 09 Oct 2017 14:00:51 +0200
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From: Vivek Gautam <gautam.vivek@samsung.com>
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Adding phy calibration sequence for USB 3.0 DRD PHY present on
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Exynos5420/5800 systems.
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This calibration facilitates setting certain PHY parameters viz.
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the Loss-of-Signal (LOS) Detector Threshold Level, as well as
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Tx-Vboost-Level for Super-Speed operations.
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Additionally we also set proper time to wait for RxDetect measurement,
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for desired PHY reference clock, so as to solve issue with enumeration
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of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive
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on the controller.
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We are using CR_port for this purpose to send required data
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to override the LOS values.
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On testing with USB 3.0 devices on USB 3.0 port present on
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SMDK5420, and peach-pit boards should see following message:
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usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
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and without this patch, should see below shown message:
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usb 1-1: new high-speed USB device number 2 using xhci-hcd
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[Also removed unnecessary extra lines in the register macro definitions]
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Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
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[adapted to use phy_calibrate as entry point]
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Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
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---
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drivers/phy/samsung/phy-exynos5-usbdrd.c | 183 +++++++++++++++++++++++++++++++
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drivers/usb/dwc3/core.c | 7 +-
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2 files changed, 188 insertions(+), 2 deletions(-)
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diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
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index 22c68f5..9e83c15 100644
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--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
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+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
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@@ -90,7 +90,17 @@
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#define PHYCLKRST_COMMONONN BIT(0)
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#define EXYNOS5_DRD_PHYREG0 0x14
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+#define PHYREG0_SSC_REF_CLK_SEL BIT(21)
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+#define PHYREG0_SSC_RANGE BIT(20)
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+#define PHYREG0_CR_WRITE BIT(19)
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+#define PHYREG0_CR_READ BIT(18)
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+#define PHYREG0_CR_DATA_IN(_x) ((_x) << 2)
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+#define PHYREG0_CR_CAP_DATA BIT(1)
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+#define PHYREG0_CR_CAP_ADDR BIT(0)
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+
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#define EXYNOS5_DRD_PHYREG1 0x18
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+#define PHYREG1_CR_DATA_OUT(_x) ((_x) << 1)
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+#define PHYREG1_CR_ACK BIT(0)
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#define EXYNOS5_DRD_PHYPARAM0 0x1c
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@@ -119,6 +129,25 @@
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#define EXYNOS5_DRD_PHYRESUME 0x34
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#define EXYNOS5_DRD_LINKPORT 0x44
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+/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
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+#define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN (0x15)
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+#define LOSLEVEL_OVRD_IN_LOS_BIAS_5420 (0x5 << 13)
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+#define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT (0x0 << 13)
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+#define LOSLEVEL_OVRD_IN_EN (0x1 << 10)
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+#define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT (0x9 << 0)
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+
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+#define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN (0x12)
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+#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420 (0x5 << 13)
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+#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT (0x4 << 13)
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+
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+#define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG (0x1010)
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+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M (0x4 << 4)
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+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M (0x8 << 4)
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+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M (0x8 << 4)
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+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M (0x20 << 4)
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+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5 (0x20 << 4)
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+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M (0x40 << 4)
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+
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#define KHZ 1000
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#define MHZ (KHZ * KHZ)
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@@ -527,6 +556,151 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
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return 0;
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}
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+static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd,
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+ u32 val, u32 cmd)
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+{
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+ u32 usec = 100;
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+ unsigned int result;
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+
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+ writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
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+
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+ do {
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+ result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);
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+ if (result & PHYREG1_CR_ACK)
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+ break;
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+
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+ udelay(1);
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+ } while (usec-- > 0);
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+
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+ if (!usec) {
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+ dev_err(phy_drd->dev,
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+ "CRPORT handshake timeout1 (0x%08x)\n", val);
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+ return -ETIME;
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+ }
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+
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+ usec = 100;
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+
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+ writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
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+
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+ do {
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+ result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);
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+ if (!(result & PHYREG1_CR_ACK))
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+ break;
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+
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+ udelay(1);
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+ } while (usec-- > 0);
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+
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+ if (!usec) {
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+ dev_err(phy_drd->dev,
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+ "CRPORT handshake timeout2 (0x%08x)\n", val);
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+ return -ETIME;
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+ }
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+
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+ return 0;
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+}
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+
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+static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd,
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+ u32 addr, u32 data)
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+{
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+ int ret;
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+
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+ /* Write Address */
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+ writel(PHYREG0_CR_DATA_IN(addr),
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+ phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
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+ ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr),
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+ PHYREG0_CR_CAP_ADDR);
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+ if (ret)
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+ return ret;
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+
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+ /* Write Data */
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+ writel(PHYREG0_CR_DATA_IN(data),
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+ phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
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+ ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
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+ PHYREG0_CR_CAP_DATA);
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+ if (ret)
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+ return ret;
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+
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+ ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
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+ PHYREG0_CR_WRITE);
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+
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+ return ret;
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+}
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+
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+/*
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+ * Calibrate few PHY parameters using CR_PORT register to meet
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+ * SuperSpeed requirements on Exynos5420 and Exynos5800 systems,
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+ * which have 28nm USB 3.0 DRD PHY.
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+ */
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+static int exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd)
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+{
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+ unsigned int temp;
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+ int ret = 0;
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+
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+ /*
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+ * Change los_bias to (0x5) for 28nm PHY from a
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+ * default value (0x0); los_level is set as default
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+ * (0x9) as also reflected in los_level[30:26] bits
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+ * of PHYPARAM0 register.
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+ */
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+ temp = LOSLEVEL_OVRD_IN_LOS_BIAS_5420 |
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+ LOSLEVEL_OVRD_IN_EN |
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+ LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT;
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+ ret = crport_ctrl_write(phy_drd,
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+ EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN,
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+ temp);
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+ if (ret) {
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+ dev_err(phy_drd->dev,
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+ "Failed setting Loss-of-Signal level for SuperSpeed\n");
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+ return ret;
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+ }
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+
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+ /*
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+ * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning,
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+ * to raise Tx signal level from its default value of (0x4)
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+ */
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+ temp = TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420;
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+ ret = crport_ctrl_write(phy_drd,
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+ EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN,
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+ temp);
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+ if (ret) {
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+ dev_err(phy_drd->dev,
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+ "Failed setting Tx-Vboost-Level for SuperSpeed\n");
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+ return ret;
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+ }
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+
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+ /*
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+ * Set proper time to wait for RxDetect measurement, for
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+ * desired reference clock of PHY, by tuning the CR_PORT
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+ * register LANE0.TX_DEBUG which is internal to PHY.
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+ * This fixes issue with few USB 3.0 devices, which are
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+ * not detected (not even generate interrupts on the bus
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+ * on insertion) without this change.
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+ * e.g. Samsung SUM-TSB16S 3.0 USB drive.
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+ */
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+ switch (phy_drd->extrefclk) {
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+ case EXYNOS5_FSEL_50MHZ:
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+ temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M;
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+ break;
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+ case EXYNOS5_FSEL_20MHZ:
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+ case EXYNOS5_FSEL_19MHZ2:
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+ temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M;
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+ break;
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+ case EXYNOS5_FSEL_24MHZ:
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+ default:
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+ temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M;
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+ break;
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+ }
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+
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+ ret = crport_ctrl_write(phy_drd,
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+ EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG,
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+ temp);
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+ if (ret)
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+ dev_err(phy_drd->dev,
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+ "Failed setting RxDetect measurement time for SuperSpeed\n");
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+
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+ return ret;
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+}
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+
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static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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@@ -538,11 +712,20 @@ static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
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return phy_drd->phys[args->args[0]].phy;
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}
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+static int exynos5_usbdrd_phy_calibrate(struct phy *phy)
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+{
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+ struct phy_usb_instance *inst = phy_get_drvdata(phy);
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+ struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
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+
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+ return exynos5420_usbdrd_phy_calibrate(phy_drd);
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+}
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+
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static const struct phy_ops exynos5_usbdrd_phy_ops = {
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.init = exynos5_usbdrd_phy_init,
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.exit = exynos5_usbdrd_phy_exit,
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.power_on = exynos5_usbdrd_phy_power_on,
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.power_off = exynos5_usbdrd_phy_power_off,
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+ .calibrate = exynos5_usbdrd_phy_calibrate,
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.owner = THIS_MODULE,
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};
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diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
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index 03474d3..224e0dd 100644
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--- a/drivers/usb/dwc3/core.c
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+++ b/drivers/usb/dwc3/core.c
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@@ -156,9 +156,10 @@ static void __dwc3_set_mode(struct work_struct *work)
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} else {
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if (dwc->usb2_phy)
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otg_set_vbus(dwc->usb2_phy->otg, true);
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- if (dwc->usb2_generic_phy)
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+ if (dwc->usb2_generic_phy) {
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phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
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-
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+ phy_calibrate(dwc->usb2_generic_phy);
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+ }
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}
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break;
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case DWC3_GCTL_PRTCAP_DEVICE:
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@@ -955,6 +956,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
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dev_err(dev, "failed to initialize host\n");
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return ret;
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}
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+ if (dwc->usb2_generic_phy)
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+ phy_calibrate(dwc->usb2_generic_phy);
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break;
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case USB_DR_MODE_OTG:
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INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
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@ -584,9 +584,10 @@ Patch321: bcm283x-dma-mapping-skip-USB-devices-when-configuring-DMA-during-probe
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# https://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git/log/?h=synquacer-netsec
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# https://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git/log/?h=synquacer-netsec
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Patch332: arm64-socionext-96b-enablement.patch
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Patch332: arm64-socionext-96b-enablement.patch
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# This needs a rebase
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# Fix Raspberry Pi and possibly some other dwc2/dwc3 users
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# Patch335: arm-exynos-fix-usb3.patch
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# https://patchwork.kernel.org/patch/10149439/
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Patch399: phy-work-around-phys-references-to-usb-phy-devices.patch
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# 400 - IBM (ppc/s390x) patches
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# 400 - IBM (ppc/s390x) patches
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# 500 - Temp fixes/CVEs etc
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# 500 - Temp fixes/CVEs etc
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@ -1892,6 +1893,9 @@ fi
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#
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#
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#
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#
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%changelog
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%changelog
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* Wed Jan 10 2018 Peter Robinson <pbrobinson@fedoraproject.org>
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||||||
|
- Fix USB on Raspberry Pi (and possibly other dwc2 devices)
|
||||||
|
|
||||||
* Tue Jan 09 2018 Laura Abbott <labbott@redhat.com> - 4.15.0-0.rc7.git1.1
|
* Tue Jan 09 2018 Laura Abbott <labbott@redhat.com> - 4.15.0-0.rc7.git1.1
|
||||||
- Linux v4.15-rc7-79-gef7f8cec80a0
|
- Linux v4.15-rc7-79-gef7f8cec80a0
|
||||||
|
|
||||||
|
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Loading…
Reference in New Issue
Block a user