3659 lines
124 KiB
Diff
3659 lines
124 KiB
Diff
|
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c.h b/drivers/net/ethernet/atheros/atl1c/atl1c.h
|
||
|
index ca70e16..b2bf324 100644
|
||
|
--- a/drivers/net/ethernet/atheros/atl1c/atl1c.h
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||
|
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c.h
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||
|
@@ -74,8 +74,6 @@
|
||
|
|
||
|
#define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)
|
||
|
#define MAX_JUMBO_FRAME_SIZE (6*1024)
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||
|
-#define MAX_TSO_FRAME_SIZE (7*1024)
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||
|
-#define MAX_TX_OFFLOAD_THRESH (9*1024)
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||
|
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||
|
#define AT_MAX_RECEIVE_QUEUE 4
|
||
|
#define AT_DEF_RECEIVE_QUEUE 1
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||
|
@@ -100,7 +98,7 @@
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||
|
#define ATL1C_ASPM_L0s_ENABLE 0x0001
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||
|
#define ATL1C_ASPM_L1_ENABLE 0x0002
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||
|
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||
|
-#define AT_REGS_LEN (75 * sizeof(u32))
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||
|
+#define AT_REGS_LEN (74 * sizeof(u32))
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||
|
#define AT_EEPROM_LEN 512
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||
|
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||
|
#define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
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@@ -297,20 +295,6 @@ enum atl1c_dma_req_block {
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atl1c_dma_req_4096 = 5
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||
|
};
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||
|
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||
|
-enum atl1c_rss_mode {
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|
- atl1c_rss_mode_disable = 0,
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||
|
- atl1c_rss_sig_que = 1,
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||
|
- atl1c_rss_mul_que_sig_int = 2,
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||
|
- atl1c_rss_mul_que_mul_int = 4,
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||
|
-};
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||
|
-
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||
|
-enum atl1c_rss_type {
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|
- atl1c_rss_disable = 0,
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||
|
- atl1c_rss_ipv4 = 1,
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||
|
- atl1c_rss_ipv4_tcp = 2,
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|
- atl1c_rss_ipv6 = 4,
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||
|
- atl1c_rss_ipv6_tcp = 8
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||
|
-};
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||
|
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||
|
enum atl1c_nic_type {
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||
|
athr_l1c = 0,
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||
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@@ -388,7 +372,6 @@ struct atl1c_hw {
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||
|
enum atl1c_dma_order dma_order;
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||
|
enum atl1c_dma_rcb rcb_value;
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||
|
enum atl1c_dma_req_block dmar_block;
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||
|
- enum atl1c_dma_req_block dmaw_block;
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||
|
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||
|
u16 device_id;
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||
|
u16 vendor_id;
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||
|
@@ -399,8 +382,6 @@ struct atl1c_hw {
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||
|
u16 phy_id2;
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||
|
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||
|
u32 intr_mask;
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||
|
- u8 dmaw_dly_cnt;
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||
|
- u8 dmar_dly_cnt;
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||
|
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||
|
u8 preamble_len;
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|
u16 max_frame_size;
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|
@@ -440,10 +421,6 @@ struct atl1c_hw {
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|
#define ATL1C_FPGA_VERSION 0x8000
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|
u16 link_cap_flags;
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|
#define ATL1C_LINK_CAP_1000M 0x0001
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||
|
- u16 cmb_tpd;
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||
|
- u16 cmb_rrd;
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||
|
- u16 cmb_rx_timer; /* 2us resolution */
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|
- u16 cmb_tx_timer;
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||
|
u32 smb_timer;
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||
|
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||
|
u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
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||
|
@@ -451,9 +428,6 @@ struct atl1c_hw {
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||
|
u16 tpd_thresh;
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||
|
u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */
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||
|
u8 rfd_burst;
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||
|
- enum atl1c_rss_type rss_type;
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||
|
- enum atl1c_rss_mode rss_mode;
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||
|
- u8 rss_hash_bits;
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||
|
u32 base_cpu;
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||
|
u32 indirect_tab;
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||
|
u8 mac_addr[ETH_ALEN];
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||
|
@@ -462,12 +436,12 @@ struct atl1c_hw {
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|
bool phy_configured;
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||
|
bool re_autoneg;
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||
|
bool emi_ca;
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||
|
+ bool msi_lnkpatch; /* link patch for specific platforms */
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||
|
};
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||
|
|
||
|
/*
|
||
|
* atl1c_ring_header represents a single, contiguous block of DMA space
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|
- * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
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- * message blocks (cmb, smb) described below
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|
+ * mapped for the three descriptor rings (tpd, rfd, rrd) described below
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||
|
*/
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|
struct atl1c_ring_header {
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void *desc; /* virtual address */
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||
|
@@ -541,16 +515,6 @@ struct atl1c_rrd_ring {
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|
u16 next_to_clean;
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||
|
};
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||
|
|
||
|
-struct atl1c_cmb {
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||
|
- void *cmb;
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||
|
- dma_addr_t dma;
|
||
|
-};
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||
|
-
|
||
|
-struct atl1c_smb {
|
||
|
- void *smb;
|
||
|
- dma_addr_t dma;
|
||
|
-};
|
||
|
-
|
||
|
/* board specific private data structure */
|
||
|
struct atl1c_adapter {
|
||
|
struct net_device *netdev;
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||
|
@@ -586,11 +550,8 @@ struct atl1c_adapter {
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|
/* All Descriptor memory */
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||
|
struct atl1c_ring_header ring_header;
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||
|
struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE];
|
||
|
- struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE];
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|
- struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE];
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|
- struct atl1c_cmb cmb;
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||
|
- struct atl1c_smb smb;
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||
|
- int num_rx_queues;
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||
|
+ struct atl1c_rfd_ring rfd_ring;
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||
|
+ struct atl1c_rrd_ring rrd_ring;
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||
|
u32 bd_number; /* board number;*/
|
||
|
};
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||
|
|
||
|
@@ -618,8 +579,14 @@ struct atl1c_adapter {
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||
|
#define AT_WRITE_REGW(a, reg, value) (\
|
||
|
writew((value), ((a)->hw_addr + reg)))
|
||
|
|
||
|
-#define AT_READ_REGW(a, reg) (\
|
||
|
- readw((a)->hw_addr + reg))
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||
|
+#define AT_READ_REGW(a, reg, pdata) do { \
|
||
|
+ if (unlikely((a)->hibernate)) { \
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||
|
+ readw((a)->hw_addr + reg); \
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||
|
+ *(u16 *)pdata = readw((a)->hw_addr + reg); \
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||
|
+ } else { \
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||
|
+ *(u16 *)pdata = readw((a)->hw_addr + reg); \
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||
|
+ } \
|
||
|
+ } while (0)
|
||
|
|
||
|
#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
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||
|
writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
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||
|
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c b/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c
|
||
|
index 0a9326a..859ea84 100644
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||
|
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c
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||
|
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c
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||
|
@@ -141,8 +141,7 @@ static void atl1c_get_regs(struct net_device *netdev,
|
||
|
|
||
|
memset(p, 0, AT_REGS_LEN);
|
||
|
|
||
|
- regs->version = 0;
|
||
|
- AT_READ_REG(hw, REG_VPD_CAP, p++);
|
||
|
+ regs->version = 1;
|
||
|
AT_READ_REG(hw, REG_PM_CTRL, p++);
|
||
|
AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL, p++);
|
||
|
AT_READ_REG(hw, REG_TWSI_CTRL, p++);
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||
|
@@ -154,7 +153,7 @@ static void atl1c_get_regs(struct net_device *netdev,
|
||
|
AT_READ_REG(hw, REG_LINK_CTRL, p++);
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AT_READ_REG(hw, REG_IDLE_STATUS, p++);
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|
AT_READ_REG(hw, REG_MDIO_CTRL, p++);
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|
- AT_READ_REG(hw, REG_SERDES_LOCK, p++);
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||
|
+ AT_READ_REG(hw, REG_SERDES, p++);
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|
AT_READ_REG(hw, REG_MAC_CTRL, p++);
|
||
|
AT_READ_REG(hw, REG_MAC_IPG_IFG, p++);
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|
AT_READ_REG(hw, REG_MAC_STA_ADDR, p++);
|
||
|
@@ -167,9 +166,9 @@ static void atl1c_get_regs(struct net_device *netdev,
|
||
|
AT_READ_REG(hw, REG_WOL_CTRL, p++);
|
||
|
|
||
|
atl1c_read_phy_reg(hw, MII_BMCR, &phy_data);
|
||
|
- regs_buff[73] = (u32) phy_data;
|
||
|
+ regs_buff[AT_REGS_LEN/sizeof(u32) - 2] = (u32) phy_data;
|
||
|
atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
|
||
|
- regs_buff[74] = (u32) phy_data;
|
||
|
+ regs_buff[AT_REGS_LEN/sizeof(u32) - 1] = (u32) phy_data;
|
||
|
}
|
||
|
|
||
|
static int atl1c_get_eeprom_len(struct net_device *netdev)
|
||
|
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
|
||
|
index bd1667c..ff9c738 100644
|
||
|
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
|
||
|
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
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||
|
@@ -43,7 +43,7 @@ int atl1c_check_eeprom_exist(struct atl1c_hw *hw)
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
-void atl1c_hw_set_mac_addr(struct atl1c_hw *hw)
|
||
|
+void atl1c_hw_set_mac_addr(struct atl1c_hw *hw, u8 *mac_addr)
|
||
|
{
|
||
|
u32 value;
|
||
|
/*
|
||
|
@@ -51,35 +51,48 @@ void atl1c_hw_set_mac_addr(struct atl1c_hw *hw)
|
||
|
* 0: 6AF600DC 1: 000B
|
||
|
* low dword
|
||
|
*/
|
||
|
- value = (((u32)hw->mac_addr[2]) << 24) |
|
||
|
- (((u32)hw->mac_addr[3]) << 16) |
|
||
|
- (((u32)hw->mac_addr[4]) << 8) |
|
||
|
- (((u32)hw->mac_addr[5])) ;
|
||
|
+ value = mac_addr[2] << 24 |
|
||
|
+ mac_addr[3] << 16 |
|
||
|
+ mac_addr[4] << 8 |
|
||
|
+ mac_addr[5];
|
||
|
AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
|
||
|
/* hight dword */
|
||
|
- value = (((u32)hw->mac_addr[0]) << 8) |
|
||
|
- (((u32)hw->mac_addr[1])) ;
|
||
|
+ value = mac_addr[0] << 8 |
|
||
|
+ mac_addr[1];
|
||
|
AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
|
||
|
}
|
||
|
|
||
|
+/* read mac address from hardware register */
|
||
|
+static bool atl1c_read_current_addr(struct atl1c_hw *hw, u8 *eth_addr)
|
||
|
+{
|
||
|
+ u32 addr[2];
|
||
|
+
|
||
|
+ AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
|
||
|
+ AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
|
||
|
+
|
||
|
+ *(u32 *) ð_addr[2] = htonl(addr[0]);
|
||
|
+ *(u16 *) ð_addr[0] = htons((u16)addr[1]);
|
||
|
+
|
||
|
+ return is_valid_ether_addr(eth_addr);
|
||
|
+}
|
||
|
+
|
||
|
/*
|
||
|
* atl1c_get_permanent_address
|
||
|
* return 0 if get valid mac address,
|
||
|
*/
|
||
|
static int atl1c_get_permanent_address(struct atl1c_hw *hw)
|
||
|
{
|
||
|
- u32 addr[2];
|
||
|
u32 i;
|
||
|
u32 otp_ctrl_data;
|
||
|
u32 twsi_ctrl_data;
|
||
|
- u32 ltssm_ctrl_data;
|
||
|
- u32 wol_data;
|
||
|
- u8 eth_addr[ETH_ALEN];
|
||
|
u16 phy_data;
|
||
|
bool raise_vol = false;
|
||
|
|
||
|
+ /* MAC-address from BIOS is the 1st priority */
|
||
|
+ if (atl1c_read_current_addr(hw, hw->perm_mac_addr))
|
||
|
+ return 0;
|
||
|
+
|
||
|
/* init */
|
||
|
- addr[0] = addr[1] = 0;
|
||
|
AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
|
||
|
if (atl1c_check_eeprom_exist(hw)) {
|
||
|
if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
|
||
|
@@ -91,33 +104,17 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
|
||
|
msleep(1);
|
||
|
}
|
||
|
}
|
||
|
-
|
||
|
- if (hw->nic_type == athr_l2c_b ||
|
||
|
- hw->nic_type == athr_l2c_b2 ||
|
||
|
- hw->nic_type == athr_l1d) {
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
|
||
|
- if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
|
||
|
- goto out;
|
||
|
- phy_data &= 0xFF7F;
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
|
||
|
-
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
|
||
|
- if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
|
||
|
- goto out;
|
||
|
- phy_data |= 0x8;
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
|
||
|
+ /* raise voltage temporally for l2cb */
|
||
|
+ if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) {
|
||
|
+ atl1c_read_phy_dbg(hw, MIIDBG_ANACTRL, &phy_data);
|
||
|
+ phy_data &= ~ANACTRL_HB_EN;
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, phy_data);
|
||
|
+ atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data);
|
||
|
+ phy_data |= VOLT_CTRL_SWLOWEST;
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data);
|
||
|
udelay(20);
|
||
|
raise_vol = true;
|
||
|
}
|
||
|
- /* close open bit of ReadOnly*/
|
||
|
- AT_READ_REG(hw, REG_LTSSM_ID_CTRL, <ssm_ctrl_data);
|
||
|
- ltssm_ctrl_data &= ~LTSSM_ID_EN_WRO;
|
||
|
- AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, ltssm_ctrl_data);
|
||
|
-
|
||
|
- /* clear any WOL settings */
|
||
|
- AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
|
||
|
- AT_READ_REG(hw, REG_WOL_CTRL, &wol_data);
|
||
|
-
|
||
|
|
||
|
AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
|
||
|
twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
|
||
|
@@ -138,37 +135,18 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
|
||
|
msleep(1);
|
||
|
}
|
||
|
if (raise_vol) {
|
||
|
- if (hw->nic_type == athr_l2c_b ||
|
||
|
- hw->nic_type == athr_l2c_b2 ||
|
||
|
- hw->nic_type == athr_l1d ||
|
||
|
- hw->nic_type == athr_l1d_2) {
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
|
||
|
- if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
|
||
|
- goto out;
|
||
|
- phy_data |= 0x80;
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
|
||
|
-
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
|
||
|
- if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
|
||
|
- goto out;
|
||
|
- phy_data &= 0xFFF7;
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
|
||
|
- udelay(20);
|
||
|
- }
|
||
|
+ atl1c_read_phy_dbg(hw, MIIDBG_ANACTRL, &phy_data);
|
||
|
+ phy_data |= ANACTRL_HB_EN;
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, phy_data);
|
||
|
+ atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data);
|
||
|
+ phy_data &= ~VOLT_CTRL_SWLOWEST;
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data);
|
||
|
+ udelay(20);
|
||
|
}
|
||
|
|
||
|
- /* maybe MAC-address is from BIOS */
|
||
|
- AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
|
||
|
- AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
|
||
|
- *(u32 *) ð_addr[2] = swab32(addr[0]);
|
||
|
- *(u16 *) ð_addr[0] = swab16(*(u16 *)&addr[1]);
|
||
|
-
|
||
|
- if (is_valid_ether_addr(eth_addr)) {
|
||
|
- memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
|
||
|
+ if (atl1c_read_current_addr(hw, hw->perm_mac_addr))
|
||
|
return 0;
|
||
|
- }
|
||
|
|
||
|
-out:
|
||
|
return -1;
|
||
|
}
|
||
|
|
||
|
@@ -278,33 +256,158 @@ void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value)
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}
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/*
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- * Reads the value from a PHY register
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- * hw - Struct containing variables accessed by shared code
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- * reg_addr - address of the PHY register to read
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+ * wait mdio module be idle
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+ * return true: idle
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+ * false: still busy
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*/
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-int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
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+bool atl1c_wait_mdio_idle(struct atl1c_hw *hw)
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{
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u32 val;
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int i;
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- val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
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- MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
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- MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
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+ for (i = 0; i < MDIO_MAX_AC_TO; i++) {
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+ AT_READ_REG(hw, REG_MDIO_CTRL, &val);
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+ if (!(val & (MDIO_CTRL_BUSY | MDIO_CTRL_START)))
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+ break;
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+ udelay(10);
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+ }
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+
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+ return i != MDIO_MAX_AC_TO;
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+}
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+
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+void atl1c_stop_phy_polling(struct atl1c_hw *hw)
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+{
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+ if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
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+ return;
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+
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+ AT_WRITE_REG(hw, REG_MDIO_CTRL, 0);
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+ atl1c_wait_mdio_idle(hw);
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+}
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+
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+void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel)
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+{
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+ u32 val;
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+
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+ if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
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+ return;
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+ val = MDIO_CTRL_SPRES_PRMBL |
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+ FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
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+ FIELDX(MDIO_CTRL_REG, 1) |
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+ MDIO_CTRL_START |
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+ MDIO_CTRL_OP_READ;
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+ AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
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+ atl1c_wait_mdio_idle(hw);
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+ val |= MDIO_CTRL_AP_EN;
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+ val &= ~MDIO_CTRL_START;
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AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
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+ udelay(30);
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+}
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- for (i = 0; i < MDIO_WAIT_TIMES; i++) {
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- udelay(2);
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- AT_READ_REG(hw, REG_MDIO_CTRL, &val);
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- if (!(val & (MDIO_START | MDIO_BUSY)))
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- break;
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+
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+/*
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+ * atl1c_read_phy_core
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+ * core funtion to read register in PHY via MDIO control regsiter.
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+ * ext: extension register (see IEEE 802.3)
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+ * dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0)
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+ * reg: reg to read
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+ */
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+int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
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+ u16 reg, u16 *phy_data)
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+{
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+ u32 val;
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+ u16 clk_sel = MDIO_CTRL_CLK_25_4;
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+
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+ atl1c_stop_phy_polling(hw);
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+
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+ *phy_data = 0;
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+
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+ /* only l2c_b2 & l1d_2 could use slow clock */
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+ if ((hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) &&
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+ hw->hibernate)
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+ clk_sel = MDIO_CTRL_CLK_25_128;
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+ if (ext) {
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+ val = FIELDX(MDIO_EXTN_DEVAD, dev) | FIELDX(MDIO_EXTN_REG, reg);
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+ AT_WRITE_REG(hw, REG_MDIO_EXTN, val);
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+ val = MDIO_CTRL_SPRES_PRMBL |
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+ FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
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+ MDIO_CTRL_START |
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+ MDIO_CTRL_MODE_EXT |
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+ MDIO_CTRL_OP_READ;
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+ } else {
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+ val = MDIO_CTRL_SPRES_PRMBL |
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+ FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
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+ FIELDX(MDIO_CTRL_REG, reg) |
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+ MDIO_CTRL_START |
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+ MDIO_CTRL_OP_READ;
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}
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- if (!(val & (MDIO_START | MDIO_BUSY))) {
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- *phy_data = (u16)val;
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- return 0;
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+ AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
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+
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+ if (!atl1c_wait_mdio_idle(hw))
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+ return -1;
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+
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+ AT_READ_REG(hw, REG_MDIO_CTRL, &val);
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+ *phy_data = (u16)FIELD_GETX(val, MDIO_CTRL_DATA);
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+
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+ atl1c_start_phy_polling(hw, clk_sel);
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+
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+ return 0;
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+}
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+
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+/*
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+ * atl1c_write_phy_core
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+ * core funtion to write to register in PHY via MDIO control regsiter.
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+ * ext: extension register (see IEEE 802.3)
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+ * dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0)
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+ * reg: reg to write
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+ */
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+int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
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+ u16 reg, u16 phy_data)
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+{
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+ u32 val;
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+ u16 clk_sel = MDIO_CTRL_CLK_25_4;
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+
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+ atl1c_stop_phy_polling(hw);
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+
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+
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+ /* only l2c_b2 & l1d_2 could use slow clock */
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+ if ((hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) &&
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+ hw->hibernate)
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+ clk_sel = MDIO_CTRL_CLK_25_128;
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+
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+ if (ext) {
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+ val = FIELDX(MDIO_EXTN_DEVAD, dev) | FIELDX(MDIO_EXTN_REG, reg);
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+ AT_WRITE_REG(hw, REG_MDIO_EXTN, val);
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+ val = MDIO_CTRL_SPRES_PRMBL |
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+ FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
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+ FIELDX(MDIO_CTRL_DATA, phy_data) |
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+ MDIO_CTRL_START |
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+ MDIO_CTRL_MODE_EXT;
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+ } else {
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+ val = MDIO_CTRL_SPRES_PRMBL |
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+ FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
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+ FIELDX(MDIO_CTRL_DATA, phy_data) |
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+ FIELDX(MDIO_CTRL_REG, reg) |
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+ MDIO_CTRL_START;
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}
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+ AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
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- return -1;
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+ if (!atl1c_wait_mdio_idle(hw))
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+ return -1;
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+
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+ atl1c_start_phy_polling(hw, clk_sel);
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+
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+ return 0;
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+}
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+
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+/*
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+ * Reads the value from a PHY register
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+ * hw - Struct containing variables accessed by shared code
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+ * reg_addr - address of the PHY register to read
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+ */
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+int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
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+{
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+ return atl1c_read_phy_core(hw, false, 0, reg_addr, phy_data);
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}
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/*
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@@ -315,27 +418,47 @@ int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
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*/
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int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data)
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{
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- int i;
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- u32 val;
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+ return atl1c_write_phy_core(hw, false, 0, reg_addr, phy_data);
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+}
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- val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
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- (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
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- MDIO_SUP_PREAMBLE | MDIO_START |
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- MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
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+/* read from PHY extension register */
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+int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
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+ u16 reg_addr, u16 *phy_data)
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+{
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+ return atl1c_read_phy_core(hw, true, dev_addr, reg_addr, phy_data);
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+}
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- AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
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+/* write to PHY extension register */
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+int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
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+ u16 reg_addr, u16 phy_data)
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+{
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+ return atl1c_write_phy_core(hw, true, dev_addr, reg_addr, phy_data);
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+}
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- for (i = 0; i < MDIO_WAIT_TIMES; i++) {
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- udelay(2);
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- AT_READ_REG(hw, REG_MDIO_CTRL, &val);
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- if (!(val & (MDIO_START | MDIO_BUSY)))
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- break;
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- }
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+int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
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+{
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+ int err;
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- if (!(val & (MDIO_START | MDIO_BUSY)))
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- return 0;
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+ err = atl1c_write_phy_reg(hw, MII_DBG_ADDR, reg_addr);
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+ if (unlikely(err))
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+ return err;
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+ else
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+ err = atl1c_read_phy_reg(hw, MII_DBG_DATA, phy_data);
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- return -1;
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+ return err;
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+}
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+
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+int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data)
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+{
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+ int err;
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+
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+ err = atl1c_write_phy_reg(hw, MII_DBG_ADDR, reg_addr);
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+ if (unlikely(err))
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+ return err;
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+ else
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+ err = atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
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+
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+ return err;
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}
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/*
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@@ -380,119 +503,100 @@ static int atl1c_phy_setup_adv(struct atl1c_hw *hw)
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void atl1c_phy_disable(struct atl1c_hw *hw)
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{
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- AT_WRITE_REGW(hw, REG_GPHY_CTRL,
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- GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
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+ atl1c_power_saving(hw, 0);
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}
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-static void atl1c_phy_magic_data(struct atl1c_hw *hw)
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-{
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- u16 data;
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-
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- data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
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- ((1 & ANA_INTERVAL_SEL_TIMER_MASK) <<
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- ANA_INTERVAL_SEL_TIMER_SHIFT);
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-
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- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_18);
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- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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-
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- data = (2 & ANA_SERDES_CDR_BW_MASK) | ANA_MS_PAD_DBG |
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- ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
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- ANA_SERDES_EN_LCKDT;
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-
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- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_5);
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- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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-
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- data = (44 & ANA_LONG_CABLE_TH_100_MASK) |
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- ((33 & ANA_SHORT_CABLE_TH_100_MASK) <<
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- ANA_SHORT_CABLE_TH_100_SHIFT) | ANA_BP_BAD_LINK_ACCUM |
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- ANA_BP_SMALL_BW;
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-
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- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_54);
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- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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-
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- data = (11 & ANA_IECHO_ADJ_MASK) | ((11 & ANA_IECHO_ADJ_MASK) <<
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- ANA_IECHO_ADJ_2_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
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- ANA_IECHO_ADJ_1_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
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- ANA_IECHO_ADJ_0_SHIFT);
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-
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- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_4);
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- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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-
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- data = ANA_RESTART_CAL | ((7 & ANA_MANUL_SWICH_ON_MASK) <<
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- ANA_MANUL_SWICH_ON_SHIFT) | ANA_MAN_ENABLE |
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- ANA_SEL_HSP | ANA_EN_HB | ANA_OEN_125M;
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-
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- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_0);
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- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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-
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- if (hw->ctrl_flags & ATL1C_HIB_DISABLE) {
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- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_41);
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- if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
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- return;
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- data &= ~ANA_TOP_PS_EN;
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- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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-
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- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_11);
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- if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
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- return;
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- data &= ~ANA_PS_HIB_EN;
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- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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- }
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-}
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int atl1c_phy_reset(struct atl1c_hw *hw)
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{
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struct atl1c_adapter *adapter = hw->adapter;
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struct pci_dev *pdev = adapter->pdev;
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u16 phy_data;
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- u32 phy_ctrl_data = GPHY_CTRL_DEFAULT;
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- u32 mii_ier_data = IER_LINK_UP | IER_LINK_DOWN;
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+ u32 phy_ctrl_data, lpi_ctrl;
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int err;
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- if (hw->ctrl_flags & ATL1C_HIB_DISABLE)
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- phy_ctrl_data &= ~GPHY_CTRL_HIB_EN;
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-
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+ /* reset PHY core */
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+ AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl_data);
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+ phy_ctrl_data &= ~(GPHY_CTRL_EXT_RESET | GPHY_CTRL_PHY_IDDQ |
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+ GPHY_CTRL_GATE_25M_EN | GPHY_CTRL_PWDOWN_HW | GPHY_CTRL_CLS);
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+ phy_ctrl_data |= GPHY_CTRL_SEL_ANA_RST;
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+ if (!(hw->ctrl_flags & ATL1C_HIB_DISABLE))
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+ phy_ctrl_data |= (GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE);
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+ else
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+ phy_ctrl_data &= ~(GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE);
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AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
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AT_WRITE_FLUSH(hw);
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- msleep(40);
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- phy_ctrl_data |= GPHY_CTRL_EXT_RESET;
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- AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
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+ udelay(10);
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+ AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data | GPHY_CTRL_EXT_RESET);
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AT_WRITE_FLUSH(hw);
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- msleep(10);
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+ udelay(10 * GPHY_CTRL_EXT_RST_TO); /* delay 800us */
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+ /* switch clock */
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if (hw->nic_type == athr_l2c_b) {
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- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x0A);
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- atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
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- atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xDFFF);
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+ atl1c_read_phy_dbg(hw, MIIDBG_CFGLPSPD, &phy_data);
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+ atl1c_write_phy_dbg(hw, MIIDBG_CFGLPSPD,
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+ phy_data & ~CFGLPSPD_RSTCNT_CLK125SW);
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}
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- if (hw->nic_type == athr_l2c_b ||
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- hw->nic_type == athr_l2c_b2 ||
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- hw->nic_type == athr_l1d ||
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||
|
- hw->nic_type == athr_l1d_2) {
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
|
||
|
- atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xFFF7);
|
||
|
- msleep(20);
|
||
|
+ /* tx-half amplitude issue fix */
|
||
|
+ if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) {
|
||
|
+ atl1c_read_phy_dbg(hw, MIIDBG_CABLE1TH_DET, &phy_data);
|
||
|
+ phy_data |= CABLE1TH_DET_EN;
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_CABLE1TH_DET, phy_data);
|
||
|
}
|
||
|
- if (hw->nic_type == athr_l1d) {
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x29);
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_DATA, 0x929D);
|
||
|
+
|
||
|
+ /* clear bit3 of dbgport 3B to lower voltage */
|
||
|
+ if (!(hw->ctrl_flags & ATL1C_HIB_DISABLE)) {
|
||
|
+ if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) {
|
||
|
+ atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data);
|
||
|
+ phy_data &= ~VOLT_CTRL_SWLOWEST;
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data);
|
||
|
+ }
|
||
|
+ /* power saving config */
|
||
|
+ phy_data =
|
||
|
+ hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2 ?
|
||
|
+ L1D_LEGCYPS_DEF : L1C_LEGCYPS_DEF;
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_LEGCYPS, phy_data);
|
||
|
+ /* hib */
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL,
|
||
|
+ SYSMODCTRL_IECHOADJ_DEF);
|
||
|
+ } else {
|
||
|
+ /* disable pws */
|
||
|
+ atl1c_read_phy_dbg(hw, MIIDBG_LEGCYPS, &phy_data);
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_LEGCYPS,
|
||
|
+ phy_data & ~LEGCYPS_EN);
|
||
|
+ /* disable hibernate */
|
||
|
+ atl1c_read_phy_dbg(hw, MIIDBG_HIBNEG, &phy_data);
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_HIBNEG,
|
||
|
+ phy_data & HIBNEG_PSHIB_EN);
|
||
|
}
|
||
|
- if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c_b2
|
||
|
- || hw->nic_type == athr_l2c) {
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x29);
|
||
|
- atl1c_write_phy_reg(hw, MII_DBG_DATA, 0xB6DD);
|
||
|
+ /* disable AZ(EEE) by default */
|
||
|
+ if (hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2 ||
|
||
|
+ hw->nic_type == athr_l2c_b2) {
|
||
|
+ AT_READ_REG(hw, REG_LPI_CTRL, &lpi_ctrl);
|
||
|
+ AT_WRITE_REG(hw, REG_LPI_CTRL, lpi_ctrl & ~LPI_CTRL_EN);
|
||
|
+ atl1c_write_phy_ext(hw, MIIEXT_ANEG, MIIEXT_LOCAL_EEEADV, 0);
|
||
|
+ atl1c_write_phy_ext(hw, MIIEXT_PCS, MIIEXT_CLDCTRL3,
|
||
|
+ L2CB_CLDCTRL3);
|
||
|
}
|
||
|
- err = atl1c_write_phy_reg(hw, MII_IER, mii_ier_data);
|
||
|
+
|
||
|
+ /* other debug port to set */
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, ANACTRL_DEF);
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_SRDSYSMOD, SRDSYSMOD_DEF);
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_TST10BTCFG, TST10BTCFG_DEF);
|
||
|
+ /* UNH-IOL test issue, set bit7 */
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_TST100BTCFG,
|
||
|
+ TST100BTCFG_DEF | TST100BTCFG_LITCH_EN);
|
||
|
+
|
||
|
+ /* set phy interrupt mask */
|
||
|
+ phy_data = IER_LINK_UP | IER_LINK_DOWN;
|
||
|
+ err = atl1c_write_phy_reg(hw, MII_IER, phy_data);
|
||
|
if (err) {
|
||
|
if (netif_msg_hw(adapter))
|
||
|
dev_err(&pdev->dev,
|
||
|
"Error enable PHY linkChange Interrupt\n");
|
||
|
return err;
|
||
|
}
|
||
|
- if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
|
||
|
- atl1c_phy_magic_data(hw);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
@@ -589,7 +693,8 @@ int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex)
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
-int atl1c_phy_power_saving(struct atl1c_hw *hw)
|
||
|
+/* select one link mode to get lower power consumption */
|
||
|
+int atl1c_phy_to_ps_link(struct atl1c_hw *hw)
|
||
|
{
|
||
|
struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
|
||
|
struct pci_dev *pdev = adapter->pdev;
|
||
|
@@ -660,3 +765,101 @@ int atl1c_restart_autoneg(struct atl1c_hw *hw)
|
||
|
|
||
|
return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
|
||
|
}
|
||
|
+
|
||
|
+int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc)
|
||
|
+{
|
||
|
+ struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
|
||
|
+ struct pci_dev *pdev = adapter->pdev;
|
||
|
+ u32 master_ctrl, mac_ctrl, phy_ctrl;
|
||
|
+ u32 wol_ctrl, speed;
|
||
|
+ u16 phy_data;
|
||
|
+
|
||
|
+ wol_ctrl = 0;
|
||
|
+ speed = adapter->link_speed == SPEED_1000 ?
|
||
|
+ MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100;
|
||
|
+
|
||
|
+ AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl);
|
||
|
+ AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl);
|
||
|
+ AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl);
|
||
|
+
|
||
|
+ master_ctrl &= ~MASTER_CTRL_CLK_SEL_DIS;
|
||
|
+ mac_ctrl = FIELD_SETX(mac_ctrl, MAC_CTRL_SPEED, speed);
|
||
|
+ mac_ctrl &= ~(MAC_CTRL_DUPLX | MAC_CTRL_RX_EN | MAC_CTRL_TX_EN);
|
||
|
+ if (adapter->link_duplex == FULL_DUPLEX)
|
||
|
+ mac_ctrl |= MAC_CTRL_DUPLX;
|
||
|
+ phy_ctrl &= ~(GPHY_CTRL_EXT_RESET | GPHY_CTRL_CLS);
|
||
|
+ phy_ctrl |= GPHY_CTRL_SEL_ANA_RST | GPHY_CTRL_HIB_PULSE |
|
||
|
+ GPHY_CTRL_HIB_EN;
|
||
|
+ if (!wufc) { /* without WoL */
|
||
|
+ master_ctrl |= MASTER_CTRL_CLK_SEL_DIS;
|
||
|
+ phy_ctrl |= GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PWDOWN_HW;
|
||
|
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl);
|
||
|
+ AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl);
|
||
|
+ AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl);
|
||
|
+ AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
|
||
|
+ hw->phy_configured = false; /* re-init PHY when resume */
|
||
|
+ return 0;
|
||
|
+ }
|
||
|
+ phy_ctrl |= GPHY_CTRL_EXT_RESET;
|
||
|
+ if (wufc & AT_WUFC_MAG) {
|
||
|
+ mac_ctrl |= MAC_CTRL_RX_EN | MAC_CTRL_BC_EN;
|
||
|
+ wol_ctrl |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
|
||
|
+ if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V11)
|
||
|
+ wol_ctrl |= WOL_PATTERN_EN | WOL_PATTERN_PME_EN;
|
||
|
+ }
|
||
|
+ if (wufc & AT_WUFC_LNKC) {
|
||
|
+ wol_ctrl |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
|
||
|
+ if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
|
||
|
+ dev_dbg(&pdev->dev, "%s: write phy MII_IER faild.\n",
|
||
|
+ atl1c_driver_name);
|
||
|
+ }
|
||
|
+ }
|
||
|
+ /* clear PHY interrupt */
|
||
|
+ atl1c_read_phy_reg(hw, MII_ISR, &phy_data);
|
||
|
+
|
||
|
+ dev_dbg(&pdev->dev, "%s: suspend MAC=%x,MASTER=%x,PHY=0x%x,WOL=%x\n",
|
||
|
+ atl1c_driver_name, mac_ctrl, master_ctrl, phy_ctrl, wol_ctrl);
|
||
|
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl);
|
||
|
+ AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl);
|
||
|
+ AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl);
|
||
|
+ AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+
|
||
|
+/* configure phy after Link change Event */
|
||
|
+void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed)
|
||
|
+{
|
||
|
+ u16 phy_val;
|
||
|
+ bool adj_thresh = false;
|
||
|
+
|
||
|
+ if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ||
|
||
|
+ hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2)
|
||
|
+ adj_thresh = true;
|
||
|
+
|
||
|
+ if (link_speed != SPEED_0) { /* link up */
|
||
|
+ /* az with brcm, half-amp */
|
||
|
+ if (hw->nic_type == athr_l1d_2) {
|
||
|
+ atl1c_read_phy_ext(hw, MIIEXT_PCS, MIIEXT_CLDCTRL6,
|
||
|
+ &phy_val);
|
||
|
+ phy_val = FIELD_GETX(phy_val, CLDCTRL6_CAB_LEN);
|
||
|
+ phy_val = phy_val > CLDCTRL6_CAB_LEN_SHORT ?
|
||
|
+ AZ_ANADECT_LONG : AZ_ANADECT_DEF;
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_AZ_ANADECT, phy_val);
|
||
|
+ }
|
||
|
+ /* threshold adjust */
|
||
|
+ if (adj_thresh && link_speed == SPEED_100 && hw->msi_lnkpatch) {
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_MSE16DB, L1D_MSE16DB_UP);
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL,
|
||
|
+ L1D_SYSMODCTRL_IECHOADJ_DEF);
|
||
|
+ }
|
||
|
+ } else { /* link down */
|
||
|
+ if (adj_thresh && hw->msi_lnkpatch) {
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL,
|
||
|
+ SYSMODCTRL_IECHOADJ_DEF);
|
||
|
+ atl1c_write_phy_dbg(hw, MIIDBG_MSE16DB,
|
||
|
+ L1D_MSE16DB_DOWN);
|
||
|
+ }
|
||
|
+ }
|
||
|
+}
|
||
|
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
|
||
|
index 655fc6c..17d935b 100644
|
||
|
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
|
||
|
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
|
||
|
@@ -25,12 +25,18 @@
|
||
|
#include <linux/types.h>
|
||
|
#include <linux/mii.h>
|
||
|
|
||
|
+#define FIELD_GETX(_x, _name) ((_x) >> (_name##_SHIFT) & (_name##_MASK))
|
||
|
+#define FIELD_SETX(_x, _name, _v) \
|
||
|
+(((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\
|
||
|
+(((_v) & (_name##_MASK)) << (_name##_SHIFT)))
|
||
|
+#define FIELDX(_name, _v) (((_v) & (_name##_MASK)) << (_name##_SHIFT))
|
||
|
+
|
||
|
struct atl1c_adapter;
|
||
|
struct atl1c_hw;
|
||
|
|
||
|
/* function prototype */
|
||
|
void atl1c_phy_disable(struct atl1c_hw *hw);
|
||
|
-void atl1c_hw_set_mac_addr(struct atl1c_hw *hw);
|
||
|
+void atl1c_hw_set_mac_addr(struct atl1c_hw *hw, u8 *mac_addr);
|
||
|
int atl1c_phy_reset(struct atl1c_hw *hw);
|
||
|
int atl1c_read_mac_addr(struct atl1c_hw *hw);
|
||
|
int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex);
|
||
|
@@ -42,47 +48,45 @@ bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value);
|
||
|
int atl1c_phy_init(struct atl1c_hw *hw);
|
||
|
int atl1c_check_eeprom_exist(struct atl1c_hw *hw);
|
||
|
int atl1c_restart_autoneg(struct atl1c_hw *hw);
|
||
|
-int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
+int atl1c_phy_to_ps_link(struct atl1c_hw *hw);
|
||
|
+int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc);
|
||
|
+bool atl1c_wait_mdio_idle(struct atl1c_hw *hw);
|
||
|
+void atl1c_stop_phy_polling(struct atl1c_hw *hw);
|
||
|
+void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel);
|
||
|
+int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
|
||
|
+ u16 reg, u16 *phy_data);
|
||
|
+int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
|
||
|
+ u16 reg, u16 phy_data);
|
||
|
+int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
|
||
|
+ u16 reg_addr, u16 *phy_data);
|
||
|
+int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
|
||
|
+ u16 reg_addr, u16 phy_data);
|
||
|
+int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
|
||
|
+int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data);
|
||
|
+void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
|
||
|
+
|
||
|
+/* hw-ids */
|
||
|
+#define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
|
||
|
+#define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
|
||
|
+#define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
|
||
|
+#define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
|
||
|
+#define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
|
||
|
+#define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
|
||
|
+#define L2CB_V10 0xc0
|
||
|
+#define L2CB_V11 0xc1
|
||
|
+
|
||
|
/* register definition */
|
||
|
#define REG_DEVICE_CAP 0x5C
|
||
|
#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
|
||
|
#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
|
||
|
|
||
|
-#define REG_DEVICE_CTRL 0x60
|
||
|
-#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
|
||
|
-#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
|
||
|
-#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
|
||
|
-#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
|
||
|
+#define DEVICE_CTRL_MAXRRS_MIN 2
|
||
|
|
||
|
#define REG_LINK_CTRL 0x68
|
||
|
#define LINK_CTRL_L0S_EN 0x01
|
||
|
#define LINK_CTRL_L1_EN 0x02
|
||
|
#define LINK_CTRL_EXT_SYNC 0x80
|
||
|
|
||
|
-#define REG_VPD_CAP 0x6C
|
||
|
-#define VPD_CAP_ID_MASK 0xff
|
||
|
-#define VPD_CAP_ID_SHIFT 0
|
||
|
-#define VPD_CAP_NEXT_PTR_MASK 0xFF
|
||
|
-#define VPD_CAP_NEXT_PTR_SHIFT 8
|
||
|
-#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
|
||
|
-#define VPD_CAP_VPD_ADDR_SHIFT 16
|
||
|
-#define VPD_CAP_VPD_FLAG 0x80000000
|
||
|
-
|
||
|
-#define REG_VPD_DATA 0x70
|
||
|
-
|
||
|
-#define REG_PCIE_UC_SEVERITY 0x10C
|
||
|
-#define PCIE_UC_SERVRITY_TRN 0x00000001
|
||
|
-#define PCIE_UC_SERVRITY_DLP 0x00000010
|
||
|
-#define PCIE_UC_SERVRITY_PSN_TLP 0x00001000
|
||
|
-#define PCIE_UC_SERVRITY_FCP 0x00002000
|
||
|
-#define PCIE_UC_SERVRITY_CPL_TO 0x00004000
|
||
|
-#define PCIE_UC_SERVRITY_CA 0x00008000
|
||
|
-#define PCIE_UC_SERVRITY_UC 0x00010000
|
||
|
-#define PCIE_UC_SERVRITY_ROV 0x00020000
|
||
|
-#define PCIE_UC_SERVRITY_MLFP 0x00040000
|
||
|
-#define PCIE_UC_SERVRITY_ECRC 0x00080000
|
||
|
-#define PCIE_UC_SERVRITY_UR 0x00100000
|
||
|
-
|
||
|
#define REG_DEV_SERIALNUM_CTRL 0x200
|
||
|
#define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
|
||
|
#define REG_DEV_MAC_SEL_SHIFT 0
|
||
|
@@ -90,25 +94,17 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
#define REG_DEV_SERIAL_NUM_EN_SHIFT 1
|
||
|
|
||
|
#define REG_TWSI_CTRL 0x218
|
||
|
+#define TWSI_CTLR_FREQ_MASK 0x3UL
|
||
|
+#define TWSI_CTRL_FREQ_SHIFT 24
|
||
|
+#define TWSI_CTRL_FREQ_100K 0
|
||
|
+#define TWSI_CTRL_FREQ_200K 1
|
||
|
+#define TWSI_CTRL_FREQ_300K 2
|
||
|
+#define TWSI_CTRL_FREQ_400K 3
|
||
|
+#define TWSI_CTRL_LD_EXIST BIT(23)
|
||
|
+#define TWSI_CTRL_HW_LDSTAT BIT(12) /* 0:finish,1:in progress */
|
||
|
+#define TWSI_CTRL_SW_LDSTART BIT(11)
|
||
|
#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
|
||
|
#define TWSI_CTRL_LD_OFFSET_SHIFT 0
|
||
|
-#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
|
||
|
-#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
|
||
|
-#define TWSI_CTRL_SW_LDSTART 0x800
|
||
|
-#define TWSI_CTRL_HW_LDSTART 0x1000
|
||
|
-#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
|
||
|
-#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
|
||
|
-#define TWSI_CTRL_LD_EXIST 0x400000
|
||
|
-#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
|
||
|
-#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
|
||
|
-#define TWSI_CTRL_FREQ_SEL_100K 0
|
||
|
-#define TWSI_CTRL_FREQ_SEL_200K 1
|
||
|
-#define TWSI_CTRL_FREQ_SEL_300K 2
|
||
|
-#define TWSI_CTRL_FREQ_SEL_400K 3
|
||
|
-#define TWSI_CTRL_SMB_SLV_ADDR
|
||
|
-#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
|
||
|
-#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
|
||
|
-
|
||
|
|
||
|
#define REG_PCIE_DEV_MISC_CTRL 0x21C
|
||
|
#define PCIE_DEV_MISC_EXT_PIPE 0x2
|
||
|
@@ -118,16 +114,23 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
#define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10
|
||
|
|
||
|
#define REG_PCIE_PHYMISC 0x1000
|
||
|
-#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
|
||
|
+#define PCIE_PHYMISC_FORCE_RCV_DET BIT(2)
|
||
|
+#define PCIE_PHYMISC_NFTS_MASK 0xFFUL
|
||
|
+#define PCIE_PHYMISC_NFTS_SHIFT 16
|
||
|
|
||
|
#define REG_PCIE_PHYMISC2 0x1004
|
||
|
-#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x3
|
||
|
-#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
|
||
|
-#define PCIE_PHYMISC2_SERDES_TH_MASK 0x3
|
||
|
-#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
|
||
|
+#define PCIE_PHYMISC2_L0S_TH_MASK 0x3UL
|
||
|
+#define PCIE_PHYMISC2_L0S_TH_SHIFT 18
|
||
|
+#define L2CB1_PCIE_PHYMISC2_L0S_TH 3
|
||
|
+#define PCIE_PHYMISC2_CDR_BW_MASK 0x3UL
|
||
|
+#define PCIE_PHYMISC2_CDR_BW_SHIFT 16
|
||
|
+#define L2CB1_PCIE_PHYMISC2_CDR_BW 3
|
||
|
|
||
|
#define REG_TWSI_DEBUG 0x1108
|
||
|
-#define TWSI_DEBUG_DEV_EXIST 0x20000000
|
||
|
+#define TWSI_DEBUG_DEV_EXIST BIT(29)
|
||
|
+
|
||
|
+#define REG_DMA_DBG 0x1114
|
||
|
+#define DMA_DBG_VENDOR_MSG BIT(0)
|
||
|
|
||
|
#define REG_EEPROM_CTRL 0x12C0
|
||
|
#define EEPROM_CTRL_DATA_HI_MASK 0xFFFF
|
||
|
@@ -140,56 +143,81 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
#define REG_EEPROM_DATA_LO 0x12C4
|
||
|
|
||
|
#define REG_OTP_CTRL 0x12F0
|
||
|
-#define OTP_CTRL_CLK_EN 0x0002
|
||
|
+#define OTP_CTRL_CLK_EN BIT(1)
|
||
|
|
||
|
#define REG_PM_CTRL 0x12F8
|
||
|
-#define PM_CTRL_SDES_EN 0x00000001
|
||
|
-#define PM_CTRL_RBER_EN 0x00000002
|
||
|
-#define PM_CTRL_CLK_REQ_EN 0x00000004
|
||
|
-#define PM_CTRL_ASPM_L1_EN 0x00000008
|
||
|
-#define PM_CTRL_SERDES_L1_EN 0x00000010
|
||
|
-#define PM_CTRL_SERDES_PLL_L1_EN 0x00000020
|
||
|
-#define PM_CTRL_SERDES_PD_EX_L1 0x00000040
|
||
|
-#define PM_CTRL_SERDES_BUDS_RX_L1_EN 0x00000080
|
||
|
-#define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xF
|
||
|
-#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8
|
||
|
-#define PM_CTRL_ASPM_L0S_EN 0x00001000
|
||
|
-#define PM_CTRL_CLK_SWH_L1 0x00002000
|
||
|
-#define PM_CTRL_CLK_PWM_VER1_1 0x00004000
|
||
|
-#define PM_CTRL_RCVR_WT_TIMER 0x00008000
|
||
|
-#define PM_CTRL_L1_ENTRY_TIMER_MASK 0xF
|
||
|
-#define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16
|
||
|
-#define PM_CTRL_PM_REQ_TIMER_MASK 0xF
|
||
|
-#define PM_CTRL_PM_REQ_TIMER_SHIFT 20
|
||
|
-#define PM_CTRL_LCKDET_TIMER_MASK 0xF
|
||
|
+#define PM_CTRL_HOTRST BIT(31)
|
||
|
+#define PM_CTRL_MAC_ASPM_CHK BIT(30) /* L0s/L1 dis by MAC based on
|
||
|
+ * thrghput(setting in 15A0) */
|
||
|
+#define PM_CTRL_SA_DLY_EN BIT(29)
|
||
|
+#define PM_CTRL_L0S_BUFSRX_EN BIT(28)
|
||
|
+#define PM_CTRL_LCKDET_TIMER_MASK 0xFUL
|
||
|
#define PM_CTRL_LCKDET_TIMER_SHIFT 24
|
||
|
-#define PM_CTRL_EN_BUFS_RX_L0S 0x10000000
|
||
|
-#define PM_CTRL_SA_DLY_EN 0x20000000
|
||
|
-#define PM_CTRL_MAC_ASPM_CHK 0x40000000
|
||
|
-#define PM_CTRL_HOTRST 0x80000000
|
||
|
+#define PM_CTRL_LCKDET_TIMER_DEF 0xC
|
||
|
+#define PM_CTRL_PM_REQ_TIMER_MASK 0xFUL
|
||
|
+#define PM_CTRL_PM_REQ_TIMER_SHIFT 20 /* pm_request_l1 time > @
|
||
|
+ * ->L0s not L1 */
|
||
|
+#define PM_CTRL_PM_REQ_TO_DEF 0xF
|
||
|
+#define PMCTRL_TXL1_AFTER_L0S BIT(19) /* l1dv2.0+ */
|
||
|
+#define L1D_PMCTRL_L1_ENTRY_TM_MASK 7UL /* l1dv2.0+, 3bits */
|
||
|
+#define L1D_PMCTRL_L1_ENTRY_TM_SHIFT 16
|
||
|
+#define L1D_PMCTRL_L1_ENTRY_TM_DIS 0
|
||
|
+#define L1D_PMCTRL_L1_ENTRY_TM_2US 1
|
||
|
+#define L1D_PMCTRL_L1_ENTRY_TM_4US 2
|
||
|
+#define L1D_PMCTRL_L1_ENTRY_TM_8US 3
|
||
|
+#define L1D_PMCTRL_L1_ENTRY_TM_16US 4
|
||
|
+#define L1D_PMCTRL_L1_ENTRY_TM_24US 5
|
||
|
+#define L1D_PMCTRL_L1_ENTRY_TM_32US 6
|
||
|
+#define L1D_PMCTRL_L1_ENTRY_TM_63US 7
|
||
|
+#define PM_CTRL_L1_ENTRY_TIMER_MASK 0xFUL /* l1C 4bits */
|
||
|
+#define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16
|
||
|
+#define L2CB1_PM_CTRL_L1_ENTRY_TM 7
|
||
|
+#define L1C_PM_CTRL_L1_ENTRY_TM 0xF
|
||
|
+#define PM_CTRL_RCVR_WT_TIMER BIT(15) /* 1:1us, 0:2ms */
|
||
|
+#define PM_CTRL_CLK_PWM_VER1_1 BIT(14) /* 0:1.0a,1:1.1 */
|
||
|
+#define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */
|
||
|
+#define PM_CTRL_ASPM_L0S_EN BIT(12)
|
||
|
+#define PM_CTRL_RXL1_AFTER_L0S BIT(11) /* l1dv2.0+ */
|
||
|
+#define L1D_PMCTRL_L0S_TIMER_MASK 7UL /* l1d2.0+, 3bits*/
|
||
|
+#define L1D_PMCTRL_L0S_TIMER_SHIFT 8
|
||
|
+#define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xFUL /* l1c, 4bits */
|
||
|
+#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8
|
||
|
+#define PM_CTRL_SERDES_BUFS_RX_L1_EN BIT(7)
|
||
|
+#define PM_CTRL_SERDES_PD_EX_L1 BIT(6) /* power down serdes rx */
|
||
|
+#define PM_CTRL_SERDES_PLL_L1_EN BIT(5)
|
||
|
+#define PM_CTRL_SERDES_L1_EN BIT(4)
|
||
|
+#define PM_CTRL_ASPM_L1_EN BIT(3)
|
||
|
+#define PM_CTRL_CLK_REQ_EN BIT(2)
|
||
|
+#define PM_CTRL_RBER_EN BIT(1)
|
||
|
+#define PM_CTRL_SPRSDWER_EN BIT(0)
|
||
|
|
||
|
#define REG_LTSSM_ID_CTRL 0x12FC
|
||
|
#define LTSSM_ID_EN_WRO 0x1000
|
||
|
+
|
||
|
+
|
||
|
/* Selene Master Control Register */
|
||
|
#define REG_MASTER_CTRL 0x1400
|
||
|
-#define MASTER_CTRL_SOFT_RST 0x1
|
||
|
-#define MASTER_CTRL_TEST_MODE_MASK 0x3
|
||
|
-#define MASTER_CTRL_TEST_MODE_SHIFT 2
|
||
|
-#define MASTER_CTRL_BERT_START 0x10
|
||
|
-#define MASTER_CTRL_OOB_DIS_OFF 0x40
|
||
|
-#define MASTER_CTRL_SA_TIMER_EN 0x80
|
||
|
-#define MASTER_CTRL_MTIMER_EN 0x100
|
||
|
-#define MASTER_CTRL_MANUAL_INT 0x200
|
||
|
-#define MASTER_CTRL_TX_ITIMER_EN 0x400
|
||
|
-#define MASTER_CTRL_RX_ITIMER_EN 0x800
|
||
|
-#define MASTER_CTRL_CLK_SEL_DIS 0x1000
|
||
|
-#define MASTER_CTRL_CLK_SWH_MODE 0x2000
|
||
|
-#define MASTER_CTRL_INT_RDCLR 0x4000
|
||
|
-#define MASTER_CTRL_REV_NUM_SHIFT 16
|
||
|
-#define MASTER_CTRL_REV_NUM_MASK 0xff
|
||
|
-#define MASTER_CTRL_DEV_ID_SHIFT 24
|
||
|
-#define MASTER_CTRL_DEV_ID_MASK 0x7f
|
||
|
-#define MASTER_CTRL_OTP_SEL 0x80000000
|
||
|
+#define MASTER_CTRL_OTP_SEL BIT(31)
|
||
|
+#define MASTER_DEV_NUM_MASK 0x7FUL
|
||
|
+#define MASTER_DEV_NUM_SHIFT 24
|
||
|
+#define MASTER_REV_NUM_MASK 0xFFUL
|
||
|
+#define MASTER_REV_NUM_SHIFT 16
|
||
|
+#define MASTER_CTRL_INT_RDCLR BIT(14)
|
||
|
+#define MASTER_CTRL_CLK_SEL_DIS BIT(12) /* 1:alwys sel pclk from
|
||
|
+ * serdes, not sw to 25M */
|
||
|
+#define MASTER_CTRL_RX_ITIMER_EN BIT(11) /* IRQ MODURATION FOR RX */
|
||
|
+#define MASTER_CTRL_TX_ITIMER_EN BIT(10) /* MODURATION FOR TX/RX */
|
||
|
+#define MASTER_CTRL_MANU_INT BIT(9) /* SOFT MANUAL INT */
|
||
|
+#define MASTER_CTRL_MANUTIMER_EN BIT(8)
|
||
|
+#define MASTER_CTRL_SA_TIMER_EN BIT(7) /* SYS ALIVE TIMER EN */
|
||
|
+#define MASTER_CTRL_OOB_DIS BIT(6) /* OUT OF BOX DIS */
|
||
|
+#define MASTER_CTRL_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */
|
||
|
+#define MASTER_CTRL_BERT_START BIT(4)
|
||
|
+#define MASTER_PCIE_TSTMOD_MASK 3UL
|
||
|
+#define MASTER_PCIE_TSTMOD_SHIFT 2
|
||
|
+#define MASTER_PCIE_RST BIT(1)
|
||
|
+#define MASTER_CTRL_SOFT_RST BIT(0) /* RST MAC & DMA */
|
||
|
+#define DMA_MAC_RST_TO 50
|
||
|
|
||
|
/* Timer Initial Value Register */
|
||
|
#define REG_MANUAL_TIMER_INIT 0x1404
|
||
|
@@ -201,87 +229,85 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
#define IRQ_MODRT_RX_TIMER_SHIFT 16
|
||
|
|
||
|
#define REG_GPHY_CTRL 0x140C
|
||
|
-#define GPHY_CTRL_EXT_RESET 0x1
|
||
|
-#define GPHY_CTRL_RTL_MODE 0x2
|
||
|
-#define GPHY_CTRL_LED_MODE 0x4
|
||
|
-#define GPHY_CTRL_ANEG_NOW 0x8
|
||
|
-#define GPHY_CTRL_REV_ANEG 0x10
|
||
|
-#define GPHY_CTRL_GATE_25M_EN 0x20
|
||
|
-#define GPHY_CTRL_LPW_EXIT 0x40
|
||
|
-#define GPHY_CTRL_PHY_IDDQ 0x80
|
||
|
-#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
|
||
|
-#define GPHY_CTRL_GIGA_DIS 0x200
|
||
|
-#define GPHY_CTRL_HIB_EN 0x400
|
||
|
-#define GPHY_CTRL_HIB_PULSE 0x800
|
||
|
-#define GPHY_CTRL_SEL_ANA_RST 0x1000
|
||
|
-#define GPHY_CTRL_PHY_PLL_ON 0x2000
|
||
|
-#define GPHY_CTRL_PWDOWN_HW 0x4000
|
||
|
-#define GPHY_CTRL_PHY_PLL_BYPASS 0x8000
|
||
|
-
|
||
|
-#define GPHY_CTRL_DEFAULT ( \
|
||
|
- GPHY_CTRL_SEL_ANA_RST |\
|
||
|
- GPHY_CTRL_HIB_PULSE |\
|
||
|
- GPHY_CTRL_HIB_EN)
|
||
|
-
|
||
|
-#define GPHY_CTRL_PW_WOL_DIS ( \
|
||
|
- GPHY_CTRL_SEL_ANA_RST |\
|
||
|
- GPHY_CTRL_HIB_PULSE |\
|
||
|
- GPHY_CTRL_HIB_EN |\
|
||
|
- GPHY_CTRL_PWDOWN_HW |\
|
||
|
- GPHY_CTRL_PHY_IDDQ)
|
||
|
-
|
||
|
-#define GPHY_CTRL_POWER_SAVING ( \
|
||
|
- GPHY_CTRL_SEL_ANA_RST |\
|
||
|
- GPHY_CTRL_HIB_EN |\
|
||
|
- GPHY_CTRL_HIB_PULSE |\
|
||
|
- GPHY_CTRL_PWDOWN_HW |\
|
||
|
- GPHY_CTRL_PHY_IDDQ)
|
||
|
+#define GPHY_CTRL_ADDR_MASK 0x1FUL
|
||
|
+#define GPHY_CTRL_ADDR_SHIFT 19
|
||
|
+#define GPHY_CTRL_BP_VLTGSW BIT(18)
|
||
|
+#define GPHY_CTRL_100AB_EN BIT(17)
|
||
|
+#define GPHY_CTRL_10AB_EN BIT(16)
|
||
|
+#define GPHY_CTRL_PHY_PLL_BYPASS BIT(15)
|
||
|
+#define GPHY_CTRL_PWDOWN_HW BIT(14) /* affect MAC&PHY, to low pw */
|
||
|
+#define GPHY_CTRL_PHY_PLL_ON BIT(13) /* 1:pll always on, 0:can sw */
|
||
|
+#define GPHY_CTRL_SEL_ANA_RST BIT(12)
|
||
|
+#define GPHY_CTRL_HIB_PULSE BIT(11)
|
||
|
+#define GPHY_CTRL_HIB_EN BIT(10)
|
||
|
+#define GPHY_CTRL_GIGA_DIS BIT(9)
|
||
|
+#define GPHY_CTRL_PHY_IDDQ_DIS BIT(8) /* pw on RST */
|
||
|
+#define GPHY_CTRL_PHY_IDDQ BIT(7) /* bit8 affect bit7 while rb */
|
||
|
+#define GPHY_CTRL_LPW_EXIT BIT(6)
|
||
|
+#define GPHY_CTRL_GATE_25M_EN BIT(5)
|
||
|
+#define GPHY_CTRL_REV_ANEG BIT(4)
|
||
|
+#define GPHY_CTRL_ANEG_NOW BIT(3)
|
||
|
+#define GPHY_CTRL_LED_MODE BIT(2)
|
||
|
+#define GPHY_CTRL_RTL_MODE BIT(1)
|
||
|
+#define GPHY_CTRL_EXT_RESET BIT(0) /* 1:out of DSP RST status */
|
||
|
+#define GPHY_CTRL_EXT_RST_TO 80 /* 800us atmost */
|
||
|
+#define GPHY_CTRL_CLS (\
|
||
|
+ GPHY_CTRL_LED_MODE |\
|
||
|
+ GPHY_CTRL_100AB_EN |\
|
||
|
+ GPHY_CTRL_PHY_PLL_ON)
|
||
|
+
|
||
|
/* Block IDLE Status Register */
|
||
|
-#define REG_IDLE_STATUS 0x1410
|
||
|
-#define IDLE_STATUS_MASK 0x00FF
|
||
|
-#define IDLE_STATUS_RXMAC_NO_IDLE 0x1
|
||
|
-#define IDLE_STATUS_TXMAC_NO_IDLE 0x2
|
||
|
-#define IDLE_STATUS_RXQ_NO_IDLE 0x4
|
||
|
-#define IDLE_STATUS_TXQ_NO_IDLE 0x8
|
||
|
-#define IDLE_STATUS_DMAR_NO_IDLE 0x10
|
||
|
-#define IDLE_STATUS_DMAW_NO_IDLE 0x20
|
||
|
-#define IDLE_STATUS_SMB_NO_IDLE 0x40
|
||
|
-#define IDLE_STATUS_CMB_NO_IDLE 0x80
|
||
|
+#define REG_IDLE_STATUS 0x1410
|
||
|
+#define IDLE_STATUS_SFORCE_MASK 0xFUL
|
||
|
+#define IDLE_STATUS_SFORCE_SHIFT 14
|
||
|
+#define IDLE_STATUS_CALIB_DONE BIT(13)
|
||
|
+#define IDLE_STATUS_CALIB_RES_MASK 0x1FUL
|
||
|
+#define IDLE_STATUS_CALIB_RES_SHIFT 8
|
||
|
+#define IDLE_STATUS_CALIBERR_MASK 0xFUL
|
||
|
+#define IDLE_STATUS_CALIBERR_SHIFT 4
|
||
|
+#define IDLE_STATUS_TXQ_BUSY BIT(3)
|
||
|
+#define IDLE_STATUS_RXQ_BUSY BIT(2)
|
||
|
+#define IDLE_STATUS_TXMAC_BUSY BIT(1)
|
||
|
+#define IDLE_STATUS_RXMAC_BUSY BIT(0)
|
||
|
+#define IDLE_STATUS_MASK (\
|
||
|
+ IDLE_STATUS_TXQ_BUSY |\
|
||
|
+ IDLE_STATUS_RXQ_BUSY |\
|
||
|
+ IDLE_STATUS_TXMAC_BUSY |\
|
||
|
+ IDLE_STATUS_RXMAC_BUSY)
|
||
|
|
||
|
/* MDIO Control Register */
|
||
|
#define REG_MDIO_CTRL 0x1414
|
||
|
-#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit
|
||
|
- * control data to write to PHY
|
||
|
- * MII management register */
|
||
|
-#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit
|
||
|
- * status data that was read
|
||
|
- * from the PHY MII management register */
|
||
|
-#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
|
||
|
-#define MDIO_REG_ADDR_SHIFT 16
|
||
|
-#define MDIO_RW 0x200000 /* 1: read, 0: write */
|
||
|
-#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
|
||
|
-#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO
|
||
|
- * master. And this bit is self
|
||
|
- * cleared after one cycle */
|
||
|
-#define MDIO_CLK_SEL_SHIFT 24
|
||
|
-#define MDIO_CLK_25_4 0
|
||
|
-#define MDIO_CLK_25_6 2
|
||
|
-#define MDIO_CLK_25_8 3
|
||
|
-#define MDIO_CLK_25_10 4
|
||
|
-#define MDIO_CLK_25_14 5
|
||
|
-#define MDIO_CLK_25_20 6
|
||
|
-#define MDIO_CLK_25_28 7
|
||
|
-#define MDIO_BUSY 0x8000000
|
||
|
-#define MDIO_AP_EN 0x10000000
|
||
|
-#define MDIO_WAIT_TIMES 10
|
||
|
-
|
||
|
-/* MII PHY Status Register */
|
||
|
-#define REG_PHY_STATUS 0x1418
|
||
|
-#define PHY_GENERAL_STATUS_MASK 0xFFFF
|
||
|
-#define PHY_STATUS_RECV_ENABLE 0x0001
|
||
|
-#define PHY_OE_PWSP_STATUS_MASK 0x07FF
|
||
|
-#define PHY_OE_PWSP_STATUS_SHIFT 16
|
||
|
-#define PHY_STATUS_LPW_STATE 0x80000000
|
||
|
+#define MDIO_CTRL_MODE_EXT BIT(30)
|
||
|
+#define MDIO_CTRL_POST_READ BIT(29)
|
||
|
+#define MDIO_CTRL_AP_EN BIT(28)
|
||
|
+#define MDIO_CTRL_BUSY BIT(27)
|
||
|
+#define MDIO_CTRL_CLK_SEL_MASK 0x7UL
|
||
|
+#define MDIO_CTRL_CLK_SEL_SHIFT 24
|
||
|
+#define MDIO_CTRL_CLK_25_4 0 /* 25MHz divide 4 */
|
||
|
+#define MDIO_CTRL_CLK_25_6 2
|
||
|
+#define MDIO_CTRL_CLK_25_8 3
|
||
|
+#define MDIO_CTRL_CLK_25_10 4
|
||
|
+#define MDIO_CTRL_CLK_25_32 5
|
||
|
+#define MDIO_CTRL_CLK_25_64 6
|
||
|
+#define MDIO_CTRL_CLK_25_128 7
|
||
|
+#define MDIO_CTRL_START BIT(23)
|
||
|
+#define MDIO_CTRL_SPRES_PRMBL BIT(22)
|
||
|
+#define MDIO_CTRL_OP_READ BIT(21) /* 1:read, 0:write */
|
||
|
+#define MDIO_CTRL_REG_MASK 0x1FUL
|
||
|
+#define MDIO_CTRL_REG_SHIFT 16
|
||
|
+#define MDIO_CTRL_DATA_MASK 0xFFFFUL
|
||
|
+#define MDIO_CTRL_DATA_SHIFT 0
|
||
|
+#define MDIO_MAX_AC_TO 120 /* 1.2ms timeout for slow clk */
|
||
|
+
|
||
|
+/* for extension reg access */
|
||
|
+#define REG_MDIO_EXTN 0x1448
|
||
|
+#define MDIO_EXTN_PORTAD_MASK 0x1FUL
|
||
|
+#define MDIO_EXTN_PORTAD_SHIFT 21
|
||
|
+#define MDIO_EXTN_DEVAD_MASK 0x1FUL
|
||
|
+#define MDIO_EXTN_DEVAD_SHIFT 16
|
||
|
+#define MDIO_EXTN_REG_MASK 0xFFFFUL
|
||
|
+#define MDIO_EXTN_REG_SHIFT 0
|
||
|
+
|
||
|
/* BIST Control and Status Register0 (for the Packet Memory) */
|
||
|
#define REG_BIST0_CTRL 0x141c
|
||
|
#define BIST0_NOW 0x1
|
||
|
@@ -299,50 +325,81 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
#define BIST1_FUSE_FLAG 0x4
|
||
|
|
||
|
/* SerDes Lock Detect Control and Status Register */
|
||
|
-#define REG_SERDES_LOCK 0x1424
|
||
|
-#define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal
|
||
|
- * comes from Analog SerDes */
|
||
|
-#define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */
|
||
|
-#define SERDES_LOCK_STS_SELFB_PLL_SHIFT 0xE
|
||
|
-#define SERDES_LOCK_STS_SELFB_PLL_MASK 0x3
|
||
|
-#define SERDES_OVCLK_18_25 0x0
|
||
|
-#define SERDES_OVCLK_12_18 0x1
|
||
|
-#define SERDES_OVCLK_0_4 0x2
|
||
|
-#define SERDES_OVCLK_4_12 0x3
|
||
|
-#define SERDES_MAC_CLK_SLOWDOWN 0x20000
|
||
|
-#define SERDES_PYH_CLK_SLOWDOWN 0x40000
|
||
|
+#define REG_SERDES 0x1424
|
||
|
+#define SERDES_PHY_CLK_SLOWDOWN BIT(18)
|
||
|
+#define SERDES_MAC_CLK_SLOWDOWN BIT(17)
|
||
|
+#define SERDES_SELFB_PLL_MASK 0x3UL
|
||
|
+#define SERDES_SELFB_PLL_SHIFT 14
|
||
|
+#define SERDES_PHYCLK_SEL_GTX BIT(13) /* 1:gtx_clk, 0:25M */
|
||
|
+#define SERDES_PCIECLK_SEL_SRDS BIT(12) /* 1:serdes,0:25M */
|
||
|
+#define SERDES_BUFS_RX_EN BIT(11)
|
||
|
+#define SERDES_PD_RX BIT(10)
|
||
|
+#define SERDES_PLL_EN BIT(9)
|
||
|
+#define SERDES_EN BIT(8)
|
||
|
+#define SERDES_SELFB_PLL_SEL_CSR BIT(6) /* 0:state-machine,1:csr */
|
||
|
+#define SERDES_SELFB_PLL_CSR_MASK 0x3UL
|
||
|
+#define SERDES_SELFB_PLL_CSR_SHIFT 4
|
||
|
+#define SERDES_SELFB_PLL_CSR_4 3 /* 4-12% OV-CLK */
|
||
|
+#define SERDES_SELFB_PLL_CSR_0 2 /* 0-4% OV-CLK */
|
||
|
+#define SERDES_SELFB_PLL_CSR_12 1 /* 12-18% OV-CLK */
|
||
|
+#define SERDES_SELFB_PLL_CSR_18 0 /* 18-25% OV-CLK */
|
||
|
+#define SERDES_VCO_SLOW BIT(3)
|
||
|
+#define SERDES_VCO_FAST BIT(2)
|
||
|
+#define SERDES_LOCK_DETECT_EN BIT(1)
|
||
|
+#define SERDES_LOCK_DETECT BIT(0)
|
||
|
+
|
||
|
+#define REG_LPI_DECISN_TIMER 0x143C
|
||
|
+#define L2CB_LPI_DESISN_TIMER 0x7D00
|
||
|
+
|
||
|
+#define REG_LPI_CTRL 0x1440
|
||
|
+#define LPI_CTRL_CHK_DA BIT(31)
|
||
|
+#define LPI_CTRL_ENH_TO_MASK 0x1FFFUL
|
||
|
+#define LPI_CTRL_ENH_TO_SHIFT 12
|
||
|
+#define LPI_CTRL_ENH_TH_MASK 0x1FUL
|
||
|
+#define LPI_CTRL_ENH_TH_SHIFT 6
|
||
|
+#define LPI_CTRL_ENH_EN BIT(5)
|
||
|
+#define LPI_CTRL_CHK_RX BIT(4)
|
||
|
+#define LPI_CTRL_CHK_STATE BIT(3)
|
||
|
+#define LPI_CTRL_GMII BIT(2)
|
||
|
+#define LPI_CTRL_TO_PHY BIT(1)
|
||
|
+#define LPI_CTRL_EN BIT(0)
|
||
|
+
|
||
|
+#define REG_LPI_WAIT 0x1444
|
||
|
+#define LPI_WAIT_TIMER_MASK 0xFFFFUL
|
||
|
+#define LPI_WAIT_TIMER_SHIFT 0
|
||
|
|
||
|
/* MAC Control Register */
|
||
|
#define REG_MAC_CTRL 0x1480
|
||
|
-#define MAC_CTRL_TX_EN 0x1
|
||
|
-#define MAC_CTRL_RX_EN 0x2
|
||
|
-#define MAC_CTRL_TX_FLOW 0x4
|
||
|
-#define MAC_CTRL_RX_FLOW 0x8
|
||
|
-#define MAC_CTRL_LOOPBACK 0x10
|
||
|
-#define MAC_CTRL_DUPLX 0x20
|
||
|
-#define MAC_CTRL_ADD_CRC 0x40
|
||
|
-#define MAC_CTRL_PAD 0x80
|
||
|
-#define MAC_CTRL_LENCHK 0x100
|
||
|
-#define MAC_CTRL_HUGE_EN 0x200
|
||
|
-#define MAC_CTRL_PRMLEN_SHIFT 10
|
||
|
-#define MAC_CTRL_PRMLEN_MASK 0xf
|
||
|
-#define MAC_CTRL_RMV_VLAN 0x4000
|
||
|
-#define MAC_CTRL_PROMIS_EN 0x8000
|
||
|
-#define MAC_CTRL_TX_PAUSE 0x10000
|
||
|
-#define MAC_CTRL_SCNT 0x20000
|
||
|
-#define MAC_CTRL_SRST_TX 0x40000
|
||
|
-#define MAC_CTRL_TX_SIMURST 0x80000
|
||
|
-#define MAC_CTRL_SPEED_SHIFT 20
|
||
|
-#define MAC_CTRL_SPEED_MASK 0x3
|
||
|
-#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
|
||
|
-#define MAC_CTRL_TX_HUGE 0x800000
|
||
|
-#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
|
||
|
-#define MAC_CTRL_MC_ALL_EN 0x2000000
|
||
|
-#define MAC_CTRL_BC_EN 0x4000000
|
||
|
-#define MAC_CTRL_DBG 0x8000000
|
||
|
-#define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000
|
||
|
-#define MAC_CTRL_HASH_ALG_CRC32 0x20000000
|
||
|
-#define MAC_CTRL_SPEED_MODE_SW 0x40000000
|
||
|
+#define MAC_CTRL_SPEED_MODE_SW BIT(30) /* 0:phy,1:sw */
|
||
|
+#define MAC_CTRL_HASH_ALG_CRC32 BIT(29) /* 1:legacy,0:lw_5b */
|
||
|
+#define MAC_CTRL_SINGLE_PAUSE_EN BIT(28)
|
||
|
+#define MAC_CTRL_DBG BIT(27)
|
||
|
+#define MAC_CTRL_BC_EN BIT(26)
|
||
|
+#define MAC_CTRL_MC_ALL_EN BIT(25)
|
||
|
+#define MAC_CTRL_RX_CHKSUM_EN BIT(24)
|
||
|
+#define MAC_CTRL_TX_HUGE BIT(23)
|
||
|
+#define MAC_CTRL_DBG_TX_BKPRESURE BIT(22)
|
||
|
+#define MAC_CTRL_SPEED_MASK 3UL
|
||
|
+#define MAC_CTRL_SPEED_SHIFT 20
|
||
|
+#define MAC_CTRL_SPEED_10_100 1
|
||
|
+#define MAC_CTRL_SPEED_1000 2
|
||
|
+#define MAC_CTRL_TX_SIMURST BIT(19)
|
||
|
+#define MAC_CTRL_SCNT BIT(17)
|
||
|
+#define MAC_CTRL_TX_PAUSE BIT(16)
|
||
|
+#define MAC_CTRL_PROMIS_EN BIT(15)
|
||
|
+#define MAC_CTRL_RMV_VLAN BIT(14)
|
||
|
+#define MAC_CTRL_PRMLEN_MASK 0xFUL
|
||
|
+#define MAC_CTRL_PRMLEN_SHIFT 10
|
||
|
+#define MAC_CTRL_HUGE_EN BIT(9)
|
||
|
+#define MAC_CTRL_LENCHK BIT(8)
|
||
|
+#define MAC_CTRL_PAD BIT(7)
|
||
|
+#define MAC_CTRL_ADD_CRC BIT(6)
|
||
|
+#define MAC_CTRL_DUPLX BIT(5)
|
||
|
+#define MAC_CTRL_LOOPBACK BIT(4)
|
||
|
+#define MAC_CTRL_RX_FLOW BIT(3)
|
||
|
+#define MAC_CTRL_TX_FLOW BIT(2)
|
||
|
+#define MAC_CTRL_RX_EN BIT(1)
|
||
|
+#define MAC_CTRL_TX_EN BIT(0)
|
||
|
|
||
|
/* MAC IPG/IFG Control Register */
|
||
|
#define REG_MAC_IPG_IFG 0x1484
|
||
|
@@ -386,34 +443,53 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
|
||
|
/* Wake-On-Lan control register */
|
||
|
#define REG_WOL_CTRL 0x14a0
|
||
|
-#define WOL_PATTERN_EN 0x00000001
|
||
|
-#define WOL_PATTERN_PME_EN 0x00000002
|
||
|
-#define WOL_MAGIC_EN 0x00000004
|
||
|
-#define WOL_MAGIC_PME_EN 0x00000008
|
||
|
-#define WOL_LINK_CHG_EN 0x00000010
|
||
|
-#define WOL_LINK_CHG_PME_EN 0x00000020
|
||
|
-#define WOL_PATTERN_ST 0x00000100
|
||
|
-#define WOL_MAGIC_ST 0x00000200
|
||
|
-#define WOL_LINKCHG_ST 0x00000400
|
||
|
-#define WOL_CLK_SWITCH_EN 0x00008000
|
||
|
-#define WOL_PT0_EN 0x00010000
|
||
|
-#define WOL_PT1_EN 0x00020000
|
||
|
-#define WOL_PT2_EN 0x00040000
|
||
|
-#define WOL_PT3_EN 0x00080000
|
||
|
-#define WOL_PT4_EN 0x00100000
|
||
|
-#define WOL_PT5_EN 0x00200000
|
||
|
-#define WOL_PT6_EN 0x00400000
|
||
|
+#define WOL_PT7_MATCH BIT(31)
|
||
|
+#define WOL_PT6_MATCH BIT(30)
|
||
|
+#define WOL_PT5_MATCH BIT(29)
|
||
|
+#define WOL_PT4_MATCH BIT(28)
|
||
|
+#define WOL_PT3_MATCH BIT(27)
|
||
|
+#define WOL_PT2_MATCH BIT(26)
|
||
|
+#define WOL_PT1_MATCH BIT(25)
|
||
|
+#define WOL_PT0_MATCH BIT(24)
|
||
|
+#define WOL_PT7_EN BIT(23)
|
||
|
+#define WOL_PT6_EN BIT(22)
|
||
|
+#define WOL_PT5_EN BIT(21)
|
||
|
+#define WOL_PT4_EN BIT(20)
|
||
|
+#define WOL_PT3_EN BIT(19)
|
||
|
+#define WOL_PT2_EN BIT(18)
|
||
|
+#define WOL_PT1_EN BIT(17)
|
||
|
+#define WOL_PT0_EN BIT(16)
|
||
|
+#define WOL_LNKCHG_ST BIT(10)
|
||
|
+#define WOL_MAGIC_ST BIT(9)
|
||
|
+#define WOL_PATTERN_ST BIT(8)
|
||
|
+#define WOL_OOB_EN BIT(6)
|
||
|
+#define WOL_LINK_CHG_PME_EN BIT(5)
|
||
|
+#define WOL_LINK_CHG_EN BIT(4)
|
||
|
+#define WOL_MAGIC_PME_EN BIT(3)
|
||
|
+#define WOL_MAGIC_EN BIT(2)
|
||
|
+#define WOL_PATTERN_PME_EN BIT(1)
|
||
|
+#define WOL_PATTERN_EN BIT(0)
|
||
|
|
||
|
/* WOL Length ( 2 DWORD ) */
|
||
|
-#define REG_WOL_PATTERN_LEN 0x14a4
|
||
|
-#define WOL_PT_LEN_MASK 0x7f
|
||
|
-#define WOL_PT0_LEN_SHIFT 0
|
||
|
-#define WOL_PT1_LEN_SHIFT 8
|
||
|
-#define WOL_PT2_LEN_SHIFT 16
|
||
|
-#define WOL_PT3_LEN_SHIFT 24
|
||
|
-#define WOL_PT4_LEN_SHIFT 0
|
||
|
-#define WOL_PT5_LEN_SHIFT 8
|
||
|
-#define WOL_PT6_LEN_SHIFT 16
|
||
|
+#define REG_WOL_PTLEN1 0x14A4
|
||
|
+#define WOL_PTLEN1_3_MASK 0xFFUL
|
||
|
+#define WOL_PTLEN1_3_SHIFT 24
|
||
|
+#define WOL_PTLEN1_2_MASK 0xFFUL
|
||
|
+#define WOL_PTLEN1_2_SHIFT 16
|
||
|
+#define WOL_PTLEN1_1_MASK 0xFFUL
|
||
|
+#define WOL_PTLEN1_1_SHIFT 8
|
||
|
+#define WOL_PTLEN1_0_MASK 0xFFUL
|
||
|
+#define WOL_PTLEN1_0_SHIFT 0
|
||
|
+
|
||
|
+#define REG_WOL_PTLEN2 0x14A8
|
||
|
+#define WOL_PTLEN2_7_MASK 0xFFUL
|
||
|
+#define WOL_PTLEN2_7_SHIFT 24
|
||
|
+#define WOL_PTLEN2_6_MASK 0xFFUL
|
||
|
+#define WOL_PTLEN2_6_SHIFT 16
|
||
|
+#define WOL_PTLEN2_5_MASK 0xFFUL
|
||
|
+#define WOL_PTLEN2_5_SHIFT 8
|
||
|
+#define WOL_PTLEN2_4_MASK 0xFFUL
|
||
|
+#define WOL_PTLEN2_4_SHIFT 0
|
||
|
|
||
|
/* Internal SRAM Partition Register */
|
||
|
#define RFDX_HEAD_ADDR_MASK 0x03FF
|
||
|
@@ -458,66 +534,50 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
*/
|
||
|
#define REG_RX_BASE_ADDR_HI 0x1540
|
||
|
#define REG_TX_BASE_ADDR_HI 0x1544
|
||
|
-#define REG_SMB_BASE_ADDR_HI 0x1548
|
||
|
-#define REG_SMB_BASE_ADDR_LO 0x154C
|
||
|
#define REG_RFD0_HEAD_ADDR_LO 0x1550
|
||
|
-#define REG_RFD1_HEAD_ADDR_LO 0x1554
|
||
|
-#define REG_RFD2_HEAD_ADDR_LO 0x1558
|
||
|
-#define REG_RFD3_HEAD_ADDR_LO 0x155C
|
||
|
#define REG_RFD_RING_SIZE 0x1560
|
||
|
#define RFD_RING_SIZE_MASK 0x0FFF
|
||
|
#define REG_RX_BUF_SIZE 0x1564
|
||
|
#define RX_BUF_SIZE_MASK 0xFFFF
|
||
|
#define REG_RRD0_HEAD_ADDR_LO 0x1568
|
||
|
-#define REG_RRD1_HEAD_ADDR_LO 0x156C
|
||
|
-#define REG_RRD2_HEAD_ADDR_LO 0x1570
|
||
|
-#define REG_RRD3_HEAD_ADDR_LO 0x1574
|
||
|
#define REG_RRD_RING_SIZE 0x1578
|
||
|
#define RRD_RING_SIZE_MASK 0x0FFF
|
||
|
-#define REG_HTPD_HEAD_ADDR_LO 0x157C
|
||
|
-#define REG_NTPD_HEAD_ADDR_LO 0x1580
|
||
|
+#define REG_TPD_PRI1_ADDR_LO 0x157C
|
||
|
+#define REG_TPD_PRI0_ADDR_LO 0x1580
|
||
|
#define REG_TPD_RING_SIZE 0x1584
|
||
|
#define TPD_RING_SIZE_MASK 0xFFFF
|
||
|
-#define REG_CMB_BASE_ADDR_LO 0x1588
|
||
|
-
|
||
|
-/* RSS about */
|
||
|
-#define REG_RSS_KEY0 0x14B0
|
||
|
-#define REG_RSS_KEY1 0x14B4
|
||
|
-#define REG_RSS_KEY2 0x14B8
|
||
|
-#define REG_RSS_KEY3 0x14BC
|
||
|
-#define REG_RSS_KEY4 0x14C0
|
||
|
-#define REG_RSS_KEY5 0x14C4
|
||
|
-#define REG_RSS_KEY6 0x14C8
|
||
|
-#define REG_RSS_KEY7 0x14CC
|
||
|
-#define REG_RSS_KEY8 0x14D0
|
||
|
-#define REG_RSS_KEY9 0x14D4
|
||
|
-#define REG_IDT_TABLE0 0x14E0
|
||
|
-#define REG_IDT_TABLE1 0x14E4
|
||
|
-#define REG_IDT_TABLE2 0x14E8
|
||
|
-#define REG_IDT_TABLE3 0x14EC
|
||
|
-#define REG_IDT_TABLE4 0x14F0
|
||
|
-#define REG_IDT_TABLE5 0x14F4
|
||
|
-#define REG_IDT_TABLE6 0x14F8
|
||
|
-#define REG_IDT_TABLE7 0x14FC
|
||
|
-#define REG_IDT_TABLE REG_IDT_TABLE0
|
||
|
-#define REG_RSS_HASH_VALUE 0x15B0
|
||
|
-#define REG_RSS_HASH_FLAG 0x15B4
|
||
|
-#define REG_BASE_CPU_NUMBER 0x15B8
|
||
|
|
||
|
/* TXQ Control Register */
|
||
|
-#define REG_TXQ_CTRL 0x1590
|
||
|
-#define TXQ_NUM_TPD_BURST_MASK 0xF
|
||
|
-#define TXQ_NUM_TPD_BURST_SHIFT 0
|
||
|
-#define TXQ_CTRL_IP_OPTION_EN 0x10
|
||
|
-#define TXQ_CTRL_EN 0x20
|
||
|
-#define TXQ_CTRL_ENH_MODE 0x40
|
||
|
-#define TXQ_CTRL_LS_8023_EN 0x80
|
||
|
-#define TXQ_TXF_BURST_NUM_SHIFT 16
|
||
|
-#define TXQ_TXF_BURST_NUM_MASK 0xFFFF
|
||
|
+#define REG_TXQ_CTRL 0x1590
|
||
|
+#define TXQ_TXF_BURST_NUM_MASK 0xFFFFUL
|
||
|
+#define TXQ_TXF_BURST_NUM_SHIFT 16
|
||
|
+#define L1C_TXQ_TXF_BURST_PREF 0x200
|
||
|
+#define L2CB_TXQ_TXF_BURST_PREF 0x40
|
||
|
+#define TXQ_CTRL_PEDING_CLR BIT(8)
|
||
|
+#define TXQ_CTRL_LS_8023_EN BIT(7)
|
||
|
+#define TXQ_CTRL_ENH_MODE BIT(6)
|
||
|
+#define TXQ_CTRL_EN BIT(5)
|
||
|
+#define TXQ_CTRL_IP_OPTION_EN BIT(4)
|
||
|
+#define TXQ_NUM_TPD_BURST_MASK 0xFUL
|
||
|
+#define TXQ_NUM_TPD_BURST_SHIFT 0
|
||
|
+#define TXQ_NUM_TPD_BURST_DEF 5
|
||
|
+#define TXQ_CFGV (\
|
||
|
+ FIELDX(TXQ_NUM_TPD_BURST, TXQ_NUM_TPD_BURST_DEF) |\
|
||
|
+ TXQ_CTRL_ENH_MODE |\
|
||
|
+ TXQ_CTRL_LS_8023_EN |\
|
||
|
+ TXQ_CTRL_IP_OPTION_EN)
|
||
|
+#define L1C_TXQ_CFGV (\
|
||
|
+ TXQ_CFGV |\
|
||
|
+ FIELDX(TXQ_TXF_BURST_NUM, L1C_TXQ_TXF_BURST_PREF))
|
||
|
+#define L2CB_TXQ_CFGV (\
|
||
|
+ TXQ_CFGV |\
|
||
|
+ FIELDX(TXQ_TXF_BURST_NUM, L2CB_TXQ_TXF_BURST_PREF))
|
||
|
+
|
||
|
|
||
|
/* Jumbo packet Threshold for task offload */
|
||
|
#define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */
|
||
|
#define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF
|
||
|
+#define MAX_TSO_FRAME_SIZE (7*1024)
|
||
|
|
||
|
#define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */
|
||
|
#define TXF_WATER_MARK_MASK 0x0FFF
|
||
|
@@ -537,26 +597,21 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
#define ASPM_THRUPUT_LIMIT_NO 0x00
|
||
|
#define ASPM_THRUPUT_LIMIT_1M 0x01
|
||
|
#define ASPM_THRUPUT_LIMIT_10M 0x02
|
||
|
-#define ASPM_THRUPUT_LIMIT_100M 0x04
|
||
|
-#define RXQ1_CTRL_EN 0x10
|
||
|
-#define RXQ2_CTRL_EN 0x20
|
||
|
-#define RXQ3_CTRL_EN 0x40
|
||
|
-#define IPV6_CHKSUM_CTRL_EN 0x80
|
||
|
-#define RSS_HASH_BITS_MASK 0x00FF
|
||
|
-#define RSS_HASH_BITS_SHIFT 8
|
||
|
-#define RSS_HASH_IPV4 0x10000
|
||
|
-#define RSS_HASH_IPV4_TCP 0x20000
|
||
|
-#define RSS_HASH_IPV6 0x40000
|
||
|
-#define RSS_HASH_IPV6_TCP 0x80000
|
||
|
+#define ASPM_THRUPUT_LIMIT_100M 0x03
|
||
|
+#define IPV6_CHKSUM_CTRL_EN BIT(7)
|
||
|
#define RXQ_RFD_BURST_NUM_MASK 0x003F
|
||
|
#define RXQ_RFD_BURST_NUM_SHIFT 20
|
||
|
-#define RSS_MODE_MASK 0x0003
|
||
|
+#define RXQ_NUM_RFD_PREF_DEF 8
|
||
|
+#define RSS_MODE_MASK 3UL
|
||
|
#define RSS_MODE_SHIFT 26
|
||
|
-#define RSS_NIP_QUEUE_SEL_MASK 0x1
|
||
|
-#define RSS_NIP_QUEUE_SEL_SHIFT 28
|
||
|
-#define RRS_HASH_CTRL_EN 0x20000000
|
||
|
-#define RX_CUT_THRU_EN 0x40000000
|
||
|
-#define RXQ_CTRL_EN 0x80000000
|
||
|
+#define RSS_MODE_DIS 0
|
||
|
+#define RSS_MODE_SQSI 1
|
||
|
+#define RSS_MODE_MQSI 2
|
||
|
+#define RSS_MODE_MQMI 3
|
||
|
+#define RSS_NIP_QUEUE_SEL BIT(28) /* 0:q0, 1:table */
|
||
|
+#define RRS_HASH_CTRL_EN BIT(29)
|
||
|
+#define RX_CUT_THRU_EN BIT(30)
|
||
|
+#define RXQ_CTRL_EN BIT(31)
|
||
|
|
||
|
#define REG_RFD_FREE_THRESH 0x15A4
|
||
|
#define RFD_FREE_THRESH_MASK 0x003F
|
||
|
@@ -577,57 +632,45 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
#define RXD_DMA_DOWN_TIMER_SHIFT 16
|
||
|
|
||
|
/* DMA Engine Control Register */
|
||
|
-#define REG_DMA_CTRL 0x15C0
|
||
|
-#define DMA_CTRL_DMAR_IN_ORDER 0x1
|
||
|
-#define DMA_CTRL_DMAR_ENH_ORDER 0x2
|
||
|
-#define DMA_CTRL_DMAR_OUT_ORDER 0x4
|
||
|
-#define DMA_CTRL_RCB_VALUE 0x8
|
||
|
-#define DMA_CTRL_DMAR_BURST_LEN_MASK 0x0007
|
||
|
-#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
|
||
|
-#define DMA_CTRL_DMAW_BURST_LEN_MASK 0x0007
|
||
|
-#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
|
||
|
-#define DMA_CTRL_DMAR_REQ_PRI 0x400
|
||
|
-#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x001F
|
||
|
-#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
|
||
|
-#define DMA_CTRL_DMAW_DLY_CNT_MASK 0x000F
|
||
|
-#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
|
||
|
-#define DMA_CTRL_CMB_EN 0x100000
|
||
|
-#define DMA_CTRL_SMB_EN 0x200000
|
||
|
-#define DMA_CTRL_CMB_NOW 0x400000
|
||
|
-#define MAC_CTRL_SMB_DIS 0x1000000
|
||
|
-#define DMA_CTRL_SMB_NOW 0x80000000
|
||
|
-
|
||
|
-/* CMB/SMB Control Register */
|
||
|
+#define REG_DMA_CTRL 0x15C0
|
||
|
+#define DMA_CTRL_SMB_NOW BIT(31)
|
||
|
+#define DMA_CTRL_WPEND_CLR BIT(30)
|
||
|
+#define DMA_CTRL_RPEND_CLR BIT(29)
|
||
|
+#define DMA_CTRL_WDLY_CNT_MASK 0xFUL
|
||
|
+#define DMA_CTRL_WDLY_CNT_SHIFT 16
|
||
|
+#define DMA_CTRL_WDLY_CNT_DEF 4
|
||
|
+#define DMA_CTRL_RDLY_CNT_MASK 0x1FUL
|
||
|
+#define DMA_CTRL_RDLY_CNT_SHIFT 11
|
||
|
+#define DMA_CTRL_RDLY_CNT_DEF 15
|
||
|
+#define DMA_CTRL_RREQ_PRI_DATA BIT(10) /* 0:tpd, 1:data */
|
||
|
+#define DMA_CTRL_WREQ_BLEN_MASK 7UL
|
||
|
+#define DMA_CTRL_WREQ_BLEN_SHIFT 7
|
||
|
+#define DMA_CTRL_RREQ_BLEN_MASK 7UL
|
||
|
+#define DMA_CTRL_RREQ_BLEN_SHIFT 4
|
||
|
+#define L1C_CTRL_DMA_RCB_LEN128 BIT(3) /* 0:64bytes,1:128bytes */
|
||
|
+#define DMA_CTRL_RORDER_MODE_MASK 7UL
|
||
|
+#define DMA_CTRL_RORDER_MODE_SHIFT 0
|
||
|
+#define DMA_CTRL_RORDER_MODE_OUT 4
|
||
|
+#define DMA_CTRL_RORDER_MODE_ENHANCE 2
|
||
|
+#define DMA_CTRL_RORDER_MODE_IN 1
|
||
|
+
|
||
|
+/* INT-triggle/SMB Control Register */
|
||
|
#define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */
|
||
|
#define SMB_STAT_TIMER_MASK 0xFFFFFF
|
||
|
-#define REG_CMB_TPD_THRESH 0x15C8
|
||
|
-#define CMB_TPD_THRESH_MASK 0xFFFF
|
||
|
-#define REG_CMB_TX_TIMER 0x15CC /* 2us resolution */
|
||
|
-#define CMB_TX_TIMER_MASK 0xFFFF
|
||
|
+#define REG_TINT_TPD_THRESH 0x15C8 /* tpd th to trig intrrupt */
|
||
|
|
||
|
/* Mail box */
|
||
|
#define MB_RFDX_PROD_IDX_MASK 0xFFFF
|
||
|
#define REG_MB_RFD0_PROD_IDX 0x15E0
|
||
|
-#define REG_MB_RFD1_PROD_IDX 0x15E4
|
||
|
-#define REG_MB_RFD2_PROD_IDX 0x15E8
|
||
|
-#define REG_MB_RFD3_PROD_IDX 0x15EC
|
||
|
|
||
|
-#define MB_PRIO_PROD_IDX_MASK 0xFFFF
|
||
|
-#define REG_MB_PRIO_PROD_IDX 0x15F0
|
||
|
-#define MB_HTPD_PROD_IDX_SHIFT 0
|
||
|
-#define MB_NTPD_PROD_IDX_SHIFT 16
|
||
|
-
|
||
|
-#define MB_PRIO_CONS_IDX_MASK 0xFFFF
|
||
|
-#define REG_MB_PRIO_CONS_IDX 0x15F4
|
||
|
-#define MB_HTPD_CONS_IDX_SHIFT 0
|
||
|
-#define MB_NTPD_CONS_IDX_SHIFT 16
|
||
|
+#define REG_TPD_PRI1_PIDX 0x15F0 /* 16bit,hi-tpd producer idx */
|
||
|
+#define REG_TPD_PRI0_PIDX 0x15F2 /* 16bit,lo-tpd producer idx */
|
||
|
+#define REG_TPD_PRI1_CIDX 0x15F4 /* 16bit,hi-tpd consumer idx */
|
||
|
+#define REG_TPD_PRI0_CIDX 0x15F6 /* 16bit,lo-tpd consumer idx */
|
||
|
|
||
|
#define REG_MB_RFD01_CONS_IDX 0x15F8
|
||
|
#define MB_RFD0_CONS_IDX_MASK 0x0000FFFF
|
||
|
#define MB_RFD1_CONS_IDX_MASK 0xFFFF0000
|
||
|
-#define REG_MB_RFD23_CONS_IDX 0x15FC
|
||
|
-#define MB_RFD2_CONS_IDX_MASK 0x0000FFFF
|
||
|
-#define MB_RFD3_CONS_IDX_MASK 0xFFFF0000
|
||
|
|
||
|
/* Interrupt Status Register */
|
||
|
#define REG_ISR 0x1600
|
||
|
@@ -705,13 +748,6 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
#define REG_INT_RETRIG_TIMER 0x1608
|
||
|
#define INT_RETRIG_TIMER_MASK 0xFFFF
|
||
|
|
||
|
-#define REG_HDS_CTRL 0x160C
|
||
|
-#define HDS_CTRL_EN 0x0001
|
||
|
-#define HDS_CTRL_BACKFILLSIZE_SHIFT 8
|
||
|
-#define HDS_CTRL_BACKFILLSIZE_MASK 0x0FFF
|
||
|
-#define HDS_CTRL_MAX_HDRSIZE_SHIFT 20
|
||
|
-#define HDS_CTRL_MAC_HDRSIZE_MASK 0x0FFF
|
||
|
-
|
||
|
#define REG_MAC_RX_STATUS_BIN 0x1700
|
||
|
#define REG_MAC_RX_STATUS_END 0x175c
|
||
|
#define REG_MAC_TX_STATUS_BIN 0x1760
|
||
|
@@ -796,73 +832,188 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
|
||
|
#define MII_DBG_ADDR 0x1D
|
||
|
#define MII_DBG_DATA 0x1E
|
||
|
|
||
|
-#define MII_ANA_CTRL_0 0x0
|
||
|
-#define ANA_RESTART_CAL 0x0001
|
||
|
-#define ANA_MANUL_SWICH_ON_SHIFT 0x1
|
||
|
-#define ANA_MANUL_SWICH_ON_MASK 0xF
|
||
|
-#define ANA_MAN_ENABLE 0x0020
|
||
|
-#define ANA_SEL_HSP 0x0040
|
||
|
-#define ANA_EN_HB 0x0080
|
||
|
-#define ANA_EN_HBIAS 0x0100
|
||
|
-#define ANA_OEN_125M 0x0200
|
||
|
-#define ANA_EN_LCKDT 0x0400
|
||
|
-#define ANA_LCKDT_PHY 0x0800
|
||
|
-#define ANA_AFE_MODE 0x1000
|
||
|
-#define ANA_VCO_SLOW 0x2000
|
||
|
-#define ANA_VCO_FAST 0x4000
|
||
|
-#define ANA_SEL_CLK125M_DSP 0x8000
|
||
|
-
|
||
|
-#define MII_ANA_CTRL_4 0x4
|
||
|
-#define ANA_IECHO_ADJ_MASK 0xF
|
||
|
-#define ANA_IECHO_ADJ_3_SHIFT 0
|
||
|
-#define ANA_IECHO_ADJ_2_SHIFT 4
|
||
|
-#define ANA_IECHO_ADJ_1_SHIFT 8
|
||
|
-#define ANA_IECHO_ADJ_0_SHIFT 12
|
||
|
-
|
||
|
-#define MII_ANA_CTRL_5 0x5
|
||
|
-#define ANA_SERDES_CDR_BW_SHIFT 0
|
||
|
-#define ANA_SERDES_CDR_BW_MASK 0x3
|
||
|
-#define ANA_MS_PAD_DBG 0x0004
|
||
|
-#define ANA_SPEEDUP_DBG 0x0008
|
||
|
-#define ANA_SERDES_TH_LOS_SHIFT 4
|
||
|
-#define ANA_SERDES_TH_LOS_MASK 0x3
|
||
|
-#define ANA_SERDES_EN_DEEM 0x0040
|
||
|
-#define ANA_SERDES_TXELECIDLE 0x0080
|
||
|
-#define ANA_SERDES_BEACON 0x0100
|
||
|
-#define ANA_SERDES_HALFTXDR 0x0200
|
||
|
-#define ANA_SERDES_SEL_HSP 0x0400
|
||
|
-#define ANA_SERDES_EN_PLL 0x0800
|
||
|
-#define ANA_SERDES_EN 0x1000
|
||
|
-#define ANA_SERDES_EN_LCKDT 0x2000
|
||
|
-
|
||
|
-#define MII_ANA_CTRL_11 0xB
|
||
|
-#define ANA_PS_HIB_EN 0x8000
|
||
|
-
|
||
|
-#define MII_ANA_CTRL_18 0x12
|
||
|
-#define ANA_TEST_MODE_10BT_01SHIFT 0
|
||
|
-#define ANA_TEST_MODE_10BT_01MASK 0x3
|
||
|
-#define ANA_LOOP_SEL_10BT 0x0004
|
||
|
-#define ANA_RGMII_MODE_SW 0x0008
|
||
|
-#define ANA_EN_LONGECABLE 0x0010
|
||
|
-#define ANA_TEST_MODE_10BT_2 0x0020
|
||
|
-#define ANA_EN_10BT_IDLE 0x0400
|
||
|
-#define ANA_EN_MASK_TB 0x0800
|
||
|
-#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
|
||
|
-#define ANA_TRIGGER_SEL_TIMER_MASK 0x3
|
||
|
-#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
|
||
|
-#define ANA_INTERVAL_SEL_TIMER_MASK 0x3
|
||
|
-
|
||
|
-#define MII_ANA_CTRL_41 0x29
|
||
|
-#define ANA_TOP_PS_EN 0x8000
|
||
|
-
|
||
|
-#define MII_ANA_CTRL_54 0x36
|
||
|
-#define ANA_LONG_CABLE_TH_100_SHIFT 0
|
||
|
-#define ANA_LONG_CABLE_TH_100_MASK 0x3F
|
||
|
-#define ANA_DESERVED 0x0040
|
||
|
-#define ANA_EN_LIT_CH 0x0080
|
||
|
-#define ANA_SHORT_CABLE_TH_100_SHIFT 8
|
||
|
-#define ANA_SHORT_CABLE_TH_100_MASK 0x3F
|
||
|
-#define ANA_BP_BAD_LINK_ACCUM 0x4000
|
||
|
-#define ANA_BP_SMALL_BW 0x8000
|
||
|
+/***************************** debug port *************************************/
|
||
|
+
|
||
|
+#define MIIDBG_ANACTRL 0x00
|
||
|
+#define ANACTRL_CLK125M_DELAY_EN 0x8000
|
||
|
+#define ANACTRL_VCO_FAST 0x4000
|
||
|
+#define ANACTRL_VCO_SLOW 0x2000
|
||
|
+#define ANACTRL_AFE_MODE_EN 0x1000
|
||
|
+#define ANACTRL_LCKDET_PHY 0x800
|
||
|
+#define ANACTRL_LCKDET_EN 0x400
|
||
|
+#define ANACTRL_OEN_125M 0x200
|
||
|
+#define ANACTRL_HBIAS_EN 0x100
|
||
|
+#define ANACTRL_HB_EN 0x80
|
||
|
+#define ANACTRL_SEL_HSP 0x40
|
||
|
+#define ANACTRL_CLASSA_EN 0x20
|
||
|
+#define ANACTRL_MANUSWON_SWR_MASK 3U
|
||
|
+#define ANACTRL_MANUSWON_SWR_SHIFT 2
|
||
|
+#define ANACTRL_MANUSWON_SWR_2V 0
|
||
|
+#define ANACTRL_MANUSWON_SWR_1P9V 1
|
||
|
+#define ANACTRL_MANUSWON_SWR_1P8V 2
|
||
|
+#define ANACTRL_MANUSWON_SWR_1P7V 3
|
||
|
+#define ANACTRL_MANUSWON_BW3_4M 0x2
|
||
|
+#define ANACTRL_RESTART_CAL 0x1
|
||
|
+#define ANACTRL_DEF 0x02EF
|
||
|
+
|
||
|
+#define MIIDBG_SYSMODCTRL 0x04
|
||
|
+#define SYSMODCTRL_IECHOADJ_PFMH_PHY 0x8000
|
||
|
+#define SYSMODCTRL_IECHOADJ_BIASGEN 0x4000
|
||
|
+#define SYSMODCTRL_IECHOADJ_PFML_PHY 0x2000
|
||
|
+#define SYSMODCTRL_IECHOADJ_PS_MASK 3U
|
||
|
+#define SYSMODCTRL_IECHOADJ_PS_SHIFT 10
|
||
|
+#define SYSMODCTRL_IECHOADJ_PS_40 3
|
||
|
+#define SYSMODCTRL_IECHOADJ_PS_20 2
|
||
|
+#define SYSMODCTRL_IECHOADJ_PS_0 1
|
||
|
+#define SYSMODCTRL_IECHOADJ_10BT_100MV 0x40 /* 1:100mv, 0:200mv */
|
||
|
+#define SYSMODCTRL_IECHOADJ_HLFAP_MASK 3U
|
||
|
+#define SYSMODCTRL_IECHOADJ_HLFAP_SHIFT 4
|
||
|
+#define SYSMODCTRL_IECHOADJ_VDFULBW 0x8
|
||
|
+#define SYSMODCTRL_IECHOADJ_VDBIASHLF 0x4
|
||
|
+#define SYSMODCTRL_IECHOADJ_VDAMPHLF 0x2
|
||
|
+#define SYSMODCTRL_IECHOADJ_VDLANSW 0x1
|
||
|
+#define SYSMODCTRL_IECHOADJ_DEF 0x88BB /* ???? */
|
||
|
+
|
||
|
+/* for l1d & l2cb */
|
||
|
+#define SYSMODCTRL_IECHOADJ_CUR_ADD 0x8000
|
||
|
+#define SYSMODCTRL_IECHOADJ_CUR_MASK 7U
|
||
|
+#define SYSMODCTRL_IECHOADJ_CUR_SHIFT 12
|
||
|
+#define SYSMODCTRL_IECHOADJ_VOL_MASK 0xFU
|
||
|
+#define SYSMODCTRL_IECHOADJ_VOL_SHIFT 8
|
||
|
+#define SYSMODCTRL_IECHOADJ_VOL_17ALL 3
|
||
|
+#define SYSMODCTRL_IECHOADJ_VOL_100M15 1
|
||
|
+#define SYSMODCTRL_IECHOADJ_VOL_10M17 0
|
||
|
+#define SYSMODCTRL_IECHOADJ_BIAS1_MASK 0xFU
|
||
|
+#define SYSMODCTRL_IECHOADJ_BIAS1_SHIFT 4
|
||
|
+#define SYSMODCTRL_IECHOADJ_BIAS2_MASK 0xFU
|
||
|
+#define SYSMODCTRL_IECHOADJ_BIAS2_SHIFT 0
|
||
|
+#define L1D_SYSMODCTRL_IECHOADJ_DEF 0x4FBB
|
||
|
+
|
||
|
+#define MIIDBG_SRDSYSMOD 0x05
|
||
|
+#define SRDSYSMOD_LCKDET_EN 0x2000
|
||
|
+#define SRDSYSMOD_PLL_EN 0x800
|
||
|
+#define SRDSYSMOD_SEL_HSP 0x400
|
||
|
+#define SRDSYSMOD_HLFTXDR 0x200
|
||
|
+#define SRDSYSMOD_TXCLK_DELAY_EN 0x100
|
||
|
+#define SRDSYSMOD_TXELECIDLE 0x80
|
||
|
+#define SRDSYSMOD_DEEMP_EN 0x40
|
||
|
+#define SRDSYSMOD_MS_PAD 0x4
|
||
|
+#define SRDSYSMOD_CDR_ADC_VLTG 0x2
|
||
|
+#define SRDSYSMOD_CDR_DAC_1MA 0x1
|
||
|
+#define SRDSYSMOD_DEF 0x2C46
|
||
|
+
|
||
|
+#define MIIDBG_CFGLPSPD 0x0A
|
||
|
+#define CFGLPSPD_RSTCNT_MASK 3U
|
||
|
+#define CFGLPSPD_RSTCNT_SHIFT 14
|
||
|
+#define CFGLPSPD_RSTCNT_CLK125SW 0x2000
|
||
|
+
|
||
|
+#define MIIDBG_HIBNEG 0x0B
|
||
|
+#define HIBNEG_PSHIB_EN 0x8000
|
||
|
+#define HIBNEG_WAKE_BOTH 0x4000
|
||
|
+#define HIBNEG_ONOFF_ANACHG_SUDEN 0x2000
|
||
|
+#define HIBNEG_HIB_PULSE 0x1000
|
||
|
+#define HIBNEG_GATE_25M_EN 0x800
|
||
|
+#define HIBNEG_RST_80U 0x400
|
||
|
+#define HIBNEG_RST_TIMER_MASK 3U
|
||
|
+#define HIBNEG_RST_TIMER_SHIFT 8
|
||
|
+#define HIBNEG_GTX_CLK_DELAY_MASK 3U
|
||
|
+#define HIBNEG_GTX_CLK_DELAY_SHIFT 5
|
||
|
+#define HIBNEG_BYPSS_BRKTIMER 0x10
|
||
|
+#define HIBNEG_DEF 0xBC40
|
||
|
+
|
||
|
+#define MIIDBG_TST10BTCFG 0x12
|
||
|
+#define TST10BTCFG_INTV_TIMER_MASK 3U
|
||
|
+#define TST10BTCFG_INTV_TIMER_SHIFT 14
|
||
|
+#define TST10BTCFG_TRIGER_TIMER_MASK 3U
|
||
|
+#define TST10BTCFG_TRIGER_TIMER_SHIFT 12
|
||
|
+#define TST10BTCFG_DIV_MAN_MLT3_EN 0x800
|
||
|
+#define TST10BTCFG_OFF_DAC_IDLE 0x400
|
||
|
+#define TST10BTCFG_LPBK_DEEP 0x4 /* 1:deep,0:shallow */
|
||
|
+#define TST10BTCFG_DEF 0x4C04
|
||
|
+
|
||
|
+#define MIIDBG_AZ_ANADECT 0x15
|
||
|
+#define AZ_ANADECT_10BTRX_TH 0x8000
|
||
|
+#define AZ_ANADECT_BOTH_01CHNL 0x4000
|
||
|
+#define AZ_ANADECT_INTV_MASK 0x3FU
|
||
|
+#define AZ_ANADECT_INTV_SHIFT 8
|
||
|
+#define AZ_ANADECT_THRESH_MASK 0xFU
|
||
|
+#define AZ_ANADECT_THRESH_SHIFT 4
|
||
|
+#define AZ_ANADECT_CHNL_MASK 0xFU
|
||
|
+#define AZ_ANADECT_CHNL_SHIFT 0
|
||
|
+#define AZ_ANADECT_DEF 0x3220
|
||
|
+#define AZ_ANADECT_LONG 0xb210
|
||
|
+
|
||
|
+#define MIIDBG_MSE16DB 0x18 /* l1d */
|
||
|
+#define L1D_MSE16DB_UP 0x05EA
|
||
|
+#define L1D_MSE16DB_DOWN 0x02EA
|
||
|
+
|
||
|
+#define MIIDBG_LEGCYPS 0x29
|
||
|
+#define LEGCYPS_EN 0x8000
|
||
|
+#define LEGCYPS_DAC_AMP1000_MASK 7U
|
||
|
+#define LEGCYPS_DAC_AMP1000_SHIFT 12
|
||
|
+#define LEGCYPS_DAC_AMP100_MASK 7U
|
||
|
+#define LEGCYPS_DAC_AMP100_SHIFT 9
|
||
|
+#define LEGCYPS_DAC_AMP10_MASK 7U
|
||
|
+#define LEGCYPS_DAC_AMP10_SHIFT 6
|
||
|
+#define LEGCYPS_UNPLUG_TIMER_MASK 7U
|
||
|
+#define LEGCYPS_UNPLUG_TIMER_SHIFT 3
|
||
|
+#define LEGCYPS_UNPLUG_DECT_EN 0x4
|
||
|
+#define LEGCYPS_ECNC_PS_EN 0x1
|
||
|
+#define L1D_LEGCYPS_DEF 0x129D
|
||
|
+#define L1C_LEGCYPS_DEF 0x36DD
|
||
|
+
|
||
|
+#define MIIDBG_TST100BTCFG 0x36
|
||
|
+#define TST100BTCFG_NORMAL_BW_EN 0x8000
|
||
|
+#define TST100BTCFG_BADLNK_BYPASS 0x4000
|
||
|
+#define TST100BTCFG_SHORTCABL_TH_MASK 0x3FU
|
||
|
+#define TST100BTCFG_SHORTCABL_TH_SHIFT 8
|
||
|
+#define TST100BTCFG_LITCH_EN 0x80
|
||
|
+#define TST100BTCFG_VLT_SW 0x40
|
||
|
+#define TST100BTCFG_LONGCABL_TH_MASK 0x3FU
|
||
|
+#define TST100BTCFG_LONGCABL_TH_SHIFT 0
|
||
|
+#define TST100BTCFG_DEF 0xE12C
|
||
|
+
|
||
|
+#define MIIDBG_VOLT_CTRL 0x3B /* only for l2cb 1 & 2 */
|
||
|
+#define VOLT_CTRL_CABLE1TH_MASK 0x1FFU
|
||
|
+#define VOLT_CTRL_CABLE1TH_SHIFT 7
|
||
|
+#define VOLT_CTRL_AMPCTRL_MASK 3U
|
||
|
+#define VOLT_CTRL_AMPCTRL_SHIFT 5
|
||
|
+#define VOLT_CTRL_SW_BYPASS 0x10
|
||
|
+#define VOLT_CTRL_SWLOWEST 0x8
|
||
|
+#define VOLT_CTRL_DACAMP10_MASK 7U
|
||
|
+#define VOLT_CTRL_DACAMP10_SHIFT 0
|
||
|
+
|
||
|
+#define MIIDBG_CABLE1TH_DET 0x3E
|
||
|
+#define CABLE1TH_DET_EN 0x8000
|
||
|
+
|
||
|
+
|
||
|
+/******* dev 3 *********/
|
||
|
+#define MIIEXT_PCS 3
|
||
|
+
|
||
|
+#define MIIEXT_CLDCTRL3 0x8003
|
||
|
+#define CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000
|
||
|
+#define CLDCTRL3_AZ_DISAMP 0x1000
|
||
|
+#define L2CB_CLDCTRL3 0x4D19
|
||
|
+#define L1D_CLDCTRL3 0xDD19
|
||
|
+
|
||
|
+#define MIIEXT_CLDCTRL6 0x8006
|
||
|
+#define CLDCTRL6_CAB_LEN_MASK 0x1FFU
|
||
|
+#define CLDCTRL6_CAB_LEN_SHIFT 0
|
||
|
+#define CLDCTRL6_CAB_LEN_SHORT 0x50
|
||
|
+
|
||
|
+/********* dev 7 **********/
|
||
|
+#define MIIEXT_ANEG 7
|
||
|
+
|
||
|
+#define MIIEXT_LOCAL_EEEADV 0x3C
|
||
|
+#define LOCAL_EEEADV_1000BT 0x4
|
||
|
+#define LOCAL_EEEADV_100BT 0x2
|
||
|
+
|
||
|
+#define MIIEXT_REMOTE_EEEADV 0x3D
|
||
|
+#define REMOTE_EEEADV_1000BT 0x4
|
||
|
+#define REMOTE_EEEADV_100BT 0x2
|
||
|
+
|
||
|
+#define MIIEXT_EEE_ANEG 0x8000
|
||
|
+#define EEE_ANEG_1000M 0x4
|
||
|
+#define EEE_ANEG_100M 0x2
|
||
|
|
||
|
#endif /*_ATL1C_HW_H_*/
|
||
|
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
|
||
|
index 1ef0c92..9cc1570 100644
|
||
|
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
|
||
|
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
|
||
|
@@ -24,14 +24,6 @@
|
||
|
#define ATL1C_DRV_VERSION "1.0.1.0-NAPI"
|
||
|
char atl1c_driver_name[] = "atl1c";
|
||
|
char atl1c_driver_version[] = ATL1C_DRV_VERSION;
|
||
|
-#define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
|
||
|
-#define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
|
||
|
-#define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
|
||
|
-#define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
|
||
|
-#define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
|
||
|
-#define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
|
||
|
-#define L2CB_V10 0xc0
|
||
|
-#define L2CB_V11 0xc1
|
||
|
|
||
|
/*
|
||
|
* atl1c_pci_tbl - PCI Device ID Table
|
||
|
@@ -54,70 +46,72 @@ static DEFINE_PCI_DEVICE_TABLE(atl1c_pci_tbl) = {
|
||
|
};
|
||
|
MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
|
||
|
|
||
|
-MODULE_AUTHOR("Jie Yang <jie.yang@atheros.com>");
|
||
|
-MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
|
||
|
+MODULE_AUTHOR("Jie Yang");
|
||
|
+MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
|
||
|
+MODULE_DESCRIPTION("Qualcom Atheros 100/1000M Ethernet Network Driver");
|
||
|
MODULE_LICENSE("GPL");
|
||
|
MODULE_VERSION(ATL1C_DRV_VERSION);
|
||
|
|
||
|
static int atl1c_stop_mac(struct atl1c_hw *hw);
|
||
|
-static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
|
||
|
-static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
|
||
|
static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
|
||
|
-static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup);
|
||
|
-static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
|
||
|
-static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
|
||
|
+static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
|
||
|
+static void atl1c_start_mac(struct atl1c_adapter *adapter);
|
||
|
+static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
|
||
|
int *work_done, int work_to_do);
|
||
|
static int atl1c_up(struct atl1c_adapter *adapter);
|
||
|
static void atl1c_down(struct atl1c_adapter *adapter);
|
||
|
+static int atl1c_reset_mac(struct atl1c_hw *hw);
|
||
|
+static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter);
|
||
|
+static int atl1c_configure(struct atl1c_adapter *adapter);
|
||
|
+static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter);
|
||
|
|
||
|
static const u16 atl1c_pay_load_size[] = {
|
||
|
128, 256, 512, 1024, 2048, 4096,
|
||
|
};
|
||
|
|
||
|
-static const u16 atl1c_rfd_prod_idx_regs[AT_MAX_RECEIVE_QUEUE] =
|
||
|
-{
|
||
|
- REG_MB_RFD0_PROD_IDX,
|
||
|
- REG_MB_RFD1_PROD_IDX,
|
||
|
- REG_MB_RFD2_PROD_IDX,
|
||
|
- REG_MB_RFD3_PROD_IDX
|
||
|
-};
|
||
|
-
|
||
|
-static const u16 atl1c_rfd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
|
||
|
-{
|
||
|
- REG_RFD0_HEAD_ADDR_LO,
|
||
|
- REG_RFD1_HEAD_ADDR_LO,
|
||
|
- REG_RFD2_HEAD_ADDR_LO,
|
||
|
- REG_RFD3_HEAD_ADDR_LO
|
||
|
-};
|
||
|
-
|
||
|
-static const u16 atl1c_rrd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
|
||
|
-{
|
||
|
- REG_RRD0_HEAD_ADDR_LO,
|
||
|
- REG_RRD1_HEAD_ADDR_LO,
|
||
|
- REG_RRD2_HEAD_ADDR_LO,
|
||
|
- REG_RRD3_HEAD_ADDR_LO
|
||
|
-};
|
||
|
|
||
|
static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
|
||
|
NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
|
||
|
static void atl1c_pcie_patch(struct atl1c_hw *hw)
|
||
|
{
|
||
|
- u32 data;
|
||
|
+ u32 mst_data, data;
|
||
|
|
||
|
- AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
|
||
|
- data |= PCIE_PHYMISC_FORCE_RCV_DET;
|
||
|
- AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
|
||
|
+ /* pclk sel could switch to 25M */
|
||
|
+ AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
|
||
|
+ mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;
|
||
|
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
|
||
|
|
||
|
+ /* WoL/PCIE related settings */
|
||
|
+ if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
|
||
|
+ AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
|
||
|
+ data |= PCIE_PHYMISC_FORCE_RCV_DET;
|
||
|
+ AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
|
||
|
+ } else { /* new dev set bit5 of MASTER */
|
||
|
+ if (!(mst_data & MASTER_CTRL_WAKEN_25M))
|
||
|
+ AT_WRITE_REG(hw, REG_MASTER_CTRL,
|
||
|
+ mst_data | MASTER_CTRL_WAKEN_25M);
|
||
|
+ }
|
||
|
+ /* aspm/PCIE setting only for l2cb 1.0 */
|
||
|
if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
|
||
|
AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
|
||
|
-
|
||
|
- data &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK <<
|
||
|
- PCIE_PHYMISC2_SERDES_CDR_SHIFT);
|
||
|
- data |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
|
||
|
- data &= ~(PCIE_PHYMISC2_SERDES_TH_MASK <<
|
||
|
- PCIE_PHYMISC2_SERDES_TH_SHIFT);
|
||
|
- data |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
|
||
|
+ data = FIELD_SETX(data, PCIE_PHYMISC2_CDR_BW,
|
||
|
+ L2CB1_PCIE_PHYMISC2_CDR_BW);
|
||
|
+ data = FIELD_SETX(data, PCIE_PHYMISC2_L0S_TH,
|
||
|
+ L2CB1_PCIE_PHYMISC2_L0S_TH);
|
||
|
AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
|
||
|
+ /* extend L1 sync timer */
|
||
|
+ AT_READ_REG(hw, REG_LINK_CTRL, &data);
|
||
|
+ data |= LINK_CTRL_EXT_SYNC;
|
||
|
+ AT_WRITE_REG(hw, REG_LINK_CTRL, data);
|
||
|
+ }
|
||
|
+ /* l2cb 1.x & l1d 1.x */
|
||
|
+ if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) {
|
||
|
+ AT_READ_REG(hw, REG_PM_CTRL, &data);
|
||
|
+ data |= PM_CTRL_L0S_BUFSRX_EN;
|
||
|
+ AT_WRITE_REG(hw, REG_PM_CTRL, data);
|
||
|
+ /* clear vendor msg */
|
||
|
+ AT_READ_REG(hw, REG_DMA_DBG, &data);
|
||
|
+ AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
@@ -130,6 +124,7 @@ static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
|
||
|
u32 data;
|
||
|
u32 pci_cmd;
|
||
|
struct pci_dev *pdev = hw->adapter->pdev;
|
||
|
+ int pos;
|
||
|
|
||
|
AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
|
||
|
pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
|
||
|
@@ -142,14 +137,23 @@ static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
|
||
|
*/
|
||
|
pci_enable_wake(pdev, PCI_D3hot, 0);
|
||
|
pci_enable_wake(pdev, PCI_D3cold, 0);
|
||
|
+ /* wol sts read-clear */
|
||
|
+ AT_READ_REG(hw, REG_WOL_CTRL, &data);
|
||
|
+ AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
|
||
|
|
||
|
/*
|
||
|
* Mask some pcie error bits
|
||
|
*/
|
||
|
- AT_READ_REG(hw, REG_PCIE_UC_SEVERITY, &data);
|
||
|
- data &= ~PCIE_UC_SERVRITY_DLP;
|
||
|
- data &= ~PCIE_UC_SERVRITY_FCP;
|
||
|
- AT_WRITE_REG(hw, REG_PCIE_UC_SEVERITY, data);
|
||
|
+ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
|
||
|
+ pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
|
||
|
+ data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
|
||
|
+ pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
|
||
|
+ /* clear error status */
|
||
|
+ pci_write_config_word(pdev, pci_pcie_cap(pdev) + PCI_EXP_DEVSTA,
|
||
|
+ PCI_EXP_DEVSTA_NFED |
|
||
|
+ PCI_EXP_DEVSTA_FED |
|
||
|
+ PCI_EXP_DEVSTA_CED |
|
||
|
+ PCI_EXP_DEVSTA_URD);
|
||
|
|
||
|
AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
|
||
|
data &= ~LTSSM_ID_EN_WRO;
|
||
|
@@ -158,11 +162,6 @@ static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
|
||
|
atl1c_pcie_patch(hw);
|
||
|
if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
|
||
|
atl1c_disable_l0s_l1(hw);
|
||
|
- if (flag & ATL1C_PCIE_PHY_RESET)
|
||
|
- AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
|
||
|
- else
|
||
|
- AT_WRITE_REG(hw, REG_GPHY_CTRL,
|
||
|
- GPHY_CTRL_DEFAULT | GPHY_CTRL_EXT_RESET);
|
||
|
|
||
|
msleep(5);
|
||
|
}
|
||
|
@@ -207,14 +206,14 @@ static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
|
||
|
* atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
|
||
|
* of the idle status register until the device is actually idle
|
||
|
*/
|
||
|
-static u32 atl1c_wait_until_idle(struct atl1c_hw *hw)
|
||
|
+static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl)
|
||
|
{
|
||
|
int timeout;
|
||
|
u32 data;
|
||
|
|
||
|
for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
|
||
|
AT_READ_REG(hw, REG_IDLE_STATUS, &data);
|
||
|
- if ((data & IDLE_STATUS_MASK) == 0)
|
||
|
+ if ((data & modu_ctrl) == 0)
|
||
|
return 0;
|
||
|
msleep(1);
|
||
|
}
|
||
|
@@ -261,15 +260,16 @@ static void atl1c_check_link_status(struct atl1c_adapter *adapter)
|
||
|
|
||
|
if ((phy_data & BMSR_LSTATUS) == 0) {
|
||
|
/* link down */
|
||
|
- hw->hibernate = true;
|
||
|
- if (atl1c_stop_mac(hw) != 0)
|
||
|
- if (netif_msg_hw(adapter))
|
||
|
- dev_warn(&pdev->dev, "stop mac failed\n");
|
||
|
- atl1c_set_aspm(hw, false);
|
||
|
netif_carrier_off(netdev);
|
||
|
netif_stop_queue(netdev);
|
||
|
- atl1c_phy_reset(hw);
|
||
|
- atl1c_phy_init(&adapter->hw);
|
||
|
+ hw->hibernate = true;
|
||
|
+ if (atl1c_reset_mac(hw) != 0)
|
||
|
+ if (netif_msg_hw(adapter))
|
||
|
+ dev_warn(&pdev->dev, "reset mac failed\n");
|
||
|
+ atl1c_set_aspm(hw, SPEED_0);
|
||
|
+ atl1c_post_phy_linkchg(hw, SPEED_0);
|
||
|
+ atl1c_reset_dma_ring(adapter);
|
||
|
+ atl1c_configure(adapter);
|
||
|
} else {
|
||
|
/* Link Up */
|
||
|
hw->hibernate = false;
|
||
|
@@ -283,10 +283,9 @@ static void atl1c_check_link_status(struct atl1c_adapter *adapter)
|
||
|
adapter->link_duplex != duplex) {
|
||
|
adapter->link_speed = speed;
|
||
|
adapter->link_duplex = duplex;
|
||
|
- atl1c_set_aspm(hw, true);
|
||
|
- atl1c_enable_tx_ctrl(hw);
|
||
|
- atl1c_enable_rx_ctrl(hw);
|
||
|
- atl1c_setup_mac_ctrl(adapter);
|
||
|
+ atl1c_set_aspm(hw, speed);
|
||
|
+ atl1c_post_phy_linkchg(hw, speed);
|
||
|
+ atl1c_start_mac(adapter);
|
||
|
if (netif_msg_link(adapter))
|
||
|
dev_info(&pdev->dev,
|
||
|
"%s: %s NIC Link is Up<%d Mbps %s>\n",
|
||
|
@@ -337,6 +336,9 @@ static void atl1c_common_task(struct work_struct *work)
|
||
|
adapter = container_of(work, struct atl1c_adapter, common_task);
|
||
|
netdev = adapter->netdev;
|
||
|
|
||
|
+ if (test_bit(__AT_DOWN, &adapter->flags))
|
||
|
+ return;
|
||
|
+
|
||
|
if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
|
||
|
netif_device_detach(netdev);
|
||
|
atl1c_down(adapter);
|
||
|
@@ -345,8 +347,11 @@ static void atl1c_common_task(struct work_struct *work)
|
||
|
}
|
||
|
|
||
|
if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
|
||
|
- &adapter->work_event))
|
||
|
+ &adapter->work_event)) {
|
||
|
+ atl1c_irq_disable(adapter);
|
||
|
atl1c_check_link_status(adapter);
|
||
|
+ atl1c_irq_enable(adapter);
|
||
|
+ }
|
||
|
}
|
||
|
|
||
|
|
||
|
@@ -470,7 +475,7 @@ static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
|
||
|
memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
|
||
|
netdev->addr_assign_type &= ~NET_ADDR_RANDOM;
|
||
|
|
||
|
- atl1c_hw_set_mac_addr(&adapter->hw);
|
||
|
+ atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
@@ -523,11 +528,16 @@ static int atl1c_set_features(struct net_device *netdev,
|
||
|
static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
|
||
|
{
|
||
|
struct atl1c_adapter *adapter = netdev_priv(netdev);
|
||
|
+ struct atl1c_hw *hw = &adapter->hw;
|
||
|
int old_mtu = netdev->mtu;
|
||
|
int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
|
||
|
|
||
|
- if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
|
||
|
- (max_frame > MAX_JUMBO_FRAME_SIZE)) {
|
||
|
+ /* Fast Ethernet controller doesn't support jumbo packet */
|
||
|
+ if (((hw->nic_type == athr_l2c ||
|
||
|
+ hw->nic_type == athr_l2c_b ||
|
||
|
+ hw->nic_type == athr_l2c_b2) && new_mtu > ETH_DATA_LEN) ||
|
||
|
+ max_frame < ETH_ZLEN + ETH_FCS_LEN ||
|
||
|
+ max_frame > MAX_JUMBO_FRAME_SIZE) {
|
||
|
if (netif_msg_link(adapter))
|
||
|
dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
|
||
|
return -EINVAL;
|
||
|
@@ -543,14 +553,6 @@ static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
|
||
|
netdev_update_features(netdev);
|
||
|
atl1c_up(adapter);
|
||
|
clear_bit(__AT_RESETTING, &adapter->flags);
|
||
|
- if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
|
||
|
- u32 phy_data;
|
||
|
-
|
||
|
- AT_READ_REG(&adapter->hw, 0x1414, &phy_data);
|
||
|
- phy_data |= 0x10000000;
|
||
|
- AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
|
||
|
- }
|
||
|
-
|
||
|
}
|
||
|
return 0;
|
||
|
}
|
||
|
@@ -563,7 +565,7 @@ static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
|
||
|
struct atl1c_adapter *adapter = netdev_priv(netdev);
|
||
|
u16 result;
|
||
|
|
||
|
- atl1c_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
|
||
|
+ atl1c_read_phy_reg(&adapter->hw, reg_num, &result);
|
||
|
return result;
|
||
|
}
|
||
|
|
||
|
@@ -572,7 +574,7 @@ static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
|
||
|
{
|
||
|
struct atl1c_adapter *adapter = netdev_priv(netdev);
|
||
|
|
||
|
- atl1c_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
|
||
|
+ atl1c_write_phy_reg(&adapter->hw, reg_num, val);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
@@ -687,21 +689,15 @@ static void atl1c_set_mac_type(struct atl1c_hw *hw)
|
||
|
|
||
|
static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
|
||
|
{
|
||
|
- u32 phy_status_data;
|
||
|
u32 link_ctrl_data;
|
||
|
|
||
|
atl1c_set_mac_type(hw);
|
||
|
- AT_READ_REG(hw, REG_PHY_STATUS, &phy_status_data);
|
||
|
AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
|
||
|
|
||
|
hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
|
||
|
ATL1C_TXQ_MODE_ENHANCE;
|
||
|
- if (link_ctrl_data & LINK_CTRL_L0S_EN)
|
||
|
- hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT;
|
||
|
- if (link_ctrl_data & LINK_CTRL_L1_EN)
|
||
|
- hw->ctrl_flags |= ATL1C_ASPM_L1_SUPPORT;
|
||
|
- if (link_ctrl_data & LINK_CTRL_EXT_SYNC)
|
||
|
- hw->ctrl_flags |= ATL1C_LINK_EXT_SYNC;
|
||
|
+ hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT |
|
||
|
+ ATL1C_ASPM_L1_SUPPORT;
|
||
|
hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
|
||
|
|
||
|
if (hw->nic_type == athr_l1c ||
|
||
|
@@ -710,6 +706,55 @@ static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
|
||
|
hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
|
||
|
return 0;
|
||
|
}
|
||
|
+
|
||
|
+struct atl1c_platform_patch {
|
||
|
+ u16 pci_did;
|
||
|
+ u8 pci_revid;
|
||
|
+ u16 subsystem_vid;
|
||
|
+ u16 subsystem_did;
|
||
|
+ u32 patch_flag;
|
||
|
+#define ATL1C_LINK_PATCH 0x1
|
||
|
+};
|
||
|
+static const struct atl1c_platform_patch plats[] __devinitdata = {
|
||
|
+{0x2060, 0xC1, 0x1019, 0x8152, 0x1},
|
||
|
+{0x2060, 0xC1, 0x1019, 0x2060, 0x1},
|
||
|
+{0x2060, 0xC1, 0x1019, 0xE000, 0x1},
|
||
|
+{0x2062, 0xC0, 0x1019, 0x8152, 0x1},
|
||
|
+{0x2062, 0xC0, 0x1019, 0x2062, 0x1},
|
||
|
+{0x2062, 0xC0, 0x1458, 0xE000, 0x1},
|
||
|
+{0x2062, 0xC1, 0x1019, 0x8152, 0x1},
|
||
|
+{0x2062, 0xC1, 0x1019, 0x2062, 0x1},
|
||
|
+{0x2062, 0xC1, 0x1458, 0xE000, 0x1},
|
||
|
+{0x2062, 0xC1, 0x1565, 0x2802, 0x1},
|
||
|
+{0x2062, 0xC1, 0x1565, 0x2801, 0x1},
|
||
|
+{0x1073, 0xC0, 0x1019, 0x8151, 0x1},
|
||
|
+{0x1073, 0xC0, 0x1019, 0x1073, 0x1},
|
||
|
+{0x1073, 0xC0, 0x1458, 0xE000, 0x1},
|
||
|
+{0x1083, 0xC0, 0x1458, 0xE000, 0x1},
|
||
|
+{0x1083, 0xC0, 0x1019, 0x8151, 0x1},
|
||
|
+{0x1083, 0xC0, 0x1019, 0x1083, 0x1},
|
||
|
+{0x1083, 0xC0, 0x1462, 0x7680, 0x1},
|
||
|
+{0x1083, 0xC0, 0x1565, 0x2803, 0x1},
|
||
|
+{0},
|
||
|
+};
|
||
|
+
|
||
|
+static void __devinit atl1c_patch_assign(struct atl1c_hw *hw)
|
||
|
+{
|
||
|
+ int i = 0;
|
||
|
+
|
||
|
+ hw->msi_lnkpatch = false;
|
||
|
+
|
||
|
+ while (plats[i].pci_did != 0) {
|
||
|
+ if (plats[i].pci_did == hw->device_id &&
|
||
|
+ plats[i].pci_revid == hw->revision_id &&
|
||
|
+ plats[i].subsystem_vid == hw->subsystem_vendor_id &&
|
||
|
+ plats[i].subsystem_did == hw->subsystem_id) {
|
||
|
+ if (plats[i].patch_flag & ATL1C_LINK_PATCH)
|
||
|
+ hw->msi_lnkpatch = true;
|
||
|
+ }
|
||
|
+ i++;
|
||
|
+ }
|
||
|
+}
|
||
|
/*
|
||
|
* atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
|
||
|
* @adapter: board private structure to initialize
|
||
|
@@ -729,9 +774,8 @@ static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
|
||
|
device_set_wakeup_enable(&pdev->dev, false);
|
||
|
adapter->link_speed = SPEED_0;
|
||
|
adapter->link_duplex = FULL_DUPLEX;
|
||
|
- adapter->num_rx_queues = AT_DEF_RECEIVE_QUEUE;
|
||
|
adapter->tpd_ring[0].count = 1024;
|
||
|
- adapter->rfd_ring[0].count = 512;
|
||
|
+ adapter->rfd_ring.count = 512;
|
||
|
|
||
|
hw->vendor_id = pdev->vendor;
|
||
|
hw->device_id = pdev->device;
|
||
|
@@ -746,26 +790,18 @@ static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
|
||
|
dev_err(&pdev->dev, "set mac function pointers failed\n");
|
||
|
return -1;
|
||
|
}
|
||
|
+ atl1c_patch_assign(hw);
|
||
|
+
|
||
|
hw->intr_mask = IMR_NORMAL_MASK;
|
||
|
hw->phy_configured = false;
|
||
|
hw->preamble_len = 7;
|
||
|
hw->max_frame_size = adapter->netdev->mtu;
|
||
|
- if (adapter->num_rx_queues < 2) {
|
||
|
- hw->rss_type = atl1c_rss_disable;
|
||
|
- hw->rss_mode = atl1c_rss_mode_disable;
|
||
|
- } else {
|
||
|
- hw->rss_type = atl1c_rss_ipv4;
|
||
|
- hw->rss_mode = atl1c_rss_mul_que_mul_int;
|
||
|
- hw->rss_hash_bits = 16;
|
||
|
- }
|
||
|
hw->autoneg_advertised = ADVERTISED_Autoneg;
|
||
|
hw->indirect_tab = 0xE4E4E4E4;
|
||
|
hw->base_cpu = 0;
|
||
|
|
||
|
hw->ict = 50000; /* 100ms */
|
||
|
hw->smb_timer = 200000; /* 400ms */
|
||
|
- hw->cmb_tpd = 4;
|
||
|
- hw->cmb_tx_timer = 1; /* 2 us */
|
||
|
hw->rx_imt = 200;
|
||
|
hw->tx_imt = 1000;
|
||
|
|
||
|
@@ -773,9 +809,6 @@ static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
|
||
|
hw->rfd_burst = 8;
|
||
|
hw->dma_order = atl1c_dma_ord_out;
|
||
|
hw->dmar_block = atl1c_dma_req_1024;
|
||
|
- hw->dmaw_block = atl1c_dma_req_1024;
|
||
|
- hw->dmar_dly_cnt = 15;
|
||
|
- hw->dmaw_dly_cnt = 4;
|
||
|
|
||
|
if (atl1c_alloc_queues(adapter)) {
|
||
|
dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
|
||
|
@@ -851,24 +884,22 @@ static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
|
||
|
*/
|
||
|
static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
|
||
|
{
|
||
|
- struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
|
||
|
- struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
|
||
|
+ struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
|
||
|
+ struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
|
||
|
struct atl1c_buffer *buffer_info;
|
||
|
struct pci_dev *pdev = adapter->pdev;
|
||
|
- int i, j;
|
||
|
+ int j;
|
||
|
|
||
|
- for (i = 0; i < adapter->num_rx_queues; i++) {
|
||
|
- for (j = 0; j < rfd_ring[i].count; j++) {
|
||
|
- buffer_info = &rfd_ring[i].buffer_info[j];
|
||
|
- atl1c_clean_buffer(pdev, buffer_info, 0);
|
||
|
- }
|
||
|
- /* zero out the descriptor ring */
|
||
|
- memset(rfd_ring[i].desc, 0, rfd_ring[i].size);
|
||
|
- rfd_ring[i].next_to_clean = 0;
|
||
|
- rfd_ring[i].next_to_use = 0;
|
||
|
- rrd_ring[i].next_to_use = 0;
|
||
|
- rrd_ring[i].next_to_clean = 0;
|
||
|
+ for (j = 0; j < rfd_ring->count; j++) {
|
||
|
+ buffer_info = &rfd_ring->buffer_info[j];
|
||
|
+ atl1c_clean_buffer(pdev, buffer_info, 0);
|
||
|
}
|
||
|
+ /* zero out the descriptor ring */
|
||
|
+ memset(rfd_ring->desc, 0, rfd_ring->size);
|
||
|
+ rfd_ring->next_to_clean = 0;
|
||
|
+ rfd_ring->next_to_use = 0;
|
||
|
+ rrd_ring->next_to_use = 0;
|
||
|
+ rrd_ring->next_to_clean = 0;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
@@ -877,8 +908,8 @@ static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
|
||
|
static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
|
||
|
{
|
||
|
struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
|
||
|
- struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
|
||
|
- struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
|
||
|
+ struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
|
||
|
+ struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
|
||
|
struct atl1c_buffer *buffer_info;
|
||
|
int i, j;
|
||
|
|
||
|
@@ -890,15 +921,13 @@ static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
|
||
|
ATL1C_SET_BUFFER_STATE(&buffer_info[i],
|
||
|
ATL1C_BUFFER_FREE);
|
||
|
}
|
||
|
- for (i = 0; i < adapter->num_rx_queues; i++) {
|
||
|
- rfd_ring[i].next_to_use = 0;
|
||
|
- rfd_ring[i].next_to_clean = 0;
|
||
|
- rrd_ring[i].next_to_use = 0;
|
||
|
- rrd_ring[i].next_to_clean = 0;
|
||
|
- for (j = 0; j < rfd_ring[i].count; j++) {
|
||
|
- buffer_info = &rfd_ring[i].buffer_info[j];
|
||
|
- ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
|
||
|
- }
|
||
|
+ rfd_ring->next_to_use = 0;
|
||
|
+ rfd_ring->next_to_clean = 0;
|
||
|
+ rrd_ring->next_to_use = 0;
|
||
|
+ rrd_ring->next_to_clean = 0;
|
||
|
+ for (j = 0; j < rfd_ring->count; j++) {
|
||
|
+ buffer_info = &rfd_ring->buffer_info[j];
|
||
|
+ ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
@@ -935,27 +964,23 @@ static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
|
||
|
{
|
||
|
struct pci_dev *pdev = adapter->pdev;
|
||
|
struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
|
||
|
- struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
|
||
|
- struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
|
||
|
+ struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
|
||
|
+ struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
|
||
|
struct atl1c_ring_header *ring_header = &adapter->ring_header;
|
||
|
- int num_rx_queues = adapter->num_rx_queues;
|
||
|
int size;
|
||
|
int i;
|
||
|
int count = 0;
|
||
|
int rx_desc_count = 0;
|
||
|
u32 offset = 0;
|
||
|
|
||
|
- rrd_ring[0].count = rfd_ring[0].count;
|
||
|
+ rrd_ring->count = rfd_ring->count;
|
||
|
for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
|
||
|
tpd_ring[i].count = tpd_ring[0].count;
|
||
|
|
||
|
- for (i = 1; i < adapter->num_rx_queues; i++)
|
||
|
- rfd_ring[i].count = rrd_ring[i].count = rfd_ring[0].count;
|
||
|
-
|
||
|
/* 2 tpd queue, one high priority queue,
|
||
|
* another normal priority queue */
|
||
|
size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
|
||
|
- rfd_ring->count * num_rx_queues);
|
||
|
+ rfd_ring->count);
|
||
|
tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
|
||
|
if (unlikely(!tpd_ring->buffer_info)) {
|
||
|
dev_err(&pdev->dev, "kzalloc failed, size = %d\n",
|
||
|
@@ -968,12 +993,11 @@ static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
|
||
|
count += tpd_ring[i].count;
|
||
|
}
|
||
|
|
||
|
- for (i = 0; i < num_rx_queues; i++) {
|
||
|
- rfd_ring[i].buffer_info =
|
||
|
- (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
|
||
|
- count += rfd_ring[i].count;
|
||
|
- rx_desc_count += rfd_ring[i].count;
|
||
|
- }
|
||
|
+ rfd_ring->buffer_info =
|
||
|
+ (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
|
||
|
+ count += rfd_ring->count;
|
||
|
+ rx_desc_count += rfd_ring->count;
|
||
|
+
|
||
|
/*
|
||
|
* real ring DMA buffer
|
||
|
* each ring/block may need up to 8 bytes for alignment, hence the
|
||
|
@@ -983,8 +1007,7 @@ static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
|
||
|
sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
|
||
|
sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
|
||
|
sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
|
||
|
- sizeof(struct atl1c_hw_stats) +
|
||
|
- 8 * 4 + 8 * 2 * num_rx_queues;
|
||
|
+ 8 * 4;
|
||
|
|
||
|
ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
|
||
|
&ring_header->dma);
|
||
|
@@ -1005,25 +1028,18 @@ static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
|
||
|
offset += roundup(tpd_ring[i].size, 8);
|
||
|
}
|
||
|
/* init RFD ring */
|
||
|
- for (i = 0; i < num_rx_queues; i++) {
|
||
|
- rfd_ring[i].dma = ring_header->dma + offset;
|
||
|
- rfd_ring[i].desc = (u8 *) ring_header->desc + offset;
|
||
|
- rfd_ring[i].size = sizeof(struct atl1c_rx_free_desc) *
|
||
|
- rfd_ring[i].count;
|
||
|
- offset += roundup(rfd_ring[i].size, 8);
|
||
|
- }
|
||
|
+ rfd_ring->dma = ring_header->dma + offset;
|
||
|
+ rfd_ring->desc = (u8 *) ring_header->desc + offset;
|
||
|
+ rfd_ring->size = sizeof(struct atl1c_rx_free_desc) * rfd_ring->count;
|
||
|
+ offset += roundup(rfd_ring->size, 8);
|
||
|
|
||
|
/* init RRD ring */
|
||
|
- for (i = 0; i < num_rx_queues; i++) {
|
||
|
- rrd_ring[i].dma = ring_header->dma + offset;
|
||
|
- rrd_ring[i].desc = (u8 *) ring_header->desc + offset;
|
||
|
- rrd_ring[i].size = sizeof(struct atl1c_recv_ret_status) *
|
||
|
- rrd_ring[i].count;
|
||
|
- offset += roundup(rrd_ring[i].size, 8);
|
||
|
- }
|
||
|
+ rrd_ring->dma = ring_header->dma + offset;
|
||
|
+ rrd_ring->desc = (u8 *) ring_header->desc + offset;
|
||
|
+ rrd_ring->size = sizeof(struct atl1c_recv_ret_status) *
|
||
|
+ rrd_ring->count;
|
||
|
+ offset += roundup(rrd_ring->size, 8);
|
||
|
|
||
|
- adapter->smb.dma = ring_header->dma + offset;
|
||
|
- adapter->smb.smb = (u8 *)ring_header->desc + offset;
|
||
|
return 0;
|
||
|
|
||
|
err_nomem:
|
||
|
@@ -1034,26 +1050,20 @@ err_nomem:
|
||
|
static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
|
||
|
{
|
||
|
struct atl1c_hw *hw = &adapter->hw;
|
||
|
- struct atl1c_rfd_ring *rfd_ring = (struct atl1c_rfd_ring *)
|
||
|
- adapter->rfd_ring;
|
||
|
- struct atl1c_rrd_ring *rrd_ring = (struct atl1c_rrd_ring *)
|
||
|
- adapter->rrd_ring;
|
||
|
+ struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
|
||
|
+ struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
|
||
|
struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
|
||
|
adapter->tpd_ring;
|
||
|
- struct atl1c_cmb *cmb = (struct atl1c_cmb *) &adapter->cmb;
|
||
|
- struct atl1c_smb *smb = (struct atl1c_smb *) &adapter->smb;
|
||
|
- int i;
|
||
|
- u32 data;
|
||
|
|
||
|
/* TPD */
|
||
|
AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
|
||
|
(u32)((tpd_ring[atl1c_trans_normal].dma &
|
||
|
AT_DMA_HI_ADDR_MASK) >> 32));
|
||
|
/* just enable normal priority TX queue */
|
||
|
- AT_WRITE_REG(hw, REG_NTPD_HEAD_ADDR_LO,
|
||
|
+ AT_WRITE_REG(hw, REG_TPD_PRI0_ADDR_LO,
|
||
|
(u32)(tpd_ring[atl1c_trans_normal].dma &
|
||
|
AT_DMA_LO_ADDR_MASK));
|
||
|
- AT_WRITE_REG(hw, REG_HTPD_HEAD_ADDR_LO,
|
||
|
+ AT_WRITE_REG(hw, REG_TPD_PRI1_ADDR_LO,
|
||
|
(u32)(tpd_ring[atl1c_trans_high].dma &
|
||
|
AT_DMA_LO_ADDR_MASK));
|
||
|
AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
|
||
|
@@ -1062,31 +1072,21 @@ static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
|
||
|
|
||
|
/* RFD */
|
||
|
AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
|
||
|
- (u32)((rfd_ring[0].dma & AT_DMA_HI_ADDR_MASK) >> 32));
|
||
|
- for (i = 0; i < adapter->num_rx_queues; i++)
|
||
|
- AT_WRITE_REG(hw, atl1c_rfd_addr_lo_regs[i],
|
||
|
- (u32)(rfd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
|
||
|
+ (u32)((rfd_ring->dma & AT_DMA_HI_ADDR_MASK) >> 32));
|
||
|
+ AT_WRITE_REG(hw, REG_RFD0_HEAD_ADDR_LO,
|
||
|
+ (u32)(rfd_ring->dma & AT_DMA_LO_ADDR_MASK));
|
||
|
|
||
|
AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
|
||
|
- rfd_ring[0].count & RFD_RING_SIZE_MASK);
|
||
|
+ rfd_ring->count & RFD_RING_SIZE_MASK);
|
||
|
AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
|
||
|
adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
|
||
|
|
||
|
/* RRD */
|
||
|
- for (i = 0; i < adapter->num_rx_queues; i++)
|
||
|
- AT_WRITE_REG(hw, atl1c_rrd_addr_lo_regs[i],
|
||
|
- (u32)(rrd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
|
||
|
+ AT_WRITE_REG(hw, REG_RRD0_HEAD_ADDR_LO,
|
||
|
+ (u32)(rrd_ring->dma & AT_DMA_LO_ADDR_MASK));
|
||
|
AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
|
||
|
- (rrd_ring[0].count & RRD_RING_SIZE_MASK));
|
||
|
+ (rrd_ring->count & RRD_RING_SIZE_MASK));
|
||
|
|
||
|
- /* CMB */
|
||
|
- AT_WRITE_REG(hw, REG_CMB_BASE_ADDR_LO, cmb->dma & AT_DMA_LO_ADDR_MASK);
|
||
|
-
|
||
|
- /* SMB */
|
||
|
- AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_HI,
|
||
|
- (u32)((smb->dma & AT_DMA_HI_ADDR_MASK) >> 32));
|
||
|
- AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_LO,
|
||
|
- (u32)(smb->dma & AT_DMA_LO_ADDR_MASK));
|
||
|
if (hw->nic_type == athr_l2c_b) {
|
||
|
AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
|
||
|
AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
|
||
|
@@ -1097,13 +1097,6 @@ static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
|
||
|
AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
|
||
|
AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
|
||
|
}
|
||
|
- if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d_2) {
|
||
|
- /* Power Saving for L2c_B */
|
||
|
- AT_READ_REG(hw, REG_SERDES_LOCK, &data);
|
||
|
- data |= SERDES_MAC_CLK_SLOWDOWN;
|
||
|
- data |= SERDES_PYH_CLK_SLOWDOWN;
|
||
|
- AT_WRITE_REG(hw, REG_SERDES_LOCK, data);
|
||
|
- }
|
||
|
/* Load all of base address above */
|
||
|
AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
|
||
|
}
|
||
|
@@ -1111,32 +1104,26 @@ static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
|
||
|
static void atl1c_configure_tx(struct atl1c_adapter *adapter)
|
||
|
{
|
||
|
struct atl1c_hw *hw = &adapter->hw;
|
||
|
- u32 dev_ctrl_data;
|
||
|
- u32 max_pay_load;
|
||
|
+ int max_pay_load;
|
||
|
u16 tx_offload_thresh;
|
||
|
u32 txq_ctrl_data;
|
||
|
- u32 max_pay_load_data;
|
||
|
|
||
|
- tx_offload_thresh = MAX_TX_OFFLOAD_THRESH;
|
||
|
+ tx_offload_thresh = MAX_TSO_FRAME_SIZE;
|
||
|
AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
|
||
|
(tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
|
||
|
- AT_READ_REG(hw, REG_DEVICE_CTRL, &dev_ctrl_data);
|
||
|
- max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT) &
|
||
|
- DEVICE_CTRL_MAX_PAYLOAD_MASK;
|
||
|
- hw->dmaw_block = min_t(u32, max_pay_load, hw->dmaw_block);
|
||
|
- max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT) &
|
||
|
- DEVICE_CTRL_MAX_RREQ_SZ_MASK;
|
||
|
+ max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
|
||
|
hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
|
||
|
-
|
||
|
- txq_ctrl_data = (hw->tpd_burst & TXQ_NUM_TPD_BURST_MASK) <<
|
||
|
- TXQ_NUM_TPD_BURST_SHIFT;
|
||
|
- if (hw->ctrl_flags & ATL1C_TXQ_MODE_ENHANCE)
|
||
|
- txq_ctrl_data |= TXQ_CTRL_ENH_MODE;
|
||
|
- max_pay_load_data = (atl1c_pay_load_size[hw->dmar_block] &
|
||
|
- TXQ_TXF_BURST_NUM_MASK) << TXQ_TXF_BURST_NUM_SHIFT;
|
||
|
- if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2)
|
||
|
- max_pay_load_data >>= 1;
|
||
|
- txq_ctrl_data |= max_pay_load_data;
|
||
|
+ /*
|
||
|
+ * if BIOS had changed the dam-read-max-length to an invalid value,
|
||
|
+ * restore it to default value
|
||
|
+ */
|
||
|
+ if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
|
||
|
+ pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
|
||
|
+ hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
|
||
|
+ }
|
||
|
+ txq_ctrl_data =
|
||
|
+ hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
|
||
|
+ L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
|
||
|
|
||
|
AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
|
||
|
}
|
||
|
@@ -1151,34 +1138,13 @@ static void atl1c_configure_rx(struct atl1c_adapter *adapter)
|
||
|
|
||
|
if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
|
||
|
rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
|
||
|
- if (hw->rss_type == atl1c_rss_ipv4)
|
||
|
- rxq_ctrl_data |= RSS_HASH_IPV4;
|
||
|
- if (hw->rss_type == atl1c_rss_ipv4_tcp)
|
||
|
- rxq_ctrl_data |= RSS_HASH_IPV4_TCP;
|
||
|
- if (hw->rss_type == atl1c_rss_ipv6)
|
||
|
- rxq_ctrl_data |= RSS_HASH_IPV6;
|
||
|
- if (hw->rss_type == atl1c_rss_ipv6_tcp)
|
||
|
- rxq_ctrl_data |= RSS_HASH_IPV6_TCP;
|
||
|
- if (hw->rss_type != atl1c_rss_disable)
|
||
|
- rxq_ctrl_data |= RRS_HASH_CTRL_EN;
|
||
|
-
|
||
|
- rxq_ctrl_data |= (hw->rss_mode & RSS_MODE_MASK) <<
|
||
|
- RSS_MODE_SHIFT;
|
||
|
- rxq_ctrl_data |= (hw->rss_hash_bits & RSS_HASH_BITS_MASK) <<
|
||
|
- RSS_HASH_BITS_SHIFT;
|
||
|
- if (hw->ctrl_flags & ATL1C_ASPM_CTRL_MON)
|
||
|
- rxq_ctrl_data |= (ASPM_THRUPUT_LIMIT_1M &
|
||
|
- ASPM_THRUPUT_LIMIT_MASK) << ASPM_THRUPUT_LIMIT_SHIFT;
|
||
|
|
||
|
- AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
|
||
|
-}
|
||
|
-
|
||
|
-static void atl1c_configure_rss(struct atl1c_adapter *adapter)
|
||
|
-{
|
||
|
- struct atl1c_hw *hw = &adapter->hw;
|
||
|
+ /* aspm for gigabit */
|
||
|
+ if (hw->nic_type != athr_l1d_2 && (hw->device_id & 1) != 0)
|
||
|
+ rxq_ctrl_data = FIELD_SETX(rxq_ctrl_data, ASPM_THRUPUT_LIMIT,
|
||
|
+ ASPM_THRUPUT_LIMIT_100M);
|
||
|
|
||
|
- AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
|
||
|
- AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
|
||
|
+ AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
|
||
|
}
|
||
|
|
||
|
static void atl1c_configure_dma(struct atl1c_adapter *adapter)
|
||
|
@@ -1186,36 +1152,11 @@ static void atl1c_configure_dma(struct atl1c_adapter *adapter)
|
||
|
struct atl1c_hw *hw = &adapter->hw;
|
||
|
u32 dma_ctrl_data;
|
||
|
|
||
|
- dma_ctrl_data = DMA_CTRL_DMAR_REQ_PRI;
|
||
|
- if (hw->ctrl_flags & ATL1C_CMB_ENABLE)
|
||
|
- dma_ctrl_data |= DMA_CTRL_CMB_EN;
|
||
|
- if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
|
||
|
- dma_ctrl_data |= DMA_CTRL_SMB_EN;
|
||
|
- else
|
||
|
- dma_ctrl_data |= MAC_CTRL_SMB_DIS;
|
||
|
-
|
||
|
- switch (hw->dma_order) {
|
||
|
- case atl1c_dma_ord_in:
|
||
|
- dma_ctrl_data |= DMA_CTRL_DMAR_IN_ORDER;
|
||
|
- break;
|
||
|
- case atl1c_dma_ord_enh:
|
||
|
- dma_ctrl_data |= DMA_CTRL_DMAR_ENH_ORDER;
|
||
|
- break;
|
||
|
- case atl1c_dma_ord_out:
|
||
|
- dma_ctrl_data |= DMA_CTRL_DMAR_OUT_ORDER;
|
||
|
- break;
|
||
|
- default:
|
||
|
- break;
|
||
|
- }
|
||
|
-
|
||
|
- dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
|
||
|
- << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
|
||
|
- dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
|
||
|
- << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
|
||
|
- dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
|
||
|
- << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
|
||
|
- dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
|
||
|
- << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
|
||
|
+ dma_ctrl_data = FIELDX(DMA_CTRL_RORDER_MODE, DMA_CTRL_RORDER_MODE_OUT) |
|
||
|
+ DMA_CTRL_RREQ_PRI_DATA |
|
||
|
+ FIELDX(DMA_CTRL_RREQ_BLEN, hw->dmar_block) |
|
||
|
+ FIELDX(DMA_CTRL_WDLY_CNT, DMA_CTRL_WDLY_CNT_DEF) |
|
||
|
+ FIELDX(DMA_CTRL_RDLY_CNT, DMA_CTRL_RDLY_CNT_DEF);
|
||
|
|
||
|
AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
|
||
|
}
|
||
|
@@ -1230,52 +1171,53 @@ static int atl1c_stop_mac(struct atl1c_hw *hw)
|
||
|
u32 data;
|
||
|
|
||
|
AT_READ_REG(hw, REG_RXQ_CTRL, &data);
|
||
|
- data &= ~(RXQ1_CTRL_EN | RXQ2_CTRL_EN |
|
||
|
- RXQ3_CTRL_EN | RXQ_CTRL_EN);
|
||
|
+ data &= ~RXQ_CTRL_EN;
|
||
|
AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
|
||
|
|
||
|
AT_READ_REG(hw, REG_TXQ_CTRL, &data);
|
||
|
data &= ~TXQ_CTRL_EN;
|
||
|
- AT_WRITE_REG(hw, REG_TWSI_CTRL, data);
|
||
|
+ AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
|
||
|
|
||
|
- atl1c_wait_until_idle(hw);
|
||
|
+ atl1c_wait_until_idle(hw, IDLE_STATUS_RXQ_BUSY | IDLE_STATUS_TXQ_BUSY);
|
||
|
|
||
|
AT_READ_REG(hw, REG_MAC_CTRL, &data);
|
||
|
data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
|
||
|
AT_WRITE_REG(hw, REG_MAC_CTRL, data);
|
||
|
|
||
|
- return (int)atl1c_wait_until_idle(hw);
|
||
|
-}
|
||
|
-
|
||
|
-static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw)
|
||
|
-{
|
||
|
- u32 data;
|
||
|
-
|
||
|
- AT_READ_REG(hw, REG_RXQ_CTRL, &data);
|
||
|
- switch (hw->adapter->num_rx_queues) {
|
||
|
- case 4:
|
||
|
- data |= (RXQ3_CTRL_EN | RXQ2_CTRL_EN | RXQ1_CTRL_EN);
|
||
|
- break;
|
||
|
- case 3:
|
||
|
- data |= (RXQ2_CTRL_EN | RXQ1_CTRL_EN);
|
||
|
- break;
|
||
|
- case 2:
|
||
|
- data |= RXQ1_CTRL_EN;
|
||
|
- break;
|
||
|
- default:
|
||
|
- break;
|
||
|
- }
|
||
|
- data |= RXQ_CTRL_EN;
|
||
|
- AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
|
||
|
+ return (int)atl1c_wait_until_idle(hw,
|
||
|
+ IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
|
||
|
}
|
||
|
|
||
|
-static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw)
|
||
|
+static void atl1c_start_mac(struct atl1c_adapter *adapter)
|
||
|
{
|
||
|
- u32 data;
|
||
|
+ struct atl1c_hw *hw = &adapter->hw;
|
||
|
+ u32 mac, txq, rxq;
|
||
|
+
|
||
|
+ hw->mac_duplex = adapter->link_duplex == FULL_DUPLEX ? true : false;
|
||
|
+ hw->mac_speed = adapter->link_speed == SPEED_1000 ?
|
||
|
+ atl1c_mac_speed_1000 : atl1c_mac_speed_10_100;
|
||
|
+
|
||
|
+ AT_READ_REG(hw, REG_TXQ_CTRL, &txq);
|
||
|
+ AT_READ_REG(hw, REG_RXQ_CTRL, &rxq);
|
||
|
+ AT_READ_REG(hw, REG_MAC_CTRL, &mac);
|
||
|
+
|
||
|
+ txq |= TXQ_CTRL_EN;
|
||
|
+ rxq |= RXQ_CTRL_EN;
|
||
|
+ mac |= MAC_CTRL_TX_EN | MAC_CTRL_TX_FLOW |
|
||
|
+ MAC_CTRL_RX_EN | MAC_CTRL_RX_FLOW |
|
||
|
+ MAC_CTRL_ADD_CRC | MAC_CTRL_PAD |
|
||
|
+ MAC_CTRL_BC_EN | MAC_CTRL_SINGLE_PAUSE_EN |
|
||
|
+ MAC_CTRL_HASH_ALG_CRC32;
|
||
|
+ if (hw->mac_duplex)
|
||
|
+ mac |= MAC_CTRL_DUPLX;
|
||
|
+ else
|
||
|
+ mac &= ~MAC_CTRL_DUPLX;
|
||
|
+ mac = FIELD_SETX(mac, MAC_CTRL_SPEED, hw->mac_speed);
|
||
|
+ mac = FIELD_SETX(mac, MAC_CTRL_PRMLEN, hw->preamble_len);
|
||
|
|
||
|
- AT_READ_REG(hw, REG_TXQ_CTRL, &data);
|
||
|
- data |= TXQ_CTRL_EN;
|
||
|
- AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
|
||
|
+ AT_WRITE_REG(hw, REG_TXQ_CTRL, txq);
|
||
|
+ AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq);
|
||
|
+ AT_WRITE_REG(hw, REG_MAC_CTRL, mac);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
@@ -1287,10 +1229,7 @@ static int atl1c_reset_mac(struct atl1c_hw *hw)
|
||
|
{
|
||
|
struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
|
||
|
struct pci_dev *pdev = adapter->pdev;
|
||
|
- u32 master_ctrl_data = 0;
|
||
|
-
|
||
|
- AT_WRITE_REG(hw, REG_IMR, 0);
|
||
|
- AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
|
||
|
+ u32 ctrl_data = 0;
|
||
|
|
||
|
atl1c_stop_mac(hw);
|
||
|
/*
|
||
|
@@ -1299,194 +1238,148 @@ static int atl1c_reset_mac(struct atl1c_hw *hw)
|
||
|
* the current PCI configuration. The global reset bit is self-
|
||
|
* clearing, and should clear within a microsecond.
|
||
|
*/
|
||
|
- AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
|
||
|
- master_ctrl_data |= MASTER_CTRL_OOB_DIS_OFF;
|
||
|
- AT_WRITE_REGW(hw, REG_MASTER_CTRL, ((master_ctrl_data | MASTER_CTRL_SOFT_RST)
|
||
|
- & 0xFFFF));
|
||
|
+ AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
|
||
|
+ ctrl_data |= MASTER_CTRL_OOB_DIS;
|
||
|
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
|
||
|
|
||
|
AT_WRITE_FLUSH(hw);
|
||
|
msleep(10);
|
||
|
/* Wait at least 10ms for All module to be Idle */
|
||
|
|
||
|
- if (atl1c_wait_until_idle(hw)) {
|
||
|
+ if (atl1c_wait_until_idle(hw, IDLE_STATUS_MASK)) {
|
||
|
dev_err(&pdev->dev,
|
||
|
"MAC state machine can't be idle since"
|
||
|
" disabled for 10ms second\n");
|
||
|
return -1;
|
||
|
}
|
||
|
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
|
||
|
+
|
||
|
+ /* driver control speed/duplex */
|
||
|
+ AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
|
||
|
+ AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
|
||
|
+
|
||
|
+ /* clk switch setting */
|
||
|
+ AT_READ_REG(hw, REG_SERDES, &ctrl_data);
|
||
|
+ switch (hw->nic_type) {
|
||
|
+ case athr_l2c_b:
|
||
|
+ ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
|
||
|
+ SERDES_MAC_CLK_SLOWDOWN);
|
||
|
+ AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
|
||
|
+ break;
|
||
|
+ case athr_l2c_b2:
|
||
|
+ case athr_l1d_2:
|
||
|
+ ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
|
||
|
+ AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
|
||
|
+ break;
|
||
|
+ default:
|
||
|
+ break;
|
||
|
+ }
|
||
|
+
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
|
||
|
{
|
||
|
- u32 pm_ctrl_data;
|
||
|
+ u16 ctrl_flags = hw->ctrl_flags;
|
||
|
|
||
|
- AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
|
||
|
- pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
|
||
|
- PM_CTRL_L1_ENTRY_TIMER_SHIFT);
|
||
|
- pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_MAC_ASPM_CHK;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
|
||
|
-
|
||
|
- pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
|
||
|
- pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
|
||
|
- pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
|
||
|
- AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
|
||
|
+ hw->ctrl_flags &= ~(ATL1C_ASPM_L0S_SUPPORT | ATL1C_ASPM_L1_SUPPORT);
|
||
|
+ atl1c_set_aspm(hw, SPEED_0);
|
||
|
+ hw->ctrl_flags = ctrl_flags;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Set ASPM state.
|
||
|
* Enable/disable L0s/L1 depend on link state.
|
||
|
*/
|
||
|
-static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup)
|
||
|
+static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
|
||
|
{
|
||
|
u32 pm_ctrl_data;
|
||
|
- u32 link_ctrl_data;
|
||
|
- u32 link_l1_timer = 0xF;
|
||
|
+ u32 link_l1_timer;
|
||
|
|
||
|
AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
|
||
|
- AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
|
||
|
+ pm_ctrl_data &= ~(PM_CTRL_ASPM_L1_EN |
|
||
|
+ PM_CTRL_ASPM_L0S_EN |
|
||
|
+ PM_CTRL_MAC_ASPM_CHK);
|
||
|
+ /* L1 timer */
|
||
|
+ if (hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
|
||
|
+ pm_ctrl_data &= ~PMCTRL_TXL1_AFTER_L0S;
|
||
|
+ link_l1_timer =
|
||
|
+ link_speed == SPEED_1000 || link_speed == SPEED_100 ?
|
||
|
+ L1D_PMCTRL_L1_ENTRY_TM_16US : 1;
|
||
|
+ pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
|
||
|
+ L1D_PMCTRL_L1_ENTRY_TM, link_l1_timer);
|
||
|
+ } else {
|
||
|
+ link_l1_timer = hw->nic_type == athr_l2c_b ?
|
||
|
+ L2CB1_PM_CTRL_L1_ENTRY_TM : L1C_PM_CTRL_L1_ENTRY_TM;
|
||
|
+ if (link_speed != SPEED_1000 && link_speed != SPEED_100)
|
||
|
+ link_l1_timer = 1;
|
||
|
+ pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
|
||
|
+ PM_CTRL_L1_ENTRY_TIMER, link_l1_timer);
|
||
|
+ }
|
||
|
|
||
|
- pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
|
||
|
- pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
|
||
|
- PM_CTRL_L1_ENTRY_TIMER_SHIFT);
|
||
|
- pm_ctrl_data &= ~(PM_CTRL_LCKDET_TIMER_MASK <<
|
||
|
- PM_CTRL_LCKDET_TIMER_SHIFT);
|
||
|
- pm_ctrl_data |= AT_LCKDET_TIMER << PM_CTRL_LCKDET_TIMER_SHIFT;
|
||
|
+ /* L0S/L1 enable */
|
||
|
+ if ((hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT) && link_speed != SPEED_0)
|
||
|
+ pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
|
||
|
+ if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
|
||
|
+ pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
|
||
|
|
||
|
+ /* l2cb & l1d & l2cb2 & l1d2 */
|
||
|
if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
|
||
|
- hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
|
||
|
- link_ctrl_data &= ~LINK_CTRL_EXT_SYNC;
|
||
|
- if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE)) {
|
||
|
- if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10)
|
||
|
- link_ctrl_data |= LINK_CTRL_EXT_SYNC;
|
||
|
- }
|
||
|
-
|
||
|
- AT_WRITE_REG(hw, REG_LINK_CTRL, link_ctrl_data);
|
||
|
-
|
||
|
- pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER;
|
||
|
- pm_ctrl_data &= ~(PM_CTRL_PM_REQ_TIMER_MASK <<
|
||
|
- PM_CTRL_PM_REQ_TIMER_SHIFT);
|
||
|
- pm_ctrl_data |= AT_ASPM_L1_TIMER <<
|
||
|
- PM_CTRL_PM_REQ_TIMER_SHIFT;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_SA_DLY_EN;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_HOTRST;
|
||
|
- pm_ctrl_data |= 1 << PM_CTRL_L1_ENTRY_TIMER_SHIFT;
|
||
|
- pm_ctrl_data |= PM_CTRL_SERDES_PD_EX_L1;
|
||
|
- }
|
||
|
- pm_ctrl_data |= PM_CTRL_MAC_ASPM_CHK;
|
||
|
- if (linkup) {
|
||
|
- pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
|
||
|
- if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
|
||
|
- pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
|
||
|
- if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
|
||
|
- pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN;
|
||
|
-
|
||
|
- if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
|
||
|
- hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
|
||
|
- if (hw->nic_type == athr_l2c_b)
|
||
|
- if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE))
|
||
|
- pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
|
||
|
- pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
|
||
|
- if (hw->adapter->link_speed == SPEED_100 ||
|
||
|
- hw->adapter->link_speed == SPEED_1000) {
|
||
|
- pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
|
||
|
- PM_CTRL_L1_ENTRY_TIMER_SHIFT);
|
||
|
- if (hw->nic_type == athr_l2c_b)
|
||
|
- link_l1_timer = 7;
|
||
|
- else if (hw->nic_type == athr_l2c_b2 ||
|
||
|
- hw->nic_type == athr_l1d_2)
|
||
|
- link_l1_timer = 4;
|
||
|
- pm_ctrl_data |= link_l1_timer <<
|
||
|
- PM_CTRL_L1_ENTRY_TIMER_SHIFT;
|
||
|
- }
|
||
|
- } else {
|
||
|
- pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
|
||
|
- pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
|
||
|
- pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
|
||
|
+ hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
|
||
|
+ pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
|
||
|
+ PM_CTRL_PM_REQ_TIMER, PM_CTRL_PM_REQ_TO_DEF);
|
||
|
+ pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER |
|
||
|
+ PM_CTRL_SERDES_PD_EX_L1 |
|
||
|
+ PM_CTRL_CLK_SWH_L1;
|
||
|
+ pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
|
||
|
+ PM_CTRL_SERDES_PLL_L1_EN |
|
||
|
+ PM_CTRL_SERDES_BUFS_RX_L1_EN |
|
||
|
+ PM_CTRL_SA_DLY_EN |
|
||
|
+ PM_CTRL_HOTRST);
|
||
|
+ /* disable l0s if link down or l2cb */
|
||
|
+ if (link_speed == SPEED_0 || hw->nic_type == athr_l2c_b)
|
||
|
pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
|
||
|
-
|
||
|
+ } else { /* l1c */
|
||
|
+ pm_ctrl_data =
|
||
|
+ FIELD_SETX(pm_ctrl_data, PM_CTRL_L1_ENTRY_TIMER, 0);
|
||
|
+ if (link_speed != SPEED_0) {
|
||
|
+ pm_ctrl_data |= PM_CTRL_SERDES_L1_EN |
|
||
|
+ PM_CTRL_SERDES_PLL_L1_EN |
|
||
|
+ PM_CTRL_SERDES_BUFS_RX_L1_EN;
|
||
|
+ pm_ctrl_data &= ~(PM_CTRL_SERDES_PD_EX_L1 |
|
||
|
+ PM_CTRL_CLK_SWH_L1 |
|
||
|
+ PM_CTRL_ASPM_L0S_EN |
|
||
|
+ PM_CTRL_ASPM_L1_EN);
|
||
|
+ } else { /* link down */
|
||
|
+ pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
|
||
|
+ pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
|
||
|
+ PM_CTRL_SERDES_PLL_L1_EN |
|
||
|
+ PM_CTRL_SERDES_BUFS_RX_L1_EN |
|
||
|
+ PM_CTRL_ASPM_L0S_EN);
|
||
|
}
|
||
|
- } else {
|
||
|
- pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
|
||
|
- pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
|
||
|
- pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
|
||
|
-
|
||
|
- if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
|
||
|
- pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
|
||
|
- else
|
||
|
- pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
|
||
|
}
|
||
|
AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
|
||
|
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
-static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter)
|
||
|
-{
|
||
|
- struct atl1c_hw *hw = &adapter->hw;
|
||
|
- struct net_device *netdev = adapter->netdev;
|
||
|
- u32 mac_ctrl_data;
|
||
|
-
|
||
|
- mac_ctrl_data = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
|
||
|
- mac_ctrl_data |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
|
||
|
-
|
||
|
- if (adapter->link_duplex == FULL_DUPLEX) {
|
||
|
- hw->mac_duplex = true;
|
||
|
- mac_ctrl_data |= MAC_CTRL_DUPLX;
|
||
|
- }
|
||
|
-
|
||
|
- if (adapter->link_speed == SPEED_1000)
|
||
|
- hw->mac_speed = atl1c_mac_speed_1000;
|
||
|
- else
|
||
|
- hw->mac_speed = atl1c_mac_speed_10_100;
|
||
|
-
|
||
|
- mac_ctrl_data |= (hw->mac_speed & MAC_CTRL_SPEED_MASK) <<
|
||
|
- MAC_CTRL_SPEED_SHIFT;
|
||
|
-
|
||
|
- mac_ctrl_data |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
|
||
|
- mac_ctrl_data |= ((hw->preamble_len & MAC_CTRL_PRMLEN_MASK) <<
|
||
|
- MAC_CTRL_PRMLEN_SHIFT);
|
||
|
-
|
||
|
- __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
|
||
|
-
|
||
|
- mac_ctrl_data |= MAC_CTRL_BC_EN;
|
||
|
- if (netdev->flags & IFF_PROMISC)
|
||
|
- mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
|
||
|
- if (netdev->flags & IFF_ALLMULTI)
|
||
|
- mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
|
||
|
-
|
||
|
- mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN;
|
||
|
- if (hw->nic_type == athr_l1d || hw->nic_type == athr_l2c_b2 ||
|
||
|
- hw->nic_type == athr_l1d_2) {
|
||
|
- mac_ctrl_data |= MAC_CTRL_SPEED_MODE_SW;
|
||
|
- mac_ctrl_data |= MAC_CTRL_HASH_ALG_CRC32;
|
||
|
- }
|
||
|
- AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
|
||
|
-}
|
||
|
-
|
||
|
/*
|
||
|
* atl1c_configure - Configure Transmit&Receive Unit after Reset
|
||
|
* @adapter: board private structure
|
||
|
*
|
||
|
* Configure the Tx /Rx unit of the MAC after a reset.
|
||
|
*/
|
||
|
-static int atl1c_configure(struct atl1c_adapter *adapter)
|
||
|
+static int atl1c_configure_mac(struct atl1c_adapter *adapter)
|
||
|
{
|
||
|
struct atl1c_hw *hw = &adapter->hw;
|
||
|
u32 master_ctrl_data = 0;
|
||
|
u32 intr_modrt_data;
|
||
|
u32 data;
|
||
|
|
||
|
+ AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
|
||
|
+ master_ctrl_data &= ~(MASTER_CTRL_TX_ITIMER_EN |
|
||
|
+ MASTER_CTRL_RX_ITIMER_EN |
|
||
|
+ MASTER_CTRL_INT_RDCLR);
|
||
|
/* clear interrupt status */
|
||
|
AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
|
||
|
/* Clear any WOL status */
|
||
|
@@ -1525,30 +1418,39 @@ static int atl1c_configure(struct atl1c_adapter *adapter)
|
||
|
master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
|
||
|
AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
|
||
|
|
||
|
- if (hw->ctrl_flags & ATL1C_CMB_ENABLE) {
|
||
|
- AT_WRITE_REG(hw, REG_CMB_TPD_THRESH,
|
||
|
- hw->cmb_tpd & CMB_TPD_THRESH_MASK);
|
||
|
- AT_WRITE_REG(hw, REG_CMB_TX_TIMER,
|
||
|
- hw->cmb_tx_timer & CMB_TX_TIMER_MASK);
|
||
|
- }
|
||
|
+ AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
|
||
|
+ hw->smb_timer & SMB_STAT_TIMER_MASK);
|
||
|
|
||
|
- if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
|
||
|
- AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
|
||
|
- hw->smb_timer & SMB_STAT_TIMER_MASK);
|
||
|
/* set MTU */
|
||
|
AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
|
||
|
VLAN_HLEN + ETH_FCS_LEN);
|
||
|
- /* HDS, disable */
|
||
|
- AT_WRITE_REG(hw, REG_HDS_CTRL, 0);
|
||
|
|
||
|
atl1c_configure_tx(adapter);
|
||
|
atl1c_configure_rx(adapter);
|
||
|
- atl1c_configure_rss(adapter);
|
||
|
atl1c_configure_dma(adapter);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
+static int atl1c_configure(struct atl1c_adapter *adapter)
|
||
|
+{
|
||
|
+ struct net_device *netdev = adapter->netdev;
|
||
|
+ int num;
|
||
|
+
|
||
|
+ atl1c_init_ring_ptrs(adapter);
|
||
|
+ atl1c_set_multi(netdev);
|
||
|
+ atl1c_restore_vlan(adapter);
|
||
|
+
|
||
|
+ num = atl1c_alloc_rx_buffer(adapter);
|
||
|
+ if (unlikely(num == 0))
|
||
|
+ return -ENOMEM;
|
||
|
+
|
||
|
+ if (atl1c_configure_mac(adapter))
|
||
|
+ return -EIO;
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
|
||
|
{
|
||
|
u16 hw_reg_addr = 0;
|
||
|
@@ -1635,16 +1537,11 @@ static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
|
||
|
struct pci_dev *pdev = adapter->pdev;
|
||
|
u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
|
||
|
u16 hw_next_to_clean;
|
||
|
- u16 shift;
|
||
|
- u32 data;
|
||
|
+ u16 reg;
|
||
|
|
||
|
- if (type == atl1c_trans_high)
|
||
|
- shift = MB_HTPD_CONS_IDX_SHIFT;
|
||
|
- else
|
||
|
- shift = MB_NTPD_CONS_IDX_SHIFT;
|
||
|
+ reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX;
|
||
|
|
||
|
- AT_READ_REG(&adapter->hw, REG_MB_PRIO_CONS_IDX, &data);
|
||
|
- hw_next_to_clean = (data >> shift) & MB_PRIO_PROD_IDX_MASK;
|
||
|
+ AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean);
|
||
|
|
||
|
while (next_to_clean != hw_next_to_clean) {
|
||
|
buffer_info = &tpd_ring->buffer_info[next_to_clean];
|
||
|
@@ -1746,9 +1643,9 @@ static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
|
||
|
skb_checksum_none_assert(skb);
|
||
|
}
|
||
|
|
||
|
-static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter, const int ringid)
|
||
|
+static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
|
||
|
{
|
||
|
- struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[ringid];
|
||
|
+ struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
|
||
|
struct pci_dev *pdev = adapter->pdev;
|
||
|
struct atl1c_buffer *buffer_info, *next_info;
|
||
|
struct sk_buff *skb;
|
||
|
@@ -1800,7 +1697,7 @@ static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter, const int ringid
|
||
|
/* TODO: update mailbox here */
|
||
|
wmb();
|
||
|
rfd_ring->next_to_use = rfd_next_to_use;
|
||
|
- AT_WRITE_REG(&adapter->hw, atl1c_rfd_prod_idx_regs[ringid],
|
||
|
+ AT_WRITE_REG(&adapter->hw, REG_MB_RFD0_PROD_IDX,
|
||
|
rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
|
||
|
}
|
||
|
|
||
|
@@ -1839,7 +1736,7 @@ static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
|
||
|
rfd_ring->next_to_clean = rfd_index;
|
||
|
}
|
||
|
|
||
|
-static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
|
||
|
+static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
|
||
|
int *work_done, int work_to_do)
|
||
|
{
|
||
|
u16 rfd_num, rfd_index;
|
||
|
@@ -1847,8 +1744,8 @@ static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
|
||
|
u16 length;
|
||
|
struct pci_dev *pdev = adapter->pdev;
|
||
|
struct net_device *netdev = adapter->netdev;
|
||
|
- struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[que];
|
||
|
- struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring[que];
|
||
|
+ struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
|
||
|
+ struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
|
||
|
struct sk_buff *skb;
|
||
|
struct atl1c_recv_ret_status *rrs;
|
||
|
struct atl1c_buffer *buffer_info;
|
||
|
@@ -1914,7 +1811,7 @@ rrs_checked:
|
||
|
count++;
|
||
|
}
|
||
|
if (count)
|
||
|
- atl1c_alloc_rx_buffer(adapter, que);
|
||
|
+ atl1c_alloc_rx_buffer(adapter);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
@@ -1931,7 +1828,7 @@ static int atl1c_clean(struct napi_struct *napi, int budget)
|
||
|
if (!netif_carrier_ok(adapter->netdev))
|
||
|
goto quit_polling;
|
||
|
/* just enable one RXQ */
|
||
|
- atl1c_clean_rx_irq(adapter, 0, &work_done, budget);
|
||
|
+ atl1c_clean_rx_irq(adapter, &work_done, budget);
|
||
|
|
||
|
if (work_done < budget) {
|
||
|
quit_polling:
|
||
|
@@ -2206,23 +2103,10 @@ static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
|
||
|
struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
|
||
|
{
|
||
|
struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
|
||
|
- u32 prod_data;
|
||
|
+ u16 reg;
|
||
|
|
||
|
- AT_READ_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, &prod_data);
|
||
|
- switch (type) {
|
||
|
- case atl1c_trans_high:
|
||
|
- prod_data &= 0xFFFF0000;
|
||
|
- prod_data |= tpd_ring->next_to_use & 0xFFFF;
|
||
|
- break;
|
||
|
- case atl1c_trans_normal:
|
||
|
- prod_data &= 0x0000FFFF;
|
||
|
- prod_data |= (tpd_ring->next_to_use & 0xFFFF) << 16;
|
||
|
- break;
|
||
|
- default:
|
||
|
- break;
|
||
|
- }
|
||
|
- wmb();
|
||
|
- AT_WRITE_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, prod_data);
|
||
|
+ reg = type == atl1c_trans_high ? REG_TPD_PRI1_PIDX : REG_TPD_PRI0_PIDX;
|
||
|
+ AT_WRITE_REGW(&adapter->hw, reg, tpd_ring->next_to_use);
|
||
|
}
|
||
|
|
||
|
static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
|
||
|
@@ -2307,8 +2191,7 @@ static int atl1c_request_irq(struct atl1c_adapter *adapter)
|
||
|
"Unable to allocate MSI interrupt Error: %d\n",
|
||
|
err);
|
||
|
adapter->have_msi = false;
|
||
|
- } else
|
||
|
- netdev->irq = pdev->irq;
|
||
|
+ }
|
||
|
|
||
|
if (!adapter->have_msi)
|
||
|
flags |= IRQF_SHARED;
|
||
|
@@ -2328,44 +2211,38 @@ static int atl1c_request_irq(struct atl1c_adapter *adapter)
|
||
|
return err;
|
||
|
}
|
||
|
|
||
|
+
|
||
|
+static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter)
|
||
|
+{
|
||
|
+ /* release tx-pending skbs and reset tx/rx ring index */
|
||
|
+ atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
|
||
|
+ atl1c_clean_tx_ring(adapter, atl1c_trans_high);
|
||
|
+ atl1c_clean_rx_ring(adapter);
|
||
|
+}
|
||
|
+
|
||
|
static int atl1c_up(struct atl1c_adapter *adapter)
|
||
|
{
|
||
|
struct net_device *netdev = adapter->netdev;
|
||
|
- int num;
|
||
|
int err;
|
||
|
- int i;
|
||
|
|
||
|
netif_carrier_off(netdev);
|
||
|
- atl1c_init_ring_ptrs(adapter);
|
||
|
- atl1c_set_multi(netdev);
|
||
|
- atl1c_restore_vlan(adapter);
|
||
|
|
||
|
- for (i = 0; i < adapter->num_rx_queues; i++) {
|
||
|
- num = atl1c_alloc_rx_buffer(adapter, i);
|
||
|
- if (unlikely(num == 0)) {
|
||
|
- err = -ENOMEM;
|
||
|
- goto err_alloc_rx;
|
||
|
- }
|
||
|
- }
|
||
|
-
|
||
|
- if (atl1c_configure(adapter)) {
|
||
|
- err = -EIO;
|
||
|
+ err = atl1c_configure(adapter);
|
||
|
+ if (unlikely(err))
|
||
|
goto err_up;
|
||
|
- }
|
||
|
|
||
|
err = atl1c_request_irq(adapter);
|
||
|
if (unlikely(err))
|
||
|
goto err_up;
|
||
|
|
||
|
+ atl1c_check_link_status(adapter);
|
||
|
clear_bit(__AT_DOWN, &adapter->flags);
|
||
|
napi_enable(&adapter->napi);
|
||
|
atl1c_irq_enable(adapter);
|
||
|
- atl1c_check_link_status(adapter);
|
||
|
netif_start_queue(netdev);
|
||
|
return err;
|
||
|
|
||
|
err_up:
|
||
|
-err_alloc_rx:
|
||
|
atl1c_clean_rx_ring(adapter);
|
||
|
return err;
|
||
|
}
|
||
|
@@ -2383,15 +2260,15 @@ static void atl1c_down(struct atl1c_adapter *adapter)
|
||
|
napi_disable(&adapter->napi);
|
||
|
atl1c_irq_disable(adapter);
|
||
|
atl1c_free_irq(adapter);
|
||
|
+ /* disable ASPM if device inactive */
|
||
|
+ atl1c_disable_l0s_l1(&adapter->hw);
|
||
|
/* reset MAC to disable all RX/TX */
|
||
|
atl1c_reset_mac(&adapter->hw);
|
||
|
msleep(1);
|
||
|
|
||
|
adapter->link_speed = SPEED_0;
|
||
|
adapter->link_duplex = -1;
|
||
|
- atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
|
||
|
- atl1c_clean_tx_ring(adapter, atl1c_trans_high);
|
||
|
- atl1c_clean_rx_ring(adapter);
|
||
|
+ atl1c_reset_dma_ring(adapter);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
@@ -2424,13 +2301,6 @@ static int atl1c_open(struct net_device *netdev)
|
||
|
if (unlikely(err))
|
||
|
goto err_up;
|
||
|
|
||
|
- if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
|
||
|
- u32 phy_data;
|
||
|
-
|
||
|
- AT_READ_REG(&adapter->hw, REG_MDIO_CTRL, &phy_data);
|
||
|
- phy_data |= MDIO_AP_EN;
|
||
|
- AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data);
|
||
|
- }
|
||
|
return 0;
|
||
|
|
||
|
err_up:
|
||
|
@@ -2456,6 +2326,8 @@ static int atl1c_close(struct net_device *netdev)
|
||
|
struct atl1c_adapter *adapter = netdev_priv(netdev);
|
||
|
|
||
|
WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
|
||
|
+ set_bit(__AT_DOWN, &adapter->flags);
|
||
|
+ cancel_work_sync(&adapter->common_task);
|
||
|
atl1c_down(adapter);
|
||
|
atl1c_free_ring_resources(adapter);
|
||
|
return 0;
|
||
|
@@ -2467,10 +2339,6 @@ static int atl1c_suspend(struct device *dev)
|
||
|
struct net_device *netdev = pci_get_drvdata(pdev);
|
||
|
struct atl1c_adapter *adapter = netdev_priv(netdev);
|
||
|
struct atl1c_hw *hw = &adapter->hw;
|
||
|
- u32 mac_ctrl_data = 0;
|
||
|
- u32 master_ctrl_data = 0;
|
||
|
- u32 wol_ctrl_data = 0;
|
||
|
- u16 mii_intr_status_data = 0;
|
||
|
u32 wufc = adapter->wol;
|
||
|
|
||
|
atl1c_disable_l0s_l1(hw);
|
||
|
@@ -2481,75 +2349,10 @@ static int atl1c_suspend(struct device *dev)
|
||
|
netif_device_detach(netdev);
|
||
|
|
||
|
if (wufc)
|
||
|
- if (atl1c_phy_power_saving(hw) != 0)
|
||
|
+ if (atl1c_phy_to_ps_link(hw) != 0)
|
||
|
dev_dbg(&pdev->dev, "phy power saving failed");
|
||
|
|
||
|
- AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
|
||
|
- AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
|
||
|
-
|
||
|
- master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS;
|
||
|
- mac_ctrl_data &= ~(MAC_CTRL_PRMLEN_MASK << MAC_CTRL_PRMLEN_SHIFT);
|
||
|
- mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
|
||
|
- MAC_CTRL_PRMLEN_MASK) <<
|
||
|
- MAC_CTRL_PRMLEN_SHIFT);
|
||
|
- mac_ctrl_data &= ~(MAC_CTRL_SPEED_MASK << MAC_CTRL_SPEED_SHIFT);
|
||
|
- mac_ctrl_data &= ~MAC_CTRL_DUPLX;
|
||
|
-
|
||
|
- if (wufc) {
|
||
|
- mac_ctrl_data |= MAC_CTRL_RX_EN;
|
||
|
- if (adapter->link_speed == SPEED_1000 ||
|
||
|
- adapter->link_speed == SPEED_0) {
|
||
|
- mac_ctrl_data |= atl1c_mac_speed_1000 <<
|
||
|
- MAC_CTRL_SPEED_SHIFT;
|
||
|
- mac_ctrl_data |= MAC_CTRL_DUPLX;
|
||
|
- } else
|
||
|
- mac_ctrl_data |= atl1c_mac_speed_10_100 <<
|
||
|
- MAC_CTRL_SPEED_SHIFT;
|
||
|
-
|
||
|
- if (adapter->link_duplex == DUPLEX_FULL)
|
||
|
- mac_ctrl_data |= MAC_CTRL_DUPLX;
|
||
|
-
|
||
|
- /* turn on magic packet wol */
|
||
|
- if (wufc & AT_WUFC_MAG)
|
||
|
- wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
|
||
|
-
|
||
|
- if (wufc & AT_WUFC_LNKC) {
|
||
|
- wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
|
||
|
- /* only link up can wake up */
|
||
|
- if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
|
||
|
- dev_dbg(&pdev->dev, "%s: read write phy "
|
||
|
- "register failed.\n",
|
||
|
- atl1c_driver_name);
|
||
|
- }
|
||
|
- }
|
||
|
- /* clear phy interrupt */
|
||
|
- atl1c_read_phy_reg(hw, MII_ISR, &mii_intr_status_data);
|
||
|
- /* Config MAC Ctrl register */
|
||
|
- __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
|
||
|
-
|
||
|
- /* magic packet maybe Broadcast&multicast&Unicast frame */
|
||
|
- if (wufc & AT_WUFC_MAG)
|
||
|
- mac_ctrl_data |= MAC_CTRL_BC_EN;
|
||
|
-
|
||
|
- dev_dbg(&pdev->dev,
|
||
|
- "%s: suspend MAC=0x%x\n",
|
||
|
- atl1c_driver_name, mac_ctrl_data);
|
||
|
- AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
|
||
|
- AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
|
||
|
- AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
|
||
|
-
|
||
|
- AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
|
||
|
- GPHY_CTRL_EXT_RESET);
|
||
|
- } else {
|
||
|
- AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_POWER_SAVING);
|
||
|
- master_ctrl_data |= MASTER_CTRL_CLK_SEL_DIS;
|
||
|
- mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT;
|
||
|
- mac_ctrl_data |= MAC_CTRL_DUPLX;
|
||
|
- AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
|
||
|
- AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
|
||
|
- AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
|
||
|
- hw->phy_configured = false; /* re-init PHY when resume */
|
||
|
- }
|
||
|
+ atl1c_power_saving(hw, wufc);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
@@ -2562,8 +2365,7 @@ static int atl1c_resume(struct device *dev)
|
||
|
struct atl1c_adapter *adapter = netdev_priv(netdev);
|
||
|
|
||
|
AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
|
||
|
- atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
|
||
|
- ATL1C_PCIE_PHY_RESET);
|
||
|
+ atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
|
||
|
|
||
|
atl1c_phy_reset(&adapter->hw);
|
||
|
atl1c_reset_mac(&adapter->hw);
|
||
|
@@ -2616,7 +2418,6 @@ static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
|
||
|
SET_NETDEV_DEV(netdev, &pdev->dev);
|
||
|
pci_set_drvdata(pdev, netdev);
|
||
|
|
||
|
- netdev->irq = pdev->irq;
|
||
|
netdev->netdev_ops = &atl1c_netdev_ops;
|
||
|
netdev->watchdog_timeo = AT_TX_WATCHDOG;
|
||
|
atl1c_set_ethtool_ops(netdev);
|
||
|
@@ -2706,14 +2507,13 @@ static int __devinit atl1c_probe(struct pci_dev *pdev,
|
||
|
dev_err(&pdev->dev, "cannot map device registers\n");
|
||
|
goto err_ioremap;
|
||
|
}
|
||
|
- netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
|
||
|
|
||
|
/* init mii data */
|
||
|
adapter->mii.dev = netdev;
|
||
|
adapter->mii.mdio_read = atl1c_mdio_read;
|
||
|
adapter->mii.mdio_write = atl1c_mdio_write;
|
||
|
adapter->mii.phy_id_mask = 0x1f;
|
||
|
- adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
|
||
|
+ adapter->mii.reg_num_mask = MDIO_CTRL_REG_MASK;
|
||
|
netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
|
||
|
setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
|
||
|
(unsigned long)adapter);
|
||
|
@@ -2723,8 +2523,7 @@ static int __devinit atl1c_probe(struct pci_dev *pdev,
|
||
|
dev_err(&pdev->dev, "net device private data init failed\n");
|
||
|
goto err_sw_init;
|
||
|
}
|
||
|
- atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
|
||
|
- ATL1C_PCIE_PHY_RESET);
|
||
|
+ atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
|
||
|
|
||
|
/* Init GPHY as early as possible due to power saving issue */
|
||
|
atl1c_phy_reset(&adapter->hw);
|
||
|
@@ -2752,7 +2551,7 @@ static int __devinit atl1c_probe(struct pci_dev *pdev,
|
||
|
dev_dbg(&pdev->dev, "mac address : %pM\n",
|
||
|
adapter->hw.mac_addr);
|
||
|
|
||
|
- atl1c_hw_set_mac_addr(&adapter->hw);
|
||
|
+ atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
|
||
|
INIT_WORK(&adapter->common_task, atl1c_common_task);
|
||
|
adapter->work_event = 0;
|
||
|
err = register_netdev(netdev);
|
||
|
@@ -2796,6 +2595,8 @@ static void __devexit atl1c_remove(struct pci_dev *pdev)
|
||
|
struct atl1c_adapter *adapter = netdev_priv(netdev);
|
||
|
|
||
|
unregister_netdev(netdev);
|
||
|
+ /* restore permanent address */
|
||
|
+ atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.perm_mac_addr);
|
||
|
atl1c_phy_disable(&adapter->hw);
|
||
|
|
||
|
iounmap(adapter->hw.hw_addr);
|