228 lines
8.1 KiB
Diff
228 lines
8.1 KiB
Diff
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From 0042e1e7a03a2fb5d6c464c03ce84d55b31add11 Mon Sep 17 00:00:00 2001
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From: Matt Roper <matthew.d.roper@intel.com>
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Date: Thu, 12 May 2016 07:05:55 -0700
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Subject: [PATCH 01/17] drm/i915: Reorganize WM structs/unions in CRTC state
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Reorganize the nested structures and unions we have for pipe watermark
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data in intel_crtc_state so that platform-specific data can be added in
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a more sensible manner (and save a bit of memory at the same time).
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The change basically changes the organization from:
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union {
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struct intel_pipe_wm ilk;
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struct intel_pipe_wm skl;
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} optimal;
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struct intel_pipe_wm intermediate /* ILK-only */
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to
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union {
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struct {
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struct intel_pipe_wm intermediate;
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struct intel_pipe_wm optimal;
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} ilk;
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struct {
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struct intel_pipe_wm optimal;
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} skl;
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}
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There should be no functional change here, but it will allow us to add
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more platform-specific fields going forward (and more easily extend to
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other platform types like VLV).
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While we're at it, let's move the entire watermark substructure out to
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its own structure definition to make the code slightly more readable.
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Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Link: http://patchwork.freedesktop.org/patch/msgid/1463061971-19638-2-git-send-email-matthew.d.roper@intel.com
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---
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drivers/gpu/drm/i915/intel_display.c | 2 +-
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drivers/gpu/drm/i915/intel_drv.h | 61 +++++++++++++++++++++---------------
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drivers/gpu/drm/i915/intel_pm.c | 18 +++++------
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3 files changed, 45 insertions(+), 36 deletions(-)
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index d19b392..4633aec 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -12027,7 +12027,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
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}
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} else if (dev_priv->display.compute_intermediate_wm) {
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if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
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- pipe_config->wm.intermediate = pipe_config->wm.optimal.ilk;
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+ pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
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}
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if (INTEL_INFO(dev)->gen >= 9) {
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diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
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index 4a24b00..5a186bf 100644
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--- a/drivers/gpu/drm/i915/intel_drv.h
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+++ b/drivers/gpu/drm/i915/intel_drv.h
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@@ -405,6 +405,40 @@ struct skl_pipe_wm {
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uint32_t linetime;
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};
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+struct intel_crtc_wm_state {
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+ union {
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+ struct {
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+ /*
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+ * Intermediate watermarks; these can be
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+ * programmed immediately since they satisfy
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+ * both the current configuration we're
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+ * switching away from and the new
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+ * configuration we're switching to.
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+ */
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+ struct intel_pipe_wm intermediate;
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+
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+ /*
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+ * Optimal watermarks, programmed post-vblank
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+ * when this state is committed.
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+ */
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+ struct intel_pipe_wm optimal;
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+ } ilk;
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+
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+ struct {
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+ /* gen9+ only needs 1-step wm programming */
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+ struct skl_pipe_wm optimal;
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+ } skl;
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+ };
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+
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+ /*
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+ * Platforms with two-step watermark programming will need to
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+ * update watermark programming post-vblank to switch from the
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+ * safe intermediate watermarks to the optimal final
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+ * watermarks.
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+ */
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+ bool need_postvbl_update;
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+};
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+
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struct intel_crtc_state {
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struct drm_crtc_state base;
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@@ -558,32 +592,7 @@ struct intel_crtc_state {
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/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
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bool disable_lp_wm;
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- struct {
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- /*
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- * Optimal watermarks, programmed post-vblank when this state
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- * is committed.
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- */
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- union {
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- struct intel_pipe_wm ilk;
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- struct skl_pipe_wm skl;
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- } optimal;
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-
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- /*
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- * Intermediate watermarks; these can be programmed immediately
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- * since they satisfy both the current configuration we're
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- * switching away from and the new configuration we're switching
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- * to.
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- */
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- struct intel_pipe_wm intermediate;
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-
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- /*
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- * Platforms with two-step watermark programming will need to
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- * update watermark programming post-vblank to switch from the
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- * safe intermediate watermarks to the optimal final
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- * watermarks.
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- */
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- bool need_postvbl_update;
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- } wm;
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+ struct intel_crtc_wm_state wm;
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/* Gamma mode programmed on the pipe */
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uint32_t gamma_mode;
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index a7ef45d..4353fec 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -2309,7 +2309,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
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int level, max_level = ilk_wm_max_level(dev), usable_level;
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struct ilk_wm_maximums max;
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- pipe_wm = &cstate->wm.optimal.ilk;
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+ pipe_wm = &cstate->wm.ilk.optimal;
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for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
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struct intel_plane_state *ps;
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@@ -2391,7 +2391,7 @@ static int ilk_compute_intermediate_wm(struct drm_device *dev,
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struct intel_crtc *intel_crtc,
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struct intel_crtc_state *newstate)
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{
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- struct intel_pipe_wm *a = &newstate->wm.intermediate;
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+ struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
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struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
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int level, max_level = ilk_wm_max_level(dev);
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@@ -2400,7 +2400,7 @@ static int ilk_compute_intermediate_wm(struct drm_device *dev,
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* currently active watermarks to get values that are safe both before
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* and after the vblank.
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*/
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- *a = newstate->wm.optimal.ilk;
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+ *a = newstate->wm.ilk.optimal;
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a->pipe_enabled |= b->pipe_enabled;
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a->sprites_enabled |= b->sprites_enabled;
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a->sprites_scaled |= b->sprites_scaled;
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@@ -2429,7 +2429,7 @@ static int ilk_compute_intermediate_wm(struct drm_device *dev,
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* If our intermediate WM are identical to the final WM, then we can
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* omit the post-vblank programming; only update if it's different.
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*/
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- if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
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+ if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
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newstate->wm.need_postvbl_update = false;
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return 0;
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@@ -3678,7 +3678,7 @@ static void skl_update_wm(struct drm_crtc *crtc)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct skl_wm_values *results = &dev_priv->wm.skl_results;
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struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
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- struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
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+ struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
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/* Clear all dirty flags */
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@@ -3757,7 +3757,7 @@ static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
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struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
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mutex_lock(&dev_priv->wm.wm_mutex);
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- intel_crtc->wm.active.ilk = cstate->wm.intermediate;
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+ intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
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ilk_program_watermarks(dev_priv);
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mutex_unlock(&dev_priv->wm.wm_mutex);
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}
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@@ -3769,7 +3769,7 @@ static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
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mutex_lock(&dev_priv->wm.wm_mutex);
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if (cstate->wm.need_postvbl_update) {
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- intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
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+ intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
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ilk_program_watermarks(dev_priv);
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}
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mutex_unlock(&dev_priv->wm.wm_mutex);
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@@ -3826,7 +3826,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
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struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
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- struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
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+ struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
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enum pipe pipe = intel_crtc->pipe;
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int level, i, max_level;
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uint32_t temp;
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@@ -3892,7 +3892,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
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struct ilk_wm_values *hw = &dev_priv->wm.hw;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
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- struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
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+ struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
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enum pipe pipe = intel_crtc->pipe;
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static const i915_reg_t wm0_pipe_reg[] = {
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[PIPE_A] = WM0_PIPEA_ILK,
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--
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2.7.4
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