47 lines
1.8 KiB
Diff
47 lines
1.8 KiB
Diff
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From patchwork Wed Oct 26 15:17:01 2016
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [3/5] ARM: OMAP4+: Fix bad fallthrough for cpuidle
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From: Tony Lindgren <tony@atomide.com>
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X-Patchwork-Id: 9397501
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Message-Id: <20161026151703.24730-4-tony@atomide.com>
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To: linux-omap@vger.kernel.org
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Cc: Nishanth Menon <nm@ti.com>, Dmitry Lifshitz <lifshitz@compulab.co.il>,
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Dave Gerlach <d-gerlach@ti.com>,
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Enric Balletbo Serra <eballetbo@gmail.com>,
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"Dr . H . Nikolaus Schaller" <hns@goldelico.com>,
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Pau Pajuel <ppajuel@gmail.com>, Grazvydas Ignotas <notasas@gmail.com>,
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Benoit Cousson <bcousson@baylibre.com>,
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Santosh Shilimkar <ssantosh@kernel.org>,
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Javier Martinez Canillas <javier@dowhile0.org>,
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Robert Nelson <robertcnelson@gmail.com>,
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Marek Belisko <marek@goldelico.com>, linux-arm-kernel@lists.infradead.org
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Date: Wed, 26 Oct 2016 08:17:01 -0700
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We don't want to fall through to a bunch of errors for retention
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if PM_OMAP4_CPU_OSWR_DISABLE is not configured for a SoC.
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Fixes: 6099dd37c669 ("ARM: OMAP5 / DRA7: Enable CPU RET on suspend")
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Signed-off-by: Tony Lindgren <tony@atomide.com>
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---
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arch/arm/mach-omap2/omap-mpuss-lowpower.c | 5 ++---
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1 file changed, 2 insertions(+), 3 deletions(-)
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diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
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--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
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+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
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@@ -244,10 +244,9 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
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save_state = 1;
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break;
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case PWRDM_POWER_RET:
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- if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) {
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+ if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
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save_state = 0;
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- break;
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- }
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+ break;
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default:
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/*
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* CPUx CSWR is invalid hardware state. Also CPUx OSWR
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