155 lines
8.0 KiB
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155 lines
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by mail.messagingengine.com (Postfix) with ESMTPA id 07E8010085;
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Sat, 12 Jan 2019 21:17:22 -0500 (EST)
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From: Samuel Holland <samuel@sholland.org>
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To: Catalin Marinas <catalin.marinas@arm.com>,
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Will Deacon <will.deacon@arm.com>,
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Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>,
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Rob Herring <robh+dt@kernel.org>, Mark Rutland <Mark.Rutland@arm.com>,
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Daniel Lezcano <daniel.lezcano@linaro.org>,
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Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <marc.zyngier@arm.com>
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Subject: [PATCH v3 2/2] arm64: dts: allwinner: a64: Enable A64 timer
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workaround
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Date: Sat, 12 Jan 2019 20:17:19 -0600
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Message-Id: <20190113021719.46457-3-samuel@sholland.org>
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In-Reply-To: <20190113021719.46457-1-samuel@sholland.org>
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References: <20190113021719.46457-1-samuel@sholland.org>
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Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,
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linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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Samuel Holland <samuel@sholland.org>
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As instability in the architectural timer has been observed on multiple
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devices using this SoC, inluding the Pine64 and the Orange Pi Win,
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enable the workaround in the SoC's device tree.
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Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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index f3a66f888205..13eac92a8c55 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -175,6 +175,7 @@
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timer {
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compatible = "arm,armv8-timer";
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+ allwinner,erratum-unknown1;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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