85 lines
3.4 KiB
Diff
85 lines
3.4 KiB
Diff
From d8cd9882c866de836235c5761b11e1bc4272508e Mon Sep 17 00:00:00 2001
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From: Kim Phillips <kim.phillips@amd.com>
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Date: Tue, 24 Jan 2023 10:33:13 -0600
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Subject: [PATCH 30/36] KVM: x86: Move open-coded CPUID leaf 0x80000021 EAX bit
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propagation code
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Move code from __do_cpuid_func() to kvm_set_cpu_caps() in preparation for adding
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the features in their native leaf.
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Also drop the bit description comments as it will be more self-describing once
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the individual features are added.
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Whilst there, switch to using the more efficient cpu_feature_enabled() instead
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of static_cpu_has().
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Note, LFENCE_RDTSC and "NULL selector clears base" are currently synthetic,
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Linux-defined feature flags as Linux tracking of the features predates AMD's
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definition. Keep the manual propagation of the flags from their synthetic
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counterparts until the kernel fully converts to AMD's definition, otherwise KVM
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would stop synthesizing the flags as intended.
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Signed-off-by: Kim Phillips <kim.phillips@amd.com>
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Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
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Acked-by: Sean Christopherson <seanjc@google.com>
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Link: https://lore.kernel.org/r/20230124163319.2277355-3-kim.phillips@amd.com
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(cherry picked from commit c35ac8c4bf600ee23bacb20f863aa7830efb23fb)
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Signed-off-by: Mridula Shastry <mridula.c.shastry@oracle.com>
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Reviewed-by: Todd Vierling <todd.vierling@oracle.com>
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---
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arch/x86/kvm/cpuid.c | 31 ++++++++++++-------------------
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1 file changed, 12 insertions(+), 19 deletions(-)
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diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
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index 3726861ae52a..2ca5ac683c44 100644
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--- a/arch/x86/kvm/cpuid.c
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+++ b/arch/x86/kvm/cpuid.c
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@@ -682,6 +682,17 @@ void kvm_set_cpu_caps(void)
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0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
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F(SME_COHERENT));
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+ kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
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+ BIT(0) /* NO_NESTED_DATA_BP */ |
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+ BIT(2) /* LFENCE Always serializing */ | 0 /* SmmPgCfgLock */ |
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+ BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */
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+ );
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+ if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
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+ kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(2) /* LFENCE Always serializing */;
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+ if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
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+ kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(6) /* NULL_SEL_CLR_BASE */;
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+ kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */;
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+
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kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
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F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
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F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
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@@ -1171,25 +1182,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
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break;
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case 0x80000021:
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entry->ebx = entry->ecx = entry->edx = 0;
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- /*
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- * Pass down these bits:
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- * EAX 0 NNDBP, Processor ignores nested data breakpoints
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- * EAX 2 LAS, LFENCE always serializing
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- * EAX 6 NSCB, Null selector clear base
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- *
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- * Other defined bits are for MSRs that KVM does not expose:
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- * EAX 3 SPCL, SMM page configuration lock
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- * EAX 13 PCMSR, Prefetch control MSR
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- *
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- * KVM doesn't support SMM_CTL.
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- * EAX 9 SMM_CTL MSR is not supported
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- */
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- entry->eax &= BIT(0) | BIT(2) | BIT(6);
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- entry->eax |= BIT(9);
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- if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
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- entry->eax |= BIT(2);
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- if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
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- entry->eax |= BIT(6);
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+ cpuid_entry_override(entry, CPUID_8000_0021_EAX);
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break;
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/*Add support for Centaur's CPUID instruction*/
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case 0xC0000000:
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--
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2.39.3
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