85 lines
3.4 KiB
Diff
85 lines
3.4 KiB
Diff
|
From d8cd9882c866de836235c5761b11e1bc4272508e Mon Sep 17 00:00:00 2001
|
||
|
From: Kim Phillips <kim.phillips@amd.com>
|
||
|
Date: Tue, 24 Jan 2023 10:33:13 -0600
|
||
|
Subject: [PATCH 30/36] KVM: x86: Move open-coded CPUID leaf 0x80000021 EAX bit
|
||
|
propagation code
|
||
|
|
||
|
Move code from __do_cpuid_func() to kvm_set_cpu_caps() in preparation for adding
|
||
|
the features in their native leaf.
|
||
|
|
||
|
Also drop the bit description comments as it will be more self-describing once
|
||
|
the individual features are added.
|
||
|
|
||
|
Whilst there, switch to using the more efficient cpu_feature_enabled() instead
|
||
|
of static_cpu_has().
|
||
|
|
||
|
Note, LFENCE_RDTSC and "NULL selector clears base" are currently synthetic,
|
||
|
Linux-defined feature flags as Linux tracking of the features predates AMD's
|
||
|
definition. Keep the manual propagation of the flags from their synthetic
|
||
|
counterparts until the kernel fully converts to AMD's definition, otherwise KVM
|
||
|
would stop synthesizing the flags as intended.
|
||
|
|
||
|
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
|
||
|
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
|
||
|
Acked-by: Sean Christopherson <seanjc@google.com>
|
||
|
Link: https://lore.kernel.org/r/20230124163319.2277355-3-kim.phillips@amd.com
|
||
|
(cherry picked from commit c35ac8c4bf600ee23bacb20f863aa7830efb23fb)
|
||
|
Signed-off-by: Mridula Shastry <mridula.c.shastry@oracle.com>
|
||
|
Reviewed-by: Todd Vierling <todd.vierling@oracle.com>
|
||
|
---
|
||
|
arch/x86/kvm/cpuid.c | 31 ++++++++++++-------------------
|
||
|
1 file changed, 12 insertions(+), 19 deletions(-)
|
||
|
|
||
|
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
|
||
|
index 3726861ae52a..2ca5ac683c44 100644
|
||
|
--- a/arch/x86/kvm/cpuid.c
|
||
|
+++ b/arch/x86/kvm/cpuid.c
|
||
|
@@ -682,6 +682,17 @@ void kvm_set_cpu_caps(void)
|
||
|
0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
|
||
|
F(SME_COHERENT));
|
||
|
|
||
|
+ kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
|
||
|
+ BIT(0) /* NO_NESTED_DATA_BP */ |
|
||
|
+ BIT(2) /* LFENCE Always serializing */ | 0 /* SmmPgCfgLock */ |
|
||
|
+ BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */
|
||
|
+ );
|
||
|
+ if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
|
||
|
+ kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(2) /* LFENCE Always serializing */;
|
||
|
+ if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
|
||
|
+ kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(6) /* NULL_SEL_CLR_BASE */;
|
||
|
+ kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */;
|
||
|
+
|
||
|
kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
|
||
|
F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
|
||
|
F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
|
||
|
@@ -1171,25 +1182,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
|
||
|
break;
|
||
|
case 0x80000021:
|
||
|
entry->ebx = entry->ecx = entry->edx = 0;
|
||
|
- /*
|
||
|
- * Pass down these bits:
|
||
|
- * EAX 0 NNDBP, Processor ignores nested data breakpoints
|
||
|
- * EAX 2 LAS, LFENCE always serializing
|
||
|
- * EAX 6 NSCB, Null selector clear base
|
||
|
- *
|
||
|
- * Other defined bits are for MSRs that KVM does not expose:
|
||
|
- * EAX 3 SPCL, SMM page configuration lock
|
||
|
- * EAX 13 PCMSR, Prefetch control MSR
|
||
|
- *
|
||
|
- * KVM doesn't support SMM_CTL.
|
||
|
- * EAX 9 SMM_CTL MSR is not supported
|
||
|
- */
|
||
|
- entry->eax &= BIT(0) | BIT(2) | BIT(6);
|
||
|
- entry->eax |= BIT(9);
|
||
|
- if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
|
||
|
- entry->eax |= BIT(2);
|
||
|
- if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
|
||
|
- entry->eax |= BIT(6);
|
||
|
+ cpuid_entry_override(entry, CPUID_8000_0021_EAX);
|
||
|
break;
|
||
|
/*Add support for Centaur's CPUID instruction*/
|
||
|
case 0xC0000000:
|
||
|
--
|
||
|
2.39.3
|
||
|
|