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12.0.0-0.2

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This commit is contained in:
Jakub Jelinek 2022-01-18 21:54:19 +01:00
parent 1d6884964d
commit b2295576ca
4 changed files with 155 additions and 4 deletions
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16
gcc.spec
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@ -1,5 +1,5 @@
%global DATE 20220118
%global gitrev 880787aef7a985a80f88a14f830fb554a33b1a87
%global gitrev c682bc883d1a29c3f697f065af23759f3d6757bc
%global gcc_version 12.0.1
%global gcc_major 12
# Note, gcc_release must be integer, if you want to add suffixes to
@ -119,7 +119,7 @@
Summary: Various compilers (C, C++, Objective-C, ...)
Name: gcc
Version: %{gcc_version}
Release: %{gcc_release}.1.1%{?dist}
Release: %{gcc_release}.2%{?dist}
# libgcc, libgfortran, libgomp, libstdc++ and crtstuff have
# GCC Runtime Exception.
License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD
@ -270,6 +270,8 @@ Patch9: gcc12-Wno-format-security.patch
Patch10: gcc12-rh1574936.patch
Patch11: gcc12-d-shared-libphobos.patch
Patch12: gcc12-pr104025.patch
Patch13: gcc12-pr104103.patch
Patch14: gcc12-pr104104.patch
Patch100: gcc12-fortran-fdec-duplicates.patch
Patch101: gcc12-fortran-flogical-as-integer.patch
@ -792,6 +794,8 @@ to NVidia PTX capable devices if available.
%endif
%patch11 -p0 -b .d-shared-libphobos~
%patch12 -p0 -b .pr104025~
%patch13 -p0 -b .pr104103~
%patch14 -p0 -b .pr104104~
%if 0%{?rhel} >= 9
%patch100 -p1 -b .fortran-fdec-duplicates~
@ -3151,8 +3155,14 @@ end
%endif
%changelog
* Tue Jan 18 2022 Jakub Jelinek <jakub@redhat.com> 12.0.1-0.1.1
* Tue Jan 18 2022 Jakub Jelinek <jakub@redhat.com> 12.0.1-0.2
- update from trunk
- PRs c++/104007, c++/104074, fortran/103692, ipa/103989, libstdc++/101124,
libstdc++/104098, middle-end/103163, tree-optimization/103987,
tree-optimization/104038
- default to -mabi=ieeelongdouble on ppc64le
- fix -Wdangling-pointer with -fsanitize=address (PR middle-end/104103)
- fix -masm=intel (PR target/104104)
* Tue Jan 18 2022 Jakub Jelinek <jakub@redhat.com> 12.0.1-0.1
- update from trunk

20
gcc12-pr104103.patch Normal file
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@ -0,0 +1,20 @@
2022-01-18 Jakub Jelinek <jakub@redhat.com>
PR middle-end/104103
* gimple-ssa-warn-access.cc (pass_waccess::check_call): Don't check
.ASAN_MARK calls.
--- gcc/gimple-ssa-warn-access.cc.jj 2022-01-16 20:55:46.783932110 +0100
+++ gcc/gimple-ssa-warn-access.cc 2022-01-18 20:56:13.697780325 +0100
@@ -4232,6 +4232,11 @@ pass_waccess::check_call (gcall *stmt)
if (gimple_call_builtin_p (stmt, BUILT_IN_NORMAL))
check_builtin (stmt);
+ /* .ASAN_MARK doesn't access any vars, only modifies shadow memory. */
+ if (gimple_call_internal_p (stmt)
+ && gimple_call_internal_fn (stmt) == IFN_ASAN_MARK)
+ return;
+
if (!m_early_checks_p)
if (tree callee = gimple_call_fndecl (stmt))
{

121
gcc12-pr104104.patch Normal file
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@ -0,0 +1,121 @@
2022-01-18 Jakub Jelinek <jakub@redhat.com>
PR target/104104
* config/i386/sse.md
(<avx512>_<complexopname>_<mode><maskc_name><round_name>,
avx512fp16_<complexopname>sh_v8hf<mask_scalarc_name><round_scalarcz_name>,
avx512dq_mul<mode>3<mask_name>, <avx2_avx512>_permvar<mode><mask_name>,
avx2_perm<mode>_1<mask_name>, avx512f_perm<mode>_1<mask_name>,
avx512dq_rangep<mode><mask_name><round_saeonly_name>,
avx512dq_ranges<mode><mask_scalar_name><round_saeonly_scalar_name>,
<avx512>_getmant<mode><mask_name><round_saeonly_name>,
avx512f_vgetmant<mode><mask_scalar_name><round_saeonly_scalar_name>):
Use vxorps\t%x0, %x0, %x0 instead of vxorps\t{%x0, %x0, %x0}.
* gcc.target/i386/pr104104.c: New test.
--- gcc/config/i386/sse.md.jj 2022-01-18 11:58:59.156988142 +0100
+++ gcc/config/i386/sse.md 2022-01-18 21:20:40.022477778 +0100
@@ -6539,7 +6539,7 @@ (define_insn "<avx512>_<complexopname>_<
{
if (TARGET_DEST_FALSE_DEP_FOR_GLC
&& <maskc_dest_false_dep_for_glc_cond>)
- output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands);
+ output_asm_insn ("vxorps\t%x0, %x0, %x0", operands);
return "v<complexopname><ssemodesuffix>\t{<round_maskc_op3>%2, %1, %0<maskc_operand3>|%0<maskc_operand3>, %1, %2<round_maskc_op3>}";
}
[(set_attr "type" "ssemul")
@@ -6750,7 +6750,7 @@ (define_insn "avx512fp16_<complexopname>
{
if (TARGET_DEST_FALSE_DEP_FOR_GLC
&& <mask_scalarc_dest_false_dep_for_glc_cond>)
- output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands);
+ output_asm_insn ("vxorps\t%x0, %x0, %x0", operands);
return "v<complexopname>sh\t{<round_scalarc_mask_op3>%2, %1, %0<mask_scalarc_operand3>|%0<mask_scalarc_operand3>, %1, %2<round_scalarc_mask_op3>}";
}
[(set_attr "type" "ssemul")
@@ -15222,7 +15222,7 @@ (define_insn "avx512dq_mul<mode>3<mask_n
&& <mask3_dest_false_dep_for_glc_cond>
&& !reg_mentioned_p (operands[0], operands[1])
&& !reg_mentioned_p (operands[0], operands[2]))
- output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands);
+ output_asm_insn ("vxorps\t%x0, %x0, %x0", operands);
return "vpmullq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}";
}
[(set_attr "type" "sseimul")
@@ -24658,7 +24658,7 @@ (define_insn "<avx2_avx512>_permvar<mode
&& <mask3_dest_false_dep_for_glc_cond>
&& !reg_mentioned_p (operands[0], operands[1])
&& !reg_mentioned_p (operands[0], operands[2]))
- output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands);
+ output_asm_insn ("vxorps\t%x0, %x0, %x0", operands);
return "vperm<ssemodesuffix>\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}";
}
[(set_attr "type" "sselog")
@@ -24900,7 +24900,7 @@ (define_insn "avx2_perm<mode>_1<mask_nam
if (TARGET_DEST_FALSE_DEP_FOR_GLC
&& <mask6_dest_false_dep_for_glc_cond>
&& !reg_mentioned_p (operands[0], operands[1]))
- output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands);
+ output_asm_insn ("vxorps\t%x0, %x0, %x0", operands);
return "vperm<ssemodesuffix>\t{%2, %1, %0<mask_operand6>|%0<mask_operand6>, %1, %2}";
}
[(set_attr "type" "sselog")
@@ -24975,7 +24975,7 @@ (define_insn "avx512f_perm<mode>_1<mask_
if (TARGET_DEST_FALSE_DEP_FOR_GLC
&& <mask10_dest_false_dep_for_glc_cond>
&& !reg_mentioned_p (operands[0], operands[1]))
- output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands);
+ output_asm_insn ("vxorps\t%x0, %x0, %x0", operands);
return "vperm<ssemodesuffix>\t{%2, %1, %0<mask_operand10>|%0<mask_operand10>, %1, %2}";
}
[(set_attr "type" "sselog")
@@ -26880,7 +26880,7 @@ (define_insn "avx512dq_rangep<mode><mask
&& <mask4_dest_false_dep_for_glc_cond>
&& !reg_mentioned_p (operands[0], operands[1])
&& !reg_mentioned_p (operands[0], operands[2]))
- output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands);
+ output_asm_insn ("vxorps\t%x0, %x0, %x0", operands);
return "vrange<ssemodesuffix>\t{%3, <round_saeonly_mask_op4>%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2<round_saeonly_mask_op4>, %3}";
}
[(set_attr "type" "sse")
@@ -26903,7 +26903,7 @@ (define_insn "avx512dq_ranges<mode><mask
&& <mask_scalar4_dest_false_dep_for_glc_cond>
&& !reg_mentioned_p (operands[0], operands[1])
&& !reg_mentioned_p (operands[0], operands[2]))
- output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands);
+ output_asm_insn ("vxorps\t%x0, %x0, %x0", operands);
return "vrange<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2<round_saeonly_scalar_mask_op4>, %3}";
}
[(set_attr "type" "sse")
@@ -26949,7 +26949,7 @@ (define_insn "<avx512>_getmant<mode><mas
if (TARGET_DEST_FALSE_DEP_FOR_GLC
&& <mask3_dest_false_dep_for_glc_cond>
&& MEM_P (operands[1]))
- output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands);
+ output_asm_insn ("vxorps\t%x0, %x0, %x0", operands);
return "vgetmant<ssemodesuffix>\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}";
}
[(set_attr "prefix" "evex")
@@ -26971,7 +26971,7 @@ (define_insn "avx512f_vgetmant<mode><mas
&& <mask_scalar4_dest_false_dep_for_glc_cond>
&& !reg_mentioned_p (operands[0], operands[1])
&& !reg_mentioned_p (operands[0], operands[2]))
- output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands);
+ output_asm_insn ("vxorps\t%x0, %x0, %x0", operands);
return "vgetmant<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2<round_saeonly_scalar_mask_op4>, %3}";
}
[(set_attr "prefix" "evex")
--- gcc/testsuite/gcc.target/i386/pr104104.c.jj 2022-01-18 21:38:17.007906673 +0100
+++ gcc/testsuite/gcc.target/i386/pr104104.c 2022-01-18 21:36:10.475623148 +0100
@@ -0,0 +1,10 @@
+/* PR target/104104 */
+/* { dg-do assemble { target vect_simd_clones } } */
+/* { dg-require-effective-target masm_intel } */
+/* { dg-options "-march=alderlake -masm=intel -O1 -fallow-store-data-races -funroll-all-loops" } */
+
+__attribute__ ((simd)) short int
+foo (void)
+{
+ return 0;
+}

2
sources
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@ -1,4 +1,4 @@
SHA512 (gcc-12.0.1-20220118.tar.xz) = 903418bda48240537a0f7b74687e70042d56cea7bc079319380098c3465079d064083e5d6bad4d9d44bcf7e7f929dd6f692ab638ff40824e8f2f2712991f9290
SHA512 (gcc-12.0.1-20220118.tar.xz) = 5fab239e915e71a8986a122e3f897f2236f21f0f183da33cad2ace8f34823cd8f32c7c0dfceffbfeae17cd99b656f242d30ddeb94eaafe3edf858ea88ec59016
SHA512 (isl-0.18.tar.bz2) = 85d0b40f4dbf14cb99d17aa07048cdcab2dc3eb527d2fbb1e84c41b2de5f351025370e57448b63b2b8a8cf8a0843a089c3263f9baee1542d5c2e1cb37ed39d94
SHA512 (newlib-cygwin-50e2a63b04bdd018484605fbb954fd1bd5147fa0.tar.xz) = 002a48a7b689a81abbf16161bcaec001a842e67dfbe372e9e109092703bfc666675f16198f60ca429370e8850d564547dc505df81bc3aaca4ce6defbc014ad6c
SHA512 (nvptx-tools-5f6f343a302d620b0868edab376c00b15741e39e.tar.xz) = f6d10db94fa1570ae0f94df073fa3c73c8e5ee16d59070b53d94f7db0de8a031bc44d7f3f1852533da04b625ce758e022263855ed43cfc6867e0708d001e53c7