10.0.1-0.12
This commit is contained in:
Jakub Jelinek
parent
643c97a3d8
commit
9d851d2a4e
1
.gitignore
vendored
1
.gitignore
vendored
@ -9,3 +9,4 @@
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/gcc-10.0.1-20200311.tar.xz
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/gcc-10.0.1-20200325.tar.xz
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/gcc-10.0.1-20200328.tar.xz
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/gcc-10.0.1-20200420.tar.xz
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55
gcc.spec
55
gcc.spec
@ -1,10 +1,10 @@
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%global DATE 20200328
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%global gitrev 97ad35f30b0d8ed5376febf09cefa2b93f9dc423
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%global DATE 20200420
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%global gitrev dbc1bb99e280740e5bda658a911d9dd3f431ad4d
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%global gcc_version 10.0.1
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%global gcc_major 10
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# Note, gcc_release must be integer, if you want to add suffixes to
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# %%{release}, append them after %%{gcc_release} on Release: line.
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%global gcc_release 0.11
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%global gcc_release 0.12
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%global nvptx_tools_gitrev 5f6f343a302d620b0868edab376c00b15741e39e
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%global newlib_cygwin_gitrev 50e2a63b04bdd018484605fbb954fd1bd5147fa0
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%global _unpackaged_files_terminate_build 0
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@ -265,8 +265,6 @@ Patch8: gcc10-foffload-default.patch
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Patch9: gcc10-Wno-format-security.patch
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Patch10: gcc10-rh1574936.patch
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Patch11: gcc10-d-shared-libphobos.patch
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Patch12: gcc10-pr93069.patch
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Patch13: gcc10-pr94343.patch
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# On ARM EABI systems, we do want -gnueabi to be part of the
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# target triple.
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@ -778,8 +776,6 @@ to NVidia PTX capable devices if available.
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%patch10 -p0 -b .rh1574936~
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%endif
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%patch11 -p0 -b .d-shared-libphobos~
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%patch12 -p0 -b .pr93069~
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%patch13 -p0 -b .pr94343~
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echo 'Red Hat %{version}-%{gcc_release}' > gcc/DEV-PHASE
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@ -3008,6 +3004,51 @@ end
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%endif
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%changelog
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* Mon Apr 20 2020 Jakub Jelinek <jakub@redhat.com> 10.0.1-0.12
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- update from trunk
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- PRs analyzer/94378, bootstrap/89494, bootstrap/92008, c++/67825,
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c++/79937, c++/85278, c++/86327, c++/88754, c++/90711, c++/90996,
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c++/91377, c++/91966, c++/92010, c++/92187, c++/92878, c++/93207,
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c++/93211, c++/93790, c++/94034, c++/94149, c++/94155, c++/94205,
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c++/94219, c++/94252, c++/94306, c++/94314, c++/94325, c++/94359,
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c++/94385, c++/94426, c++/94453, c++/94454, c++/94462, c++/94470,
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c++/94475, c++/94477, c++/94478, c++/94480, c++/94481, c++/94483,
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c++/94507, c++/94512, c++/94521, c++/94523, c++/94528, c++/94571,
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c++/94588, c++/94608, c++/94632, c/92326, c/94392, c/94593, d/90136,
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d/94304, d/94305, d/94315, d/94321, d/94424, d/94425, d/94609,
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debug/94439, debug/94441, debug/94450, debug/94459, debug/94495,
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driver/94381, fortran/57129, fortran/85982, fortran/87644,
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fortran/87923, fortran/91800, fortran/93364, fortran/93498,
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fortran/93500, fortran/93522, fortran/93686, fortran/93871,
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fortran/94030, fortran/94090, fortran/94091, fortran/94192,
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fortran/94246, fortran/94347, fortran/94348, fortran/94386,
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gcov-profile/93401, gcov-profile/94570, go/94607, ipa/92676,
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ipa/93621, ipa/93940, ipa/94363, ipa/94434, ipa/94445, ipa/94582,
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libgcc/94513, libgomp/92843, libstdc++/93960, libstdc++/94498,
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libstdc++/94520, libstdc++/94562, libstdc++/94565, lto/94612,
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middle-end/89433, middle-end/93465, middle-end/94412,
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middle-end/94423, middle-end/94436, middle-end/94465,
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middle-end/94479, middle-end/94526, middle-end/94539,
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middle-end/94614, middle-end/94635, objc/94637, other/94629,
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rtl-optimization/84169, rtl-optimization/87716,
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rtl-optimization/93946, rtl-optimization/93974,
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rtl-optimization/94123, rtl-optimization/94291,
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rtl-optimization/94344, rtl-optimization/94468,
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rtl-optimization/94516, rtl-optimization/94605,
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rtl-optimization/94618, target/93053, target/94317, target/94368,
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target/94396, target/94417, target/94420, target/94435, target/94438,
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target/94460, target/94467, target/94488, target/94494, target/94500,
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target/94509, target/94530, target/94542, target/94551, target/94556,
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target/94561, target/94567, target/94584, target/94603, target/94606,
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testsuite/93369, testsuite/94079, testsuite/94402, testsuite/94533,
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tree-optimization/89713, tree-optimization/91322,
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tree-optimization/93674, tree-optimization/94043,
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tree-optimization/94398, tree-optimization/94401,
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tree-optimization/94403, tree-optimization/94443,
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tree-optimization/94482, tree-optimization/94524,
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tree-optimization/94573, tree-optimization/94574,
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tree-optimization/94598, tree-optimization/94621
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* Sat Mar 28 2020 Jakub Jelinek <jakub@redhat.com> 10.0.1-0.11
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- update from trunk
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- PRs c++/81349, c++/84733, c++/93810, c++/93824, c++/94057, c++/94078,
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@ -1,70 +0,0 @@
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2020-03-26 Jakub Jelinek <jakub@redhat.com>
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PR target/93069
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* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
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<store_mask_constraint> instead of m in output operand constraint.
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(vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
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%{%3%}.
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* gcc.target/i386/avx512vl-pr93069.c: New test.
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* gcc.dg/vect/pr93069.c: New test.
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--- gcc/config/i386/sse.md.jj 2019-12-27 18:16:48.146431083 +0100
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+++ gcc/config/i386/sse.md 2019-12-28 14:43:29.181456611 +0100
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@@ -8782,7 +8782,8 @@
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})
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(define_insn "vec_extract_lo_<mode><mask_name>"
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- [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,v,m")
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+ [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
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+ "=v,v,<store_mask_constraint>")
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(vec_select:<ssehalfvecmode>
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(match_operand:V16FI 1 "<store_mask_predicate>"
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"v,<store_mask_constraint>,v")
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@@ -8834,7 +8835,8 @@
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})
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(define_insn "vec_extract_lo_<mode><mask_name>"
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- [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,v,m")
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+ [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
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+ "=v,v,<store_mask_constraint>")
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(vec_select:<ssehalfvecmode>
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(match_operand:VI8F_256 1 "<store_mask_predicate>"
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"v,<store_mask_constraint>,v")
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@@ -8844,7 +8846,7 @@
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&& (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
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{
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if (<mask_applied>)
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- return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}";
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+ return "vextract<shuffletype>64x2\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
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else
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return "#";
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}
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--- gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c.jj 2019-12-28 16:31:30.118695074 +0100
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+++ gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c 2019-12-28 16:32:16.920990539 +0100
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@@ -0,0 +1,12 @@
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+/* PR target/93069 */
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+/* { dg-do assemble { target vect_simd_clones } } */
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+/* { dg-options "-O2 -fopenmp-simd -mtune=skylake-avx512" } */
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+/* { dg-additional-options "-mavx512vl" { target avx512vl } } */
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+/* { dg-additional-options "-mavx512dq" { target avx512dq } } */
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+
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+#pragma omp declare simd
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+int
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+foo (int x, int y)
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+{
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+ return x == 0 ? x : y;
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+}
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--- gcc/testsuite/gcc.dg/vect/pr93069.c.jj 2019-12-28 16:31:01.822121036 +0100
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+++ gcc/testsuite/gcc.dg/vect/pr93069.c 2019-12-28 16:30:35.503517205 +0100
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@@ -0,0 +1,10 @@
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+/* PR target/93069 */
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+/* { dg-do assemble { target vect_simd_clones } } */
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+/* { dg-options "-O2 -fopenmp-simd" } */
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+
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+#pragma omp declare simd
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+int
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+foo (int x, int y)
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+{
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+ return x == 0 ? x : y;
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+}
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@ -1,78 +0,0 @@
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2020-03-26 Jakub Jelinek <jakub@redhat.com>
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PR target/94343
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* config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
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!TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
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operand is a register. Don't enable masked variants for V*[QH]Imode.
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* gcc.target/i386/avx512f-pr94343.c: New test.
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* gcc.target/i386/avx512vl-pr94343.c: New test.
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--- gcc/config/i386/sse.md.jj 2020-03-06 11:35:46.284074858 +0100
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+++ gcc/config/i386/sse.md 2020-03-26 18:49:39.644131577 +0100
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@@ -12796,14 +12796,29 @@ (define_expand "one_cmpl<mode>2"
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})
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(define_insn "<mask_codefor>one_cmpl<mode>2<mask_name>"
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- [(set (match_operand:VI 0 "register_operand" "=v")
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- (xor:VI (match_operand:VI 1 "nonimmediate_operand" "vm")
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- (match_operand:VI 2 "vector_all_ones_operand" "BC")))]
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- "TARGET_AVX512F"
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- "vpternlog<ternlogsuffix>\t{$0x55, %1, %0, %0<mask_operand3>|%0<mask_operand3>, %0, %1, 0x55}"
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+ [(set (match_operand:VI 0 "register_operand" "=v,v")
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+ (xor:VI (match_operand:VI 1 "nonimmediate_operand" "v,m")
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+ (match_operand:VI 2 "vector_all_ones_operand" "BC,BC")))]
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+ "TARGET_AVX512F
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+ && (!<mask_applied>
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+ || <ssescalarmode>mode == SImode
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+ || <ssescalarmode>mode == DImode)"
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+{
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+ if (TARGET_AVX512VL)
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+ return "vpternlog<ternlogsuffix>\t{$0x55, %1, %0, %0<mask_operand3>|%0<mask_operand3>, %0, %1, 0x55}";
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+ else
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+ return "vpternlog<ternlogsuffix>\t{$0x55, %g1, %g0, %g0<mask_operand3>|%g0<mask_operand3>, %g0, %g1, 0x55}";
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+}
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[(set_attr "type" "sselog")
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(set_attr "prefix" "evex")
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- (set_attr "mode" "<sseinsnmode>")])
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+ (set (attr "mode")
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+ (if_then_else (match_test "TARGET_AVX512VL")
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+ (const_string "<sseinsnmode>")
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+ (const_string "XI")))
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+ (set (attr "enabled")
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+ (if_then_else (eq_attr "alternative" "1")
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+ (symbol_ref "<MODE_SIZE> == 64 || TARGET_AVX512VL")
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+ (const_int 1)))])
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(define_expand "<sse2_avx2>_andnot<mode>3"
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[(set (match_operand:VI_AVX2 0 "register_operand")
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--- gcc/testsuite/gcc.target/i386/avx512f-pr94343.c.jj 2020-03-26 17:47:40.008654504 +0100
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+++ gcc/testsuite/gcc.target/i386/avx512f-pr94343.c 2020-03-26 17:48:37.169811375 +0100
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@@ -0,0 +1,12 @@
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+/* PR target/94343 */
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mavx512f -mno-avx512vl" } */
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+/* { dg-final { scan-assembler-not "vpternlogd\[^\n\r]*xmm\[0-9]*" } } */
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+
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+typedef int __v4si __attribute__((vector_size (16)));
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+
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+__v4si
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+foo (__v4si a)
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+{
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+ return ~a;
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+}
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--- gcc/testsuite/gcc.target/i386/avx512vl-pr94343.c.jj 2020-03-26 17:48:53.232573115 +0100
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+++ gcc/testsuite/gcc.target/i386/avx512vl-pr94343.c 2020-03-26 17:49:08.034352968 +0100
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@@ -0,0 +1,12 @@
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+/* PR target/94343 */
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mavx512vl" } */
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+/* { dg-final { scan-assembler "vpternlogd\[^\n\r]*xmm\[0-9]*" } } */
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+
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+typedef int __v4si __attribute__((vector_size (16)));
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+
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+__v4si
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+foo (__v4si a)
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+{
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+ return ~a;
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+}
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2
sources
2
sources
@ -1,3 +1,3 @@
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SHA512 (gcc-10.0.1-20200328.tar.xz) = 567f7b9c7b3ac41465bac0354d94f58ab92abe8a5cc2462551397d4bee6071a90ae79c65a4e1d84f51dde6b8639574606675204c78ce0d16f3fc47c169a4ef60
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SHA512 (gcc-10.0.1-20200420.tar.xz) = 3504ebfe7b9fbe59daaf5568ffe3d2c286180dda52ca57600dca370aca51231464e553758148487d1ea15c1d50f1cb72229910592a5137e4901ef537394437e4
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SHA512 (newlib-cygwin-50e2a63b04bdd018484605fbb954fd1bd5147fa0.tar.xz) = 9ceea0b883185fe489724d54a7e909bb6ed4785fcadf80162033dc6a133e2657337175601278e4155d1f8fac275ff9c8a02572aea876166c608774c809f832e9
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SHA512 (nvptx-tools-5f6f343a302d620b0868edab376c00b15741e39e.tar.xz) = f6d10db94fa1570ae0f94df073fa3c73c8e5ee16d59070b53d94f7db0de8a031bc44d7f3f1852533da04b625ce758e022263855ed43cfc6867e0708d001e53c7
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