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9.0.1-0.8

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This commit is contained in:
Jakub Jelinek 2019-02-27 15:29:11 +01:00
parent d1c6bd89f3
commit 8ccdd26200
6 changed files with 354 additions and 4 deletions
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1
.gitignore vendored
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@ -66,3 +66,4 @@
/gcc-9.0.1-20190215.tar.xz /gcc-9.0.1-20190215.tar.xz
/gcc-9.0.1-20190219.tar.xz /gcc-9.0.1-20190219.tar.xz
/gcc-9.0.1-20190221.tar.xz /gcc-9.0.1-20190221.tar.xz
/gcc-9.0.1-20190227.tar.xz

37
gcc.spec
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@ -1,10 +1,10 @@
%global DATE 20190221 %global DATE 20190227
%global SVNREV 269078 %global SVNREV 269254
%global gcc_version 9.0.1 %global gcc_version 9.0.1
%global gcc_major 9 %global gcc_major 9
# Note, gcc_release must be integer, if you want to add suffixes to # Note, gcc_release must be integer, if you want to add suffixes to
# %%{release}, append them after %%{gcc_release} on Release: line. # %%{release}, append them after %%{gcc_release} on Release: line.
%global gcc_release 0.7 %global gcc_release 0.8
%global nvptx_tools_gitrev c28050f60193b3b95a18866a96f03334e874e78f %global nvptx_tools_gitrev c28050f60193b3b95a18866a96f03334e874e78f
%global nvptx_newlib_gitrev aadc8eb0ec43b7cd0dd2dfb484bae63c8b05ef24 %global nvptx_newlib_gitrev aadc8eb0ec43b7cd0dd2dfb484bae63c8b05ef24
%global _unpackaged_files_terminate_build 0 %global _unpackaged_files_terminate_build 0
@ -256,6 +256,9 @@ Patch10: gcc9-rh1574936.patch
Patch11: gcc9-d-shared-libphobos.patch Patch11: gcc9-d-shared-libphobos.patch
Patch12: gcc9-pr89014.patch Patch12: gcc9-pr89014.patch
Patch13: gcc9-pr89093.patch Patch13: gcc9-pr89093.patch
Patch14: gcc9-pr70341.patch
Patch15: gcc9-pr89490.patch
Patch16: gcc9-pr89506.patch
Patch1000: nvptx-tools-no-ptxas.patch Patch1000: nvptx-tools-no-ptxas.patch
Patch1001: nvptx-tools-build.patch Patch1001: nvptx-tools-build.patch
@ -768,6 +771,9 @@ to NVidia PTX capable devices if available.
%patch11 -p0 -b .d-shared-libphobos~ %patch11 -p0 -b .d-shared-libphobos~
%patch12 -p0 -b .pr89014~ %patch12 -p0 -b .pr89014~
%patch13 -p0 -b .pr89093~ %patch13 -p0 -b .pr89093~
%patch14 -p0 -b .pr70341~
%patch15 -p0 -b .pr89490~
%patch16 -p0 -b .pr89506~
cd nvptx-tools-%{nvptx_tools_gitrev} cd nvptx-tools-%{nvptx_tools_gitrev}
%patch1000 -p1 -b .nvptx-tools-no-ptxas~ %patch1000 -p1 -b .nvptx-tools-no-ptxas~
@ -2956,6 +2962,31 @@ end
%endif %endif
%changelog %changelog
* Wed Feb 27 2019 Jakub Jelinek <jakub@redhat.com> 9.0.1-0.8
- update from trunk
- PRs c++/84585, c++/84676, c++/87685, c++/88294, c++/88394, c++/88419,
c++/88869, c++/88987, c++/89285, c++/89419, c++/89420, c++/89422,
c++/89481, c++/89488, c++/89507, c/77754, c/80409, c/89425, c/89495,
debug/88878, debug/89514, driver/69471, fortran/43210, fortran/72741,
fortran/78027, fortran/83057, fortran/84387, fortran/88117,
fortran/88326, fortran/89174, fortran/89266, fortran/89282,
fortran/89366, fortran/89385, fortran/89431, fortran/89492,
fortran/89496, go/89170, libfortran/89274, libstdc++/89446,
libstdc++/89466, libstdc++/89477, middle-end/85598, middle-end/87609,
rtl-optimization/86096, rtl-optimization/87761,
rtl-optimization/89445, target/87007, target/88530, target/89324,
target/89338, target/89339, target/89434, target/89438, target/89444,
target/89474, testsuite/89476, tree-optimization/87609,
tree-optimization/88853, tree-optimization/88993,
tree-optimization/89280, tree-optimization/89440,
tree-optimization/89489, tree-optimization/89500,
tree-optimization/89505
- improve arm and aarch64 casesi (PR target/70341)
- don't use section anchors block infrastructure for mergeable section
data (PR rtl-optimization/89490)
- fix arm cmpsi2_addneg and subsi3_carryin_compare_const patterns
and corresponding splitters (PR target/89506)
* Thu Feb 21 2019 Jakub Jelinek <jakub@redhat.com> 9.0.1-0.7 * Thu Feb 21 2019 Jakub Jelinek <jakub@redhat.com> 9.0.1-0.7
- update from trunk - update from trunk
- PRs c++/84536, c++/87513, c++/87921, c++/88368, c++/88380, c++/88572, - PRs c++/84536, c++/87513, c++/87921, c++/88368, c++/88380, c++/88572,

187
gcc9-pr70341.patch Normal file
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@ -0,0 +1,187 @@
2019-02-23 Jakub Jelinek <jakub@redhat.com>
PR target/70341
* config/arm/arm.md (arm_casesi_internal): New define_expand. Rename
old define_insn to ...
(*arm_casesi_internal): ... this. Add mode to LABEL_REFs.
* config/arm/thumb2.md (thumb2_casesi_internal): New define_expand.
Rename old define_insn to ...
(*thumb2_casesi_internal): ... this. Add mode to LABEL_REFs.
(thumb2_casesi_internal_pic): New define_expand. Rename old
define_insn to ...
(*thumb2_casesi_internal_pic): ... this. Add mode to LABEL_REFs.
* config/aarch64/aarch64.md (casesi): Create the casesi_dispatch
MEM manually here, set MEM_READONLY_P and MEM_NOTRAP_P on it.
--- gcc/config/arm/arm.md.jj 2019-02-18 20:48:32.643732307 +0100
+++ gcc/config/arm/arm.md 2019-02-21 14:40:50.603452028 +0100
@@ -8914,16 +8914,35 @@ (define_expand "casesi"
;; The USE in this pattern is needed to tell flow analysis that this is
;; a CASESI insn. It has no other purpose.
-(define_insn "arm_casesi_internal"
+(define_expand "arm_casesi_internal"
+ [(parallel [(set (pc)
+ (if_then_else
+ (leu (match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "arm_rhs_operand"))
+ (match_dup 4)
+ (label_ref:SI (match_operand 3 ""))))
+ (clobber (reg:CC CC_REGNUM))
+ (use (label_ref:SI (match_operand 2 "")))])]
+ "TARGET_ARM"
+{
+ operands[4] = gen_rtx_MULT (SImode, operands[0], GEN_INT (4));
+ operands[4] = gen_rtx_PLUS (SImode, operands[4],
+ gen_rtx_LABEL_REF (SImode, operands[2]));
+ operands[4] = gen_rtx_MEM (SImode, operands[4]);
+ MEM_READONLY_P (operands[4]) = 1;
+ MEM_NOTRAP_P (operands[4]) = 1;
+})
+
+(define_insn "*arm_casesi_internal"
[(parallel [(set (pc)
(if_then_else
(leu (match_operand:SI 0 "s_register_operand" "r")
(match_operand:SI 1 "arm_rhs_operand" "rI"))
(mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
- (label_ref (match_operand 2 "" ""))))
- (label_ref (match_operand 3 "" ""))))
+ (label_ref:SI (match_operand 2 "" ""))))
+ (label_ref:SI (match_operand 3 "" ""))))
(clobber (reg:CC CC_REGNUM))
- (use (label_ref (match_dup 2)))])]
+ (use (label_ref:SI (match_dup 2)))])]
"TARGET_ARM"
"*
if (flag_pic)
--- gcc/config/arm/thumb2.md.jj 2019-01-01 12:37:28.280792453 +0100
+++ gcc/config/arm/thumb2.md 2019-02-21 15:00:26.811137210 +0100
@@ -1079,17 +1079,37 @@ (define_insn "thumb2_zero_extendqisi2_v6
(set_attr "neg_pool_range" "*,250")]
)
-(define_insn "thumb2_casesi_internal"
+(define_expand "thumb2_casesi_internal"
+ [(parallel [(set (pc)
+ (if_then_else
+ (leu (match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "arm_rhs_operand"))
+ (match_dup 4)
+ (label_ref:SI (match_operand 3 ""))))
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (match_scratch:SI 5))
+ (use (label_ref:SI (match_operand 2 "")))])]
+ "TARGET_THUMB2 && !flag_pic"
+{
+ operands[4] = gen_rtx_MULT (SImode, operands[0], GEN_INT (4));
+ operands[4] = gen_rtx_PLUS (SImode, operands[4],
+ gen_rtx_LABEL_REF (SImode, operands[2]));
+ operands[4] = gen_rtx_MEM (SImode, operands[4]);
+ MEM_READONLY_P (operands[4]) = 1;
+ MEM_NOTRAP_P (operands[4]) = 1;
+})
+
+(define_insn "*thumb2_casesi_internal"
[(parallel [(set (pc)
(if_then_else
(leu (match_operand:SI 0 "s_register_operand" "r")
(match_operand:SI 1 "arm_rhs_operand" "rI"))
(mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
- (label_ref (match_operand 2 "" ""))))
- (label_ref (match_operand 3 "" ""))))
+ (label_ref:SI (match_operand 2 "" ""))))
+ (label_ref:SI (match_operand 3 "" ""))))
(clobber (reg:CC CC_REGNUM))
(clobber (match_scratch:SI 4 "=&r"))
- (use (label_ref (match_dup 2)))])]
+ (use (label_ref:SI (match_dup 2)))])]
"TARGET_THUMB2 && !flag_pic"
"* return thumb2_output_casesi(operands);"
[(set_attr "conds" "clob")
@@ -1097,18 +1117,39 @@ (define_insn "thumb2_casesi_internal"
(set_attr "type" "multiple")]
)
-(define_insn "thumb2_casesi_internal_pic"
+(define_expand "thumb2_casesi_internal_pic"
+ [(parallel [(set (pc)
+ (if_then_else
+ (leu (match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "arm_rhs_operand"))
+ (match_dup 4)
+ (label_ref:SI (match_operand 3 ""))))
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (match_scratch:SI 5))
+ (clobber (match_scratch:SI 6))
+ (use (label_ref:SI (match_operand 2 "")))])]
+ "TARGET_THUMB2 && flag_pic"
+{
+ operands[4] = gen_rtx_MULT (SImode, operands[0], GEN_INT (4));
+ operands[4] = gen_rtx_PLUS (SImode, operands[4],
+ gen_rtx_LABEL_REF (SImode, operands[2]));
+ operands[4] = gen_rtx_MEM (SImode, operands[4]);
+ MEM_READONLY_P (operands[4]) = 1;
+ MEM_NOTRAP_P (operands[4]) = 1;
+})
+
+(define_insn "*thumb2_casesi_internal_pic"
[(parallel [(set (pc)
(if_then_else
(leu (match_operand:SI 0 "s_register_operand" "r")
(match_operand:SI 1 "arm_rhs_operand" "rI"))
(mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
- (label_ref (match_operand 2 "" ""))))
- (label_ref (match_operand 3 "" ""))))
+ (label_ref:SI (match_operand 2 "" ""))))
+ (label_ref:SI (match_operand 3 "" ""))))
(clobber (reg:CC CC_REGNUM))
(clobber (match_scratch:SI 4 "=&r"))
(clobber (match_scratch:SI 5 "=r"))
- (use (label_ref (match_dup 2)))])]
+ (use (label_ref:SI (match_dup 2)))])]
"TARGET_THUMB2 && flag_pic"
"* return thumb2_output_casesi(operands);"
[(set_attr "conds" "clob")
--- gcc/config/aarch64/aarch64.md.jj 2019-01-19 09:39:18.847831222 +0100
+++ gcc/config/aarch64/aarch64.md 2019-02-21 15:25:27.874532191 +0100
@@ -622,13 +622,27 @@ (define_expand "casesi"
operands[0], operands[2], operands[4]));
operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[3]));
- emit_jump_insn (gen_casesi_dispatch (operands[2], operands[0],
- operands[3]));
+ operands[2]
+ = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[2], operands[0]),
+ UNSPEC_CASESI);
+ operands[2] = gen_rtx_MEM (DImode, operands[2]);
+ MEM_READONLY_P (operands[2]) = 1;
+ MEM_NOTRAP_P (operands[2]) = 1;
+ emit_jump_insn (gen_casesi_dispatch (operands[2], operands[3]));
DONE;
}
)
-(define_insn "casesi_dispatch"
+(define_expand "casesi_dispatch"
+ [(parallel
+ [(set (pc) (match_operand:DI 0 ""))
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (match_scratch:DI 2))
+ (clobber (match_scratch:DI 3))
+ (use (label_ref:DI (match_operand 1 "")))])]
+ "")
+
+(define_insn "*casesi_dispatch"
[(parallel
[(set (pc)
(mem:DI (unspec [(match_operand:DI 0 "register_operand" "r")
@@ -637,7 +651,7 @@ (define_insn "casesi_dispatch"
(clobber (reg:CC CC_REGNUM))
(clobber (match_scratch:DI 3 "=r"))
(clobber (match_scratch:DI 4 "=r"))
- (use (label_ref (match_operand 2 "" "")))])]
+ (use (label_ref:DI (match_operand 2 "" "")))])]
""
"*
return aarch64_output_casesi (operands);

60
gcc9-pr89490.patch Normal file
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@ -0,0 +1,60 @@
2019-02-27 Bernd Edlinger <bernd.edlinger@hotmail.de>
PR rtl-optimization/89490
* varasm.c (get_block_for_section): Bail out for mergeable sections.
(default_use_anchors_for_symbol_p, output_object_block): Assert the
block section is not mergeable.
--- gcc/varasm.c.orig 2019-02-21 23:50:24.000000000 +0100
+++ gcc/varasm.c 2019-02-27 11:33:32.741967812 +0100
@@ -363,7 +363,11 @@ use_object_blocks_p (void)
/* Return the object_block structure for section SECT. Create a new
structure if we haven't created one already. Return null if SECT
- itself is null. */
+ itself is null. Return also null for mergeable sections since
+ section anchors can't be used in mergeable sections anyway,
+ because the linker might move objects around, and using the
+ object blocks infrastructure in that case is both a waste and a
+ maintenance burden. */
static struct object_block *
get_block_for_section (section *sect)
@@ -373,6 +377,9 @@ get_block_for_section (section *sect)
if (sect == NULL)
return NULL;
+ if (sect->common.flags & SECTION_MERGE)
+ return NULL;
+
object_block **slot
= object_block_htab->find_slot_with_hash (sect, hash_section (sect),
INSERT);
@@ -7014,14 +7021,13 @@ default_asm_output_anchor (rtx symbol)
bool
default_use_anchors_for_symbol_p (const_rtx symbol)
{
- section *sect;
tree decl;
+ section *sect = SYMBOL_REF_BLOCK (symbol)->sect;
- /* Don't use anchors for mergeable sections. The linker might move
- the objects around. */
- sect = SYMBOL_REF_BLOCK (symbol)->sect;
- if (sect->common.flags & SECTION_MERGE)
- return false;
+ /* This function should only be called with non-zero SYMBOL_REF_BLOCK,
+ furthermore get_block_for_section should not create object blocks
+ for mergeable sections. */
+ gcc_checking_assert (sect && !(sect->common.flags & SECTION_MERGE));
/* Don't use anchors for small data sections. The small data register
acts as an anchor for such sections. */
@@ -7630,6 +7636,7 @@ output_object_block (struct object_block
else
switch_to_section (block->sect);
+ gcc_checking_assert (!(block->sect->common.flags & SECTION_MERGE));
assemble_align (block->alignment);
/* Define the values of all anchors relative to the current section

71
gcc9-pr89506.patch Normal file
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@ -0,0 +1,71 @@
2019-02-26 Jakub Jelinek <jakub@redhat.com>
PR target/89506
* config/arm/arm.md (cmpsi2_addneg): Use
trunc_int_for_mode (-INTVAL (...), SImode) instead of -INTVAL (...).
(*subsi3_carryin_compare_const): Similarly, just instead of -UINTVAL.
(*compare_scc splitter): Use gen_int_mode.
(*negscc): Likewise.
* gcc.dg/pr89506.c: New test.
--- gcc/config/arm/arm.md.jj 2019-02-25 11:32:02.914684615 +0100
+++ gcc/config/arm/arm.md 2019-02-26 14:41:41.128767480 +0100
@@ -867,7 +867,9 @@ (define_insn "cmpsi2_addneg"
(set (match_operand:SI 0 "s_register_operand" "=r,r")
(plus:SI (match_dup 1)
(match_operand:SI 3 "arm_addimm_operand" "I,L")))]
- "TARGET_32BIT && INTVAL (operands[2]) == -INTVAL (operands[3])"
+ "TARGET_32BIT
+ && (INTVAL (operands[2])
+ == trunc_int_for_mode (-INTVAL (operands[3]), SImode))"
"@
adds%?\\t%0, %1, %3
subs%?\\t%0, %1, #%n3"
@@ -1185,7 +1187,9 @@ (define_insn "*subsi3_carryin_compare_co
(minus:SI (plus:SI (match_dup 1)
(match_operand:SI 3 "arm_neg_immediate_operand" "L"))
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
- "TARGET_32BIT && UINTVAL (operands[2]) == -UINTVAL (operands[3])"
+ "TARGET_32BIT
+ && (INTVAL (operands[2])
+ == trunc_int_for_mode (-INTVAL (operands[3]), SImode))"
"sbcs\\t%0, %1, #%n3"
[(set_attr "conds" "set")
(set_attr "type" "adcs_imm")]
@@ -9281,7 +9285,7 @@ (define_split
(cond_exec (ne:CC (reg:CC CC_REGNUM) (const_int 0))
(set (match_dup 0) (const_int 1)))]
{
- operands[3] = GEN_INT (-INTVAL (operands[2]));
+ operands[3] = gen_int_mode (-INTVAL (operands[2]), SImode);
})
(define_split
@@ -10061,7 +10065,8 @@ (define_insn_and_split "*negscc"
/* Emit subs\\t%0, %1, %2\;mvnne\\t%0, #0 */
if (CONST_INT_P (operands[2]))
emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
- GEN_INT (- INTVAL (operands[2]))));
+ gen_int_mode (-INTVAL (operands[2]),
+ SImode)));
else
emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2]));
--- gcc/testsuite/gcc.dg/pr89506.c.jj 2019-02-26 14:45:29.662027068 +0100
+++ gcc/testsuite/gcc.dg/pr89506.c 2019-02-26 14:45:06.570405009 +0100
@@ -0,0 +1,14 @@
+/* PR target/89506 */
+/* { dg-do compile } */
+/* { dg-options "-Og -g -w" } */
+
+long long a;
+int c;
+
+int
+foo (long long d, short e)
+{
+ __builtin_sub_overflow (0xffffffff, c, &a);
+ e >>= ~2147483647 != (int) a;
+ return d + e;
+}

2
sources
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@ -1,3 +1,3 @@
SHA512 (gcc-9.0.1-20190221.tar.xz) = 2a83371869c2b5cc52b789236db2a55cf59294e0a8e7ae1e44d4dac873bbecd7daa33bcd15c0a7bce2941f8c68329de1f88d6ac09effb3c9e04f76902227a3b9 SHA512 (gcc-9.0.1-20190227.tar.xz) = 0d42138bc1d2ac54fabf7e7d680a3492283955b869ec4ab1576e2d88a6d4ee7283e45a16a1b1db14dbdd6096da86461d81461bf8db70c4c65451529c7dc46145
SHA512 (nvptx-newlib-aadc8eb0ec43b7cd0dd2dfb484bae63c8b05ef24.tar.xz) = 94f7089365296f7dfa485107b4143bebc850a81586f3460fd896bbbb6ba099a00217d4042133424fd2183b352132f4fd367e6a60599bdae2a26dfd48a77d0e04 SHA512 (nvptx-newlib-aadc8eb0ec43b7cd0dd2dfb484bae63c8b05ef24.tar.xz) = 94f7089365296f7dfa485107b4143bebc850a81586f3460fd896bbbb6ba099a00217d4042133424fd2183b352132f4fd367e6a60599bdae2a26dfd48a77d0e04
SHA512 (nvptx-tools-c28050f60193b3b95a18866a96f03334e874e78f.tar.xz) = a688cb12cf805950a5abbb13b52f45c81dbee98e310b7ed57ae20e76dbfa5964a16270148374a6426d177db71909d28360490f091c86a5d19d4faa5127beeee1 SHA512 (nvptx-tools-c28050f60193b3b95a18866a96f03334e874e78f.tar.xz) = a688cb12cf805950a5abbb13b52f45c81dbee98e310b7ed57ae20e76dbfa5964a16270148374a6426d177db71909d28360490f091c86a5d19d4faa5127beeee1