10.0.1-0.11
This commit is contained in:
Jakub Jelinek
parent
047162357c
commit
643c97a3d8
1
.gitignore
vendored
1
.gitignore
vendored
@ -8,3 +8,4 @@
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/gcc-10.0.1-20200216.tar.xz
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/gcc-10.0.1-20200311.tar.xz
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/gcc-10.0.1-20200325.tar.xz
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/gcc-10.0.1-20200328.tar.xz
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29
gcc.spec
29
gcc.spec
@ -1,10 +1,10 @@
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%global DATE 20200325
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%global gitrev 17146084e899406b7b39093e945561c737dfe02c
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%global DATE 20200328
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%global gitrev 97ad35f30b0d8ed5376febf09cefa2b93f9dc423
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%global gcc_version 10.0.1
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%global gcc_major 10
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# Note, gcc_release must be integer, if you want to add suffixes to
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# %%{release}, append them after %%{gcc_release} on Release: line.
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%global gcc_release 0.10
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%global gcc_release 0.11
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%global nvptx_tools_gitrev 5f6f343a302d620b0868edab376c00b15741e39e
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%global newlib_cygwin_gitrev 50e2a63b04bdd018484605fbb954fd1bd5147fa0
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%global _unpackaged_files_terminate_build 0
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@ -180,6 +180,7 @@ BuildRequires: gdb
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BuildRequires: glibc-devel >= 2.4.90-13
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BuildRequires: elfutils-devel >= 0.147
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BuildRequires: elfutils-libelf-devel >= 0.147
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BuildRequires: libzstd-devel
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%ifarch ppc ppc64 ppc64le ppc64p7 s390 s390x sparc sparcv9 alpha
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# Make sure glibc supports TFmode long double
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BuildRequires: glibc >= 2.3.90-35
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@ -264,8 +265,8 @@ Patch8: gcc10-foffload-default.patch
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Patch9: gcc10-Wno-format-security.patch
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Patch10: gcc10-rh1574936.patch
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Patch11: gcc10-d-shared-libphobos.patch
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Patch12: gcc10-pr94308.patch
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Patch13: gcc10-pr94254.patch
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Patch12: gcc10-pr93069.patch
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Patch13: gcc10-pr94343.patch
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# On ARM EABI systems, we do want -gnueabi to be part of the
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# target triple.
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@ -777,8 +778,8 @@ to NVidia PTX capable devices if available.
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%patch10 -p0 -b .rh1574936~
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%endif
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%patch11 -p0 -b .d-shared-libphobos~
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%patch12 -p0 -b .pr94308~
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%patch13 -p0 -b .pr94254~
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%patch12 -p0 -b .pr93069~
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%patch13 -p0 -b .pr94343~
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echo 'Red Hat %{version}-%{gcc_release}' > gcc/DEV-PHASE
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@ -3007,6 +3008,20 @@ end
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%endif
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%changelog
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* Sat Mar 28 2020 Jakub Jelinek <jakub@redhat.com> 10.0.1-0.11
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- update from trunk
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- PRs c++/81349, c++/84733, c++/93810, c++/93824, c++/94057, c++/94078,
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c++/94098, c++/94257, c++/94265, c++/94272, c++/94319, c++/94326,
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c++/94336, c++/94339, c++/94346, c/93573, debug/94273, debug/94281,
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debug/94296, debug/94323, fortran/93363, fortran/93957, ipa/94271,
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lto/94259, middle-end/94004, rtl-optimization/92264, target/94145,
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target/94220, target/94292, testsuite/94334, tree-optimization/90332,
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tree-optimization/94131, tree-optimization/94269,
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tree-optimization/94329, tree-optimization/94352
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- fix x86 vec_extract_{lo,hi}*_mask AVX512* patterns (PR target/93069)
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- fix x86 *one_cmpl*2* AVX512* patterns (PR target/94343)
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- add BuildRequires: libzstd-devel
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* Wed Mar 25 2020 Jakub Jelinek <jakub@redhat.com> 10.0.1-0.10
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- update from trunk
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- PRs analyzer/94047, analyzer/94099, analyzer/94105, c++/67960, c++/69694,
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70
gcc10-pr93069.patch
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70
gcc10-pr93069.patch
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2020-03-26 Jakub Jelinek <jakub@redhat.com>
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PR target/93069
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* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
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<store_mask_constraint> instead of m in output operand constraint.
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(vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
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%{%3%}.
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* gcc.target/i386/avx512vl-pr93069.c: New test.
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* gcc.dg/vect/pr93069.c: New test.
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--- gcc/config/i386/sse.md.jj 2019-12-27 18:16:48.146431083 +0100
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+++ gcc/config/i386/sse.md 2019-12-28 14:43:29.181456611 +0100
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@@ -8782,7 +8782,8 @@
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})
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(define_insn "vec_extract_lo_<mode><mask_name>"
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- [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,v,m")
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+ [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
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+ "=v,v,<store_mask_constraint>")
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(vec_select:<ssehalfvecmode>
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(match_operand:V16FI 1 "<store_mask_predicate>"
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"v,<store_mask_constraint>,v")
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@@ -8834,7 +8835,8 @@
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})
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(define_insn "vec_extract_lo_<mode><mask_name>"
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- [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,v,m")
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+ [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
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+ "=v,v,<store_mask_constraint>")
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(vec_select:<ssehalfvecmode>
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(match_operand:VI8F_256 1 "<store_mask_predicate>"
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"v,<store_mask_constraint>,v")
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@@ -8844,7 +8846,7 @@
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&& (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
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{
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if (<mask_applied>)
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- return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}";
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+ return "vextract<shuffletype>64x2\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
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else
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return "#";
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}
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--- gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c.jj 2019-12-28 16:31:30.118695074 +0100
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+++ gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c 2019-12-28 16:32:16.920990539 +0100
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@@ -0,0 +1,12 @@
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+/* PR target/93069 */
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+/* { dg-do assemble { target vect_simd_clones } } */
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+/* { dg-options "-O2 -fopenmp-simd -mtune=skylake-avx512" } */
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+/* { dg-additional-options "-mavx512vl" { target avx512vl } } */
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+/* { dg-additional-options "-mavx512dq" { target avx512dq } } */
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+
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+#pragma omp declare simd
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+int
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+foo (int x, int y)
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+{
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+ return x == 0 ? x : y;
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+}
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--- gcc/testsuite/gcc.dg/vect/pr93069.c.jj 2019-12-28 16:31:01.822121036 +0100
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+++ gcc/testsuite/gcc.dg/vect/pr93069.c 2019-12-28 16:30:35.503517205 +0100
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@@ -0,0 +1,10 @@
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+/* PR target/93069 */
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+/* { dg-do assemble { target vect_simd_clones } } */
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+/* { dg-options "-O2 -fopenmp-simd" } */
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+
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+#pragma omp declare simd
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+int
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+foo (int x, int y)
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+{
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+ return x == 0 ? x : y;
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+}
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@ -1,24 +0,0 @@
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2020-03-23 Richard Sandiford <richard.sandiford@arm.com>
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PR target/94254
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* config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow
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FPRs to change between SDmode and DDmode.
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--- gcc/config/rs6000/rs6000.c
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+++ gcc/config/rs6000/rs6000.c
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@@ -12307,6 +12307,15 @@ rs6000_can_change_mode_class (machine_mode from,
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if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
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return false;
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+ /* Allow SD<->DD changes, since SDmode values are stored in
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+ the low half of the DDmode, just like target-independent
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+ code expects. We need to allow at least SD->DD since
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+ rs6000_secondary_memory_needed_mode asks for that change
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+ to be made for SD reloads. */
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+ if ((to == DDmode && from == SDmode)
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+ || (to == SDmode && from == DDmode))
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+ return true;
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+
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if (from_size < 8 || to_size < 8)
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return false;
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@ -1,52 +0,0 @@
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2020-03-25 Jakub Jelinek <jakub@redhat.com>
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PR target/94308
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* config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
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INSN_CODE (insn) to -1 when changing the pattern.
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* gcc.target/i386/pr94308.c: New test.
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--- gcc/config/i386/i386-features.c.jj 2020-03-17 13:50:52.955933209 +0100
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+++ gcc/config/i386/i386-features.c 2020-03-24 19:19:17.801609289 +0100
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@@ -1792,6 +1792,7 @@ ix86_add_reg_usage_to_vzeroupper (rtx_in
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RTVEC_ELT (vec, j) = gen_rtx_SET (reg, reg);
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}
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XVEC (pattern, 0) = vec;
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+ INSN_CODE (insn) = -1;
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df_insn_rescan (insn);
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}
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--- gcc/testsuite/gcc.target/i386/pr94308.c.jj 2020-03-24 19:32:51.964436310 +0100
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+++ gcc/testsuite/gcc.target/i386/pr94308.c 2020-03-24 19:32:39.848617482 +0100
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@@ -0,0 +1,31 @@
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+/* PR target/94308 */
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mfpmath=sse -mavx2 -mfma" } */
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+
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+#include <x86intrin.h>
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+
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+void
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+foo (float *x, const float *y, const float *z, unsigned int w)
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+{
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+ unsigned int a;
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+ const unsigned int b = w / 8;
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+ const float *c = y;
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+ const float *d = z;
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+ __m256 e = _mm256_setzero_ps ();
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+ __m256 f, g;
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+ for (a = 0; a < b; a++)
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+ {
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+ f = _mm256_loadu_ps (c);
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+ g = _mm256_loadu_ps (d);
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+ c += 8;
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+ d += 8;
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+ e = _mm256_fmadd_ps (f, g, e);
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+ }
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+ __attribute__ ((aligned (32))) float h[8];
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+ _mm256_storeu_ps (h, e);
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+ _mm256_zeroupper ();
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+ float i = h[0] + h[1] + h[2] + h[3] + h[4] + h[5] + h[6] + h[7];
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+ for (a = b * 8; a < w; a++)
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+ i += (*c++) * (*d++);
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+ *x = i;
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+}
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78
gcc10-pr94343.patch
Normal file
78
gcc10-pr94343.patch
Normal file
@ -0,0 +1,78 @@
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2020-03-26 Jakub Jelinek <jakub@redhat.com>
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PR target/94343
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* config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
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!TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
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operand is a register. Don't enable masked variants for V*[QH]Imode.
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* gcc.target/i386/avx512f-pr94343.c: New test.
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* gcc.target/i386/avx512vl-pr94343.c: New test.
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--- gcc/config/i386/sse.md.jj 2020-03-06 11:35:46.284074858 +0100
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+++ gcc/config/i386/sse.md 2020-03-26 18:49:39.644131577 +0100
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@@ -12796,14 +12796,29 @@ (define_expand "one_cmpl<mode>2"
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})
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(define_insn "<mask_codefor>one_cmpl<mode>2<mask_name>"
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- [(set (match_operand:VI 0 "register_operand" "=v")
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- (xor:VI (match_operand:VI 1 "nonimmediate_operand" "vm")
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- (match_operand:VI 2 "vector_all_ones_operand" "BC")))]
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- "TARGET_AVX512F"
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- "vpternlog<ternlogsuffix>\t{$0x55, %1, %0, %0<mask_operand3>|%0<mask_operand3>, %0, %1, 0x55}"
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+ [(set (match_operand:VI 0 "register_operand" "=v,v")
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+ (xor:VI (match_operand:VI 1 "nonimmediate_operand" "v,m")
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+ (match_operand:VI 2 "vector_all_ones_operand" "BC,BC")))]
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+ "TARGET_AVX512F
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+ && (!<mask_applied>
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+ || <ssescalarmode>mode == SImode
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+ || <ssescalarmode>mode == DImode)"
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+{
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+ if (TARGET_AVX512VL)
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+ return "vpternlog<ternlogsuffix>\t{$0x55, %1, %0, %0<mask_operand3>|%0<mask_operand3>, %0, %1, 0x55}";
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+ else
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+ return "vpternlog<ternlogsuffix>\t{$0x55, %g1, %g0, %g0<mask_operand3>|%g0<mask_operand3>, %g0, %g1, 0x55}";
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+}
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[(set_attr "type" "sselog")
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(set_attr "prefix" "evex")
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- (set_attr "mode" "<sseinsnmode>")])
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+ (set (attr "mode")
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+ (if_then_else (match_test "TARGET_AVX512VL")
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+ (const_string "<sseinsnmode>")
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+ (const_string "XI")))
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+ (set (attr "enabled")
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+ (if_then_else (eq_attr "alternative" "1")
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+ (symbol_ref "<MODE_SIZE> == 64 || TARGET_AVX512VL")
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+ (const_int 1)))])
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(define_expand "<sse2_avx2>_andnot<mode>3"
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[(set (match_operand:VI_AVX2 0 "register_operand")
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--- gcc/testsuite/gcc.target/i386/avx512f-pr94343.c.jj 2020-03-26 17:47:40.008654504 +0100
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+++ gcc/testsuite/gcc.target/i386/avx512f-pr94343.c 2020-03-26 17:48:37.169811375 +0100
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@@ -0,0 +1,12 @@
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+/* PR target/94343 */
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mavx512f -mno-avx512vl" } */
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+/* { dg-final { scan-assembler-not "vpternlogd\[^\n\r]*xmm\[0-9]*" } } */
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+
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+typedef int __v4si __attribute__((vector_size (16)));
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+
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+__v4si
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+foo (__v4si a)
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+{
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+ return ~a;
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+}
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--- gcc/testsuite/gcc.target/i386/avx512vl-pr94343.c.jj 2020-03-26 17:48:53.232573115 +0100
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+++ gcc/testsuite/gcc.target/i386/avx512vl-pr94343.c 2020-03-26 17:49:08.034352968 +0100
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@@ -0,0 +1,12 @@
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+/* PR target/94343 */
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mavx512vl" } */
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+/* { dg-final { scan-assembler "vpternlogd\[^\n\r]*xmm\[0-9]*" } } */
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+
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+typedef int __v4si __attribute__((vector_size (16)));
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+
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+__v4si
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+foo (__v4si a)
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+{
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+ return ~a;
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+}
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2
sources
2
sources
@ -1,3 +1,3 @@
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SHA512 (gcc-10.0.1-20200325.tar.xz) = 5431edeeb9ef900ce49e4fa13869c63d84c244f846be96f1e782249b0a4ac3c6d5ce73117bd3fb1d2d786e82d394ec0a5ea5cc4615f8cc61d7f6aa43db6a8ce9
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SHA512 (gcc-10.0.1-20200328.tar.xz) = 567f7b9c7b3ac41465bac0354d94f58ab92abe8a5cc2462551397d4bee6071a90ae79c65a4e1d84f51dde6b8639574606675204c78ce0d16f3fc47c169a4ef60
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SHA512 (newlib-cygwin-50e2a63b04bdd018484605fbb954fd1bd5147fa0.tar.xz) = 9ceea0b883185fe489724d54a7e909bb6ed4785fcadf80162033dc6a133e2657337175601278e4155d1f8fac275ff9c8a02572aea876166c608774c809f832e9
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SHA512 (nvptx-tools-5f6f343a302d620b0868edab376c00b15741e39e.tar.xz) = f6d10db94fa1570ae0f94df073fa3c73c8e5ee16d59070b53d94f7db0de8a031bc44d7f3f1852533da04b625ce758e022263855ed43cfc6867e0708d001e53c7
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