.gcc-toolset-13-gcc.metadata

@@ -1,4 +0,0 @@
-8ebd6709d853b5be064b5a0499927c721ac172f8 SOURCES/gcc-13.2.1-20231205.tar.xz
-ae5fbb33bcb442121fbbf482a93f6b3c84d489ee SOURCES/isl-0.24.tar.bz2
-003af8bc05476507f4dd02340b727b72b404e275 SOURCES/newlib-cygwin-9e09d6ed83cce4777a5950412647ccc603040409.tar.xz
-6bfe7ac1b208935ee2c0939bb47cfe775c1c81b3 SOURCES/nvptx-tools-aa3404ad5a496cda5d79a50bedb1344fd63e8763.tar.xz

.gitignore

@@ -1,4 +1,4 @@
-SOURCES/gcc-13.2.1-20231205.tar.xz
-SOURCES/isl-0.24.tar.bz2
-SOURCES/newlib-cygwin-9e09d6ed83cce4777a5950412647ccc603040409.tar.xz
-SOURCES/nvptx-tools-aa3404ad5a496cda5d79a50bedb1344fd63e8763.tar.xz
+/gcc-13.1.1-20230614.tar.xz
+/gcc-13.2.1-20231205.tar.xz
+/gcc-13.3.1-20240522.tar.xz
+/gcc-13.3.1-20240611.tar.xz

SOURCES/gcc13-pr110792.patch

@@ -1,163 +0,0 @@
-PR target/110792: Early clobber issues with rot32di2_doubleword on i386.
-
-This patch is a conservative fix for PR target/110792, a wrong-code
-regression affecting doubleword rotations by BITS_PER_WORD, which
-effectively swaps the highpart and lowpart words, when the source to be
-rotated resides in memory. The issue is that if the register used to
-hold the lowpart of the destination is mentioned in the address of
-the memory operand, the current define_insn_and_split unintentionally
-clobbers it before reading the highpart.
-
-Hence, for the testcase, the incorrectly generated code looks like:
-
-	salq    $4, %rdi                // calculate address
-	movq    WHIRL_S+8(%rdi), %rdi   // accidentally clobber addr
-	movq    WHIRL_S(%rdi), %rbp     // load (wrong) lowpart
-
-Traditionally, the textbook way to fix this would be to add an
-explicit early clobber to the instruction's constraints.
-
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
-        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-                       (const_int 32)))]
-
-but unfortunately this currently generates significantly worse code,
-due to a strange choice of reloads (effectively memcpy), which ends up
-looking like:
-
-	salq    $4, %rdi                // calculate address
-	movdqa  WHIRL_S(%rdi), %xmm0    // load the double word in SSE reg.
-	movaps  %xmm0, -16(%rsp)        // store the SSE reg back to the stack
-	movq    -8(%rsp), %rdi          // load highpart
-	movq    -16(%rsp), %rbp         // load lowpart
-
-Note that reload's "&" doesn't distinguish between the memory being
-early clobbered, vs the registers used in an addressing mode being
-early clobbered.
-    
-The fix proposed in this patch is to remove the third alternative, that
-allowed offsetable memory as an operand, forcing reload to place the
-operand into a register before the rotation.  This results in:
-
-	salq    $4, %rdi
-	movq    WHIRL_S(%rdi), %rax
-	movq    WHIRL_S+8(%rdi), %rdi
-	movq    %rax, %rbp
-
-I believe there's a more advanced solution, by swapping the order of
-the loads (if first destination register is mentioned in the address),
-or inserting a lea insn (if both destination registers are mentioned
-in the address), but this fix is a minimal "safe" solution, that
-should hopefully be suitable for backporting.
-
-2023-08-06  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/testsuite/ChangeLog
-	PR target/110792
-	* gcc.target/i386/pr110792.c: Remove dg-final scan-assembler-not.
-
-2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/ChangeLog
-        PR target/110792
-        * config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
-        place operand in a register before gen_<insn>64ti2_doubleword.
-        (<any_rotate>di3): Likewise, for rotations by 32 bits, place
-        operand in a register before gen_<insn>32di2_doubleword.
-        (<any_rotate>32di2_doubleword): Constrain operand to be in register.
-        (<any_rotate>64ti2_doubleword): Likewise.
-
-gcc/testsuite/ChangeLog
-        PR target/110792
-        * g++.target/i386/pr110792.C: New 32-bit C++ test case.
-        * gcc.target/i386/pr110792.c: New 64-bit C test case.
-
---- gcc/config/i386/i386.md
-+++ gcc/config/i386/i386.md
-@@ -15341,7 +15341,10 @@ (define_expand "<insn>ti3"
-     emit_insn (gen_ix86_<insn>ti3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
--    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (TImode, operands[1]);
-+      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     {
-       rtx amount = force_reg (QImode, operands[2]);
-@@ -15376,7 +15379,10 @@ (define_expand "<insn>di3"
-     emit_insn (gen_ix86_<insn>di3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
--    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (DImode, operands[1]);
-+      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     FAIL;
- 
-@@ -15544,8 +15550,8 @@ (define_insn_and_split "ix86_rotr<dwi>3_doubleword"
- })
- 
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
--       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r")
-+       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
-                       (const_int 32)))]
-  "!TARGET_64BIT"
-  "#"
-@@ -15562,8 +15568,8 @@ (define_insn_and_split "<insn>32di2_doubleword"
- })
- 
- (define_insn_and_split "<insn>64ti2_doubleword"
-- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
--       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:TI 0 "register_operand" "=r,r")
-+       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
-                       (const_int 64)))]
-  "TARGET_64BIT"
-  "#"
---- gcc/testsuite/g++.target/i386/pr110792.C
-+++ gcc/testsuite/g++.target/i386/pr110792.C
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target ia32 } } */
-+/* { dg-options "-O2" } */
-+
-+template <int ROT, typename T>
-+inline T rotr(T input)
-+{
-+   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
-+}
-+
-+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
-+unsigned long long whirl(unsigned char x0)
-+{
-+   const unsigned long long s4 = WHIRL_S[x0&0xFF];
-+   return rotr<32>(s4);
-+}
-+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
---- gcc/testsuite/gcc.target/i386/pr110792.c
-+++ gcc/testsuite/gcc.target/i386/pr110792.c
-@@ -0,0 +1,17 @@
-+/* { dg-do compile { target int128 } } */
-+/* { dg-options "-O2" } */
-+
-+static inline unsigned __int128 rotr(unsigned __int128 input)
-+{
-+   return ((input >> 64) | (input << (64)));
-+}
-+
-+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
-+unsigned __int128 whirl(unsigned char x0)
-+{
-+   register int t __asm("rdi") = x0&0xFF;
-+   const unsigned __int128 s4 = WHIRL_S[t];
-+   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
-+   asm("":::"memory");
-+   return tt;
-+}

SOURCES/gcc13-testsuite-aarch64-add-fno-stack-protector.patch

@@ -1,500 +0,0 @@
-From 3439b79cb7f97464d65316a94d40d49505fb2150 Mon Sep 17 00:00:00 2001
-From: Marek Polacek <polacek@redhat.com>
-Date: Wed, 6 Dec 2023 15:34:24 -0500
-Subject: [PATCH] aarch64: add -fno-stack-protector to tests
-
-These tests fail when the testsuite is executed with -fstack-protector-strong.
-To avoid this, this patch adds -fno-stack-protector to dg-options.
-
-The list of FAILs is appended.  As you can see, it's mostly about
-scan-assembler-* which are sort of expected to fail with the stack
-protector on.
-
-FAIL: gcc.target/aarch64/ldp_stp_unaligned_2.c scan-assembler-not mov\\tx[0-9]+, sp
-FAIL: gcc.target/aarch64/shadow_call_stack_5.c scan-assembler-times stp\\\\tx29, x30, \\\\[sp\\\\] 1
-FAIL: gcc.target/aarch64/shadow_call_stack_5.c scan-assembler ldr\\\\tx29, \\\\[sp\\\\]
-FAIL: gcc.target/aarch64/shadow_call_stack_6.c scan-assembler-times str\\\\tx30, \\\\[sp\\\\] 1
-FAIL: gcc.target/aarch64/shadow_call_stack_7.c scan-assembler-times stp\\\\tx19, x30, \\\\[sp, -[0-9]+\\\\]! 1
-FAIL: gcc.target/aarch64/shadow_call_stack_7.c scan-assembler ldr\\\\tx19, \\\\[sp\\\\], [0-9]+
-FAIL: gcc.target/aarch64/shadow_call_stack_8.c scan-assembler-times stp\\\\tx19, x20, \\\\[sp, -[0-9]+\\\\]! 1
-FAIL: gcc.target/aarch64/shadow_call_stack_8.c scan-assembler ldp\\\\tx19, x20, \\\\[sp\\\\], [0-9]+
-FAIL: gcc.target/aarch64/stack-check-12.c scan-assembler-times str\\\\txzr,  2
-FAIL: gcc.target/aarch64/stack-check-prologue-11.c scan-assembler-times str\\\\s+xzr, \\\\[sp, 1024\\\\] 1
-FAIL: gcc.target/aarch64/stack-check-prologue-12.c scan-assembler-times str\\\\s+xzr, \\\\[sp, 1024\\\\] 1
-FAIL: gcc.target/aarch64/stack-check-prologue-13.c scan-assembler-times str\\\\s+xzr, \\\\[sp, 1024\\\\] 1
-FAIL: gcc.target/aarch64/stack-check-prologue-13.c scan-assembler-times str\\\\s+x30, \\\\[sp\\\\] 1
-FAIL: gcc.target/aarch64/stack-check-prologue-14.c scan-assembler-times str\\\\s+xzr, \\\\[sp, 1024\\\\] 1
-FAIL: gcc.target/aarch64/stack-check-prologue-14.c scan-assembler-times str\\\\s+x30, \\\\[sp\\\\] 1
-FAIL: gcc.target/aarch64/stack-check-prologue-15.c scan-assembler-times str\\\\s+xzr, \\\\[sp, 1024\\\\] 1
-FAIL: gcc.target/aarch64/stack-check-prologue-15.c scan-assembler-times str\\\\s+x30, \\\\[sp\\\\] 1
-FAIL: gcc.target/aarch64/stack-check-prologue-17.c check-function-bodies test1
-FAIL: gcc.target/aarch64/stack-check-prologue-17.c check-function-bodies test2
-FAIL: gcc.target/aarch64/stack-check-prologue-18.c check-function-bodies test1
-FAIL: gcc.target/aarch64/stack-check-prologue-18.c check-function-bodies test2
-FAIL: gcc.target/aarch64/stack-check-prologue-18.c check-function-bodies test3
-FAIL: gcc.target/aarch64/stack-check-prologue-19.c check-function-bodies test1
-FAIL: gcc.target/aarch64/stack-check-prologue-19.c check-function-bodies test2
-FAIL: gcc.target/aarch64/stack-check-prologue-19.c check-function-bodies test3
-FAIL: gcc.target/aarch64/stack-check-prologue-2.c scan-assembler-times str\\\\s+xzr, 0
-FAIL: gcc.target/aarch64/stack-check-prologue-5.c scan-assembler-times str\\\\s+xzr, \\\\[sp, 1024\\\\] 1
-FAIL: gcc.target/aarch64/stack-check-prologue-6.c scan-assembler-times str\\\\s+xzr, \\\\[sp, 1024\\\\] 1
-FAIL: gcc.target/aarch64/stack-check-prologue-8.c scan-assembler-times str\\\\s+xzr, \\\\[sp, 1024\\\\] 2
-FAIL: gcc.target/aarch64/stack-check-prologue-9.c scan-assembler-times str\\\\s+xzr, \\\\[sp, 1024\\\\] 1
-FAIL: gcc.target/aarch64/test_frame_1.c scan-assembler-times str\\tx30, \\\\[sp, -[0-9]+\\\\]! 2
-FAIL: gcc.target/aarch64/test_frame_10.c scan-assembler-times stp\\tx19, x30, \\\\[sp, [0-9]+\\\\] 1
-FAIL: gcc.target/aarch64/test_frame_10.c scan-assembler ldp\\tx19, x30, \\\\[sp, [0-9]+\\\\]
-FAIL: gcc.target/aarch64/test_frame_11.c scan-assembler-times stp\\tx29, x30, \\\\[sp, -[0-9]+\\\\]! 2
-FAIL: gcc.target/aarch64/test_frame_13.c scan-assembler-times stp\\tx29, x30, \\\\[sp\\\\] 1
-FAIL: gcc.target/aarch64/test_frame_15.c scan-assembler-times stp\\tx29, x30, \\\\[sp, [0-9]+\\\\] 1
-FAIL: gcc.target/aarch64/test_frame_2.c scan-assembler-times stp\\tx19, x30, \\\\[sp, -[0-9]+\\\\]! 1
-FAIL: gcc.target/aarch64/test_frame_2.c scan-assembler ldp\\tx19, x30, \\\\[sp\\\\], [0-9]+
-FAIL: gcc.target/aarch64/test_frame_4.c scan-assembler-times stp\\tx19, x30, \\\\[sp, -[0-9]+\\\\]! 1
-FAIL: gcc.target/aarch64/test_frame_4.c scan-assembler ldp\\tx19, x30, \\\\[sp\\\\], [0-9]+
-FAIL: gcc.target/aarch64/test_frame_6.c scan-assembler-times str\\tx30, \\\\[sp\\\\] 1
-FAIL: gcc.target/aarch64/test_frame_7.c scan-assembler-times stp\\tx19, x30, \\\\[sp] 1
-FAIL: gcc.target/aarch64/test_frame_8.c scan-assembler-times str\\tx30, \\\\[sp, [0-9]+\\\\] 1
-FAIL: gcc.target/aarch64/test_frame_8.c scan-assembler ldr\\tx30, \\\\[sp, [0-9]+\\\\]
-FAIL: gcc.target/aarch64/sve/struct_vect_24.c scan-assembler-times cmp\\\\s+x[0-9]+, 61440 4
-FAIL: gcc.target/aarch64/sve/struct_vect_24.c scan-assembler-times sub\\\\s+x[0-9]+, x[0-9]+, 61440 4
-FAIL: gcc.target/aarch64/sve/struct_vect_24.c scan-assembler-times cmp\\s+x[0-9]+, 61440 4
-FAIL: gcc.target/aarch64/sve/struct_vect_24.c scan-assembler-times sub\\s+x[0-9]+, x[0-9]+, 61440 4
-
-gcc/testsuite/ChangeLog:
-
-	* gcc.target/aarch64/ldp_stp_unaligned_2.c: Use -fno-stack-protector.
-	* gcc.target/aarch64/shadow_call_stack_5.c: Likewise.
-	* gcc.target/aarch64/shadow_call_stack_6.c: Likewise.
-	* gcc.target/aarch64/shadow_call_stack_7.c: Likewise.
-	* gcc.target/aarch64/shadow_call_stack_8.c: Likewise.
-	* gcc.target/aarch64/stack-check-12.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-11.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-12.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-13.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-14.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-15.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-17.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-18.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-19.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-2.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-5.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-6.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-8.c: Likewise.
-	* gcc.target/aarch64/stack-check-prologue-9.c: Likewise.
-	* gcc.target/aarch64/sve/struct_vect_24.c: Likewise.
-	* gcc.target/aarch64/test_frame_1.c: Likewise.
-	* gcc.target/aarch64/test_frame_10.c: Likewise.
-	* gcc.target/aarch64/test_frame_11.c: Likewise.
-	* gcc.target/aarch64/test_frame_13.c: Likewise.
-	* gcc.target/aarch64/test_frame_15.c: Likewise.
-	* gcc.target/aarch64/test_frame_2.c: Likewise.
-	* gcc.target/aarch64/test_frame_4.c: Likewise.
-	* gcc.target/aarch64/test_frame_6.c: Likewise.
-	* gcc.target/aarch64/test_frame_7.c: Likewise.
-	* gcc.target/aarch64/test_frame_8.c: Likewise.
----
- gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c     | 2 +-
- gcc/testsuite/gcc.target/aarch64/shadow_call_stack_5.c     | 2 +-
- gcc/testsuite/gcc.target/aarch64/shadow_call_stack_6.c     | 2 +-
- gcc/testsuite/gcc.target/aarch64/shadow_call_stack_7.c     | 2 +-
- gcc/testsuite/gcc.target/aarch64/shadow_call_stack_8.c     | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-12.c          | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-11.c | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-12.c | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-13.c | 4 ++--
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-14.c | 4 ++--
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-15.c | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-17.c | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-18.c | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-2.c  | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-5.c  | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-6.c  | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-8.c  | 2 +-
- gcc/testsuite/gcc.target/aarch64/stack-check-prologue-9.c  | 2 +-
- gcc/testsuite/gcc.target/aarch64/sve/struct_vect_24.c      | 2 +-
- gcc/testsuite/gcc.target/aarch64/test_frame_1.c            | 2 +-
- gcc/testsuite/gcc.target/aarch64/test_frame_10.c           | 2 +-
- gcc/testsuite/gcc.target/aarch64/test_frame_11.c           | 2 +-
- gcc/testsuite/gcc.target/aarch64/test_frame_13.c           | 2 +-
- gcc/testsuite/gcc.target/aarch64/test_frame_15.c           | 2 +-
- gcc/testsuite/gcc.target/aarch64/test_frame_2.c            | 2 +-
- gcc/testsuite/gcc.target/aarch64/test_frame_4.c            | 2 +-
- gcc/testsuite/gcc.target/aarch64/test_frame_6.c            | 2 +-
- gcc/testsuite/gcc.target/aarch64/test_frame_7.c            | 2 +-
- gcc/testsuite/gcc.target/aarch64/test_frame_8.c            | 2 +-
- 30 files changed, 32 insertions(+), 32 deletions(-)
-
-diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c
-index 1e46755a39a..50d7d7a2d5d 100644
---- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c
-+++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c
-@@ -1,4 +1,4 @@
--/* { dg-options "-O2 -fomit-frame-pointer" } */
-+/* { dg-options "-O2 -fomit-frame-pointer -fno-stack-protector" } */
- 
- /* Check that we split unaligned LDP/STP into base and aligned offset.  */
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_5.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_5.c
-index d88357ca04d..d7f82984ff5 100644
---- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_5.c
-+++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_5.c
-@@ -7,7 +7,7 @@
-      * optimized code should use "ldr	x29, [sp]" to restore x29 only.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O2 -fno-omit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps" } */
-+/* { dg-options "-O2 -fno-omit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_6.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_6.c
-index 83b74834c6a..8d088aecc20 100644
---- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_6.c
-+++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_6.c
-@@ -7,7 +7,7 @@
-      * optimized code should not restore x30 in epilogue.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O2 -fomit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps" } */
-+/* { dg-options "-O2 -fomit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_7.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_7.c
-index 5537fb3293a..a2f376e0091 100644
---- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_7.c
-+++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_7.c
-@@ -7,7 +7,7 @@
-      * optimized code should use "ldr   x19, [sp], x" to restore x19 only.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O2 -fomit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps" } */
-+/* { dg-options "-O2 -fomit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_8.c b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_8.c
-index b03f26f7bcf..5162cbb3917 100644
---- a/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_8.c
-+++ b/gcc/testsuite/gcc.target/aarch64/shadow_call_stack_8.c
-@@ -9,7 +9,7 @@
-      * optimized code should not restore x30 in epilogue.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O0 -fomit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps" } */
-+/* { dg-options "-O0 -fomit-frame-pointer -fsanitize=shadow-call-stack -fno-exceptions -ffixed-x18 --save-temps -fno-stack-protector" } */
- 
- int func1 (void)
- {
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-12.c b/gcc/testsuite/gcc.target/aarch64/stack-check-12.c
-index be5a57a9ec6..e1a4c67b041 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-12.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-12.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fno-asynchronous-unwind-tables -fno-unwind-tables" } */
-+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-stack-protector" } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
- 
- typedef unsigned __attribute__((mode(DI))) uint64_t;
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-11.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-11.c
-index 741f2f5fadc..d57aece05bb 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-11.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-11.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16" } */
-+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fno-stack-protector" } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
- 
- #define SIZE (6 * 64 * 1024) + (1 * 32 * 1024)
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-12.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-12.c
-index ece68003ade..895d130e4fa 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-12.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-12.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fomit-frame-pointer -momit-leaf-frame-pointer" } */
-+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fomit-frame-pointer -momit-leaf-frame-pointer -fno-stack-protector" } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
- 
- void
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-13.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-13.c
-index 0fc900c6943..1f1a6c497be 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-13.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-13.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fomit-frame-pointer -momit-leaf-frame-pointer" } */
-+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fomit-frame-pointer -momit-leaf-frame-pointer -fno-stack-protector" } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
- 
- void h (void) __attribute__ ((noreturn));
-@@ -17,4 +17,4 @@ f (void)
- 
- /* SIZE is more than 1 guard-size, but only one 64KB page is used, expect only 1
-    probe.  Leaf function and omitting leaf pointers, tail call to noreturn which
--   may only omit an epilogue and not a prologue.  Checking for LR saving.  */
-\ No newline at end of file
-+   may only omit an epilogue and not a prologue.  Checking for LR saving.  */
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-14.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-14.c
-index ea733f861e7..facb3cb72a7 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-14.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-14.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fomit-frame-pointer -momit-leaf-frame-pointer" } */
-+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fomit-frame-pointer -momit-leaf-frame-pointer -fno-stack-protector" } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
- 
- void h (void) __attribute__ ((noreturn));
-@@ -21,4 +21,4 @@ f (void)
-    probe at 1024 and one implicit probe due to LR being saved.  Leaf function
-    and omitting leaf pointers, tail call to noreturn which may only omit an
-    epilogue and not a prologue and control flow in between.  Checking for
--   LR saving.  */
-\ No newline at end of file
-+   LR saving.  */
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-15.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-15.c
-index 63df4a5609a..f2ac60a6214 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-15.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-15.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fomit-frame-pointer -momit-leaf-frame-pointer" } */
-+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fomit-frame-pointer -momit-leaf-frame-pointer -fno-stack-protector" } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
- 
- void g (volatile int *x) ;
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-17.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-17.c
-index f0ec1389771..1cf6fbbb085 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-17.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-17.c
-@@ -1,4 +1,4 @@
--/* { dg-options "-O2 -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12" } */
-+/* { dg-options "-O2 -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12 -fno-stack-protector" } */
- /* { dg-final { check-function-bodies "**" "" } } */
- 
- void f(int, ...);
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-18.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-18.c
-index 6383bec5ebc..2e06346c158 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-18.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-18.c
-@@ -1,4 +1,4 @@
--/* { dg-options "-O2 -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12" } */
-+/* { dg-options "-O2 -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12 -fno-stack-protector" } */
- /* { dg-final { check-function-bodies "**" "" } } */
- 
- void f(int, ...);
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c
-index 562039b5e9b..38eab4d36ab 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c
-@@ -1,4 +1,4 @@
--/* { dg-options "-O2 -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12 -fsanitize=shadow-call-stack -ffixed-x18" } */
-+/* { dg-options "-O2 -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12 -fsanitize=shadow-call-stack -ffixed-x18 -fno-stack-protector" } */
- /* { dg-final { check-function-bodies "**" "" } } */
- 
- void f(int, ...);
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-2.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-2.c
-index 61c52a251a7..b37f62cad27 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-2.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-2.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16" } */
-+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fno-stack-protector" } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
- 
- #define SIZE 2 * 1024
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-5.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-5.c
-index 2ee16350127..34a438671d0 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-5.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-5.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16" } */
-+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fno-stack-protector" } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
- 
- #define SIZE 64 * 1024
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-6.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-6.c
-index 3c9b606cbe0..a4e34e2fe6a 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-6.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-6.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16" } */
-+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fno-stack-protector" } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
- 
- #define SIZE 65 * 1024
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-8.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-8.c
-index 333f5fcc360..277dce4c71e 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-8.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-8.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16" } */
-+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fno-stack-protector" } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
- 
- #define SIZE 128 * 1024
-diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-9.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-9.c
-index a3ff89b5581..a21305541c1 100644
---- a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-9.c
-+++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-9.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16" } */
-+/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fno-stack-protector" } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
- 
- #define SIZE 6 * 64 * 1024
-diff --git a/gcc/testsuite/gcc.target/aarch64/sve/struct_vect_24.c b/gcc/testsuite/gcc.target/aarch64/sve/struct_vect_24.c
-index 68a9d5e3d2e..19be6de0c2e 100644
---- a/gcc/testsuite/gcc.target/aarch64/sve/struct_vect_24.c
-+++ b/gcc/testsuite/gcc.target/aarch64/sve/struct_vect_24.c
-@@ -1,6 +1,6 @@
- /* { dg-do compile } */
- /* { dg-require-effective-target supports_stack_clash_protection } */
--/* { dg-options "-O3 -fopenmp-simd -fstack-clash-protection --param stack-clash-protection-guard-size=16" } */
-+/* { dg-options "-O3 -fopenmp-simd -fstack-clash-protection --param stack-clash-protection-guard-size=16 -fno-stack-protector" } */
- 
- #include <stdint.h>
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_1.c b/gcc/testsuite/gcc.target/aarch64/test_frame_1.c
-index f906b073545..c9b8822b4b1 100644
---- a/gcc/testsuite/gcc.target/aarch64/test_frame_1.c
-+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_1.c
-@@ -6,7 +6,7 @@
-      * optimized code should use "str !" for stack adjustment.  */
- 
- /* { dg-do run } */
--/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_10.c b/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
-index c54ab2d0ccb..fe5cbd9ed05 100644
---- a/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
-+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
-@@ -7,7 +7,7 @@
-      * Use a single stack adjustment, no writeback.  */
- 
- /* { dg-do run } */
--/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_11.c b/gcc/testsuite/gcc.target/aarch64/test_frame_11.c
-index f162cc091e0..11cf471168d 100644
---- a/gcc/testsuite/gcc.target/aarch64/test_frame_11.c
-+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_11.c
-@@ -5,7 +5,7 @@
-      * optimized code should use "stp !" for stack adjustment.  */
- 
- /* { dg-do run } */
--/* { dg-options "-O2 --save-temps" } */
-+/* { dg-options "-O2 --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_13.c b/gcc/testsuite/gcc.target/aarch64/test_frame_13.c
-index 74b3370fa46..ec56963c038 100644
---- a/gcc/testsuite/gcc.target/aarch64/test_frame_13.c
-+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_13.c
-@@ -5,7 +5,7 @@
-      * Use a single stack adjustment, no writeback.  */
- 
- /* { dg-do run } */
--/* { dg-options "-O2 --save-temps" } */
-+/* { dg-options "-O2 --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_15.c b/gcc/testsuite/gcc.target/aarch64/test_frame_15.c
-index bed6714b4fe..4247008de8e 100644
---- a/gcc/testsuite/gcc.target/aarch64/test_frame_15.c
-+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_15.c
-@@ -6,7 +6,7 @@
-      * Use a single stack adjustment, no writeback.  */
- 
- /* { dg-do run } */
--/* { dg-options "-O2 --save-temps" } */
-+/* { dg-options "-O2 --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_2.c b/gcc/testsuite/gcc.target/aarch64/test_frame_2.c
-index 0d715314cb8..9c4243b6480 100644
---- a/gcc/testsuite/gcc.target/aarch64/test_frame_2.c
-+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_2.c
-@@ -6,7 +6,7 @@
-      * optimized code should use "stp !" for stack adjustment.  */
- 
- /* { dg-do run } */
--/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_4.c b/gcc/testsuite/gcc.target/aarch64/test_frame_4.c
-index b41229c42f4..8d0bed93e44 100644
---- a/gcc/testsuite/gcc.target/aarch64/test_frame_4.c
-+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_4.c
-@@ -6,7 +6,7 @@
-      * we can use "stp !" to optimize stack adjustment.  */
- 
- /* { dg-do run } */
--/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_6.c b/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
-index 56259c945d2..2944a8bbe16 100644
---- a/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
-+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
-@@ -6,7 +6,7 @@
-      * use a single stack adjustment, no writeback.  */
- 
- /* { dg-do run } */
--/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_7.c b/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
-index 5702656a5da..ca371632d81 100644
---- a/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
-+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
-@@ -6,7 +6,7 @@
-      * use a single stack adjustment, no writeback.  */
- 
- /* { dg-do run } */
--/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_8.c b/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
-index 75a68b41e08..084e8fac373 100644
---- a/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
-+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
-@@ -5,7 +5,7 @@
-      * number of callee-saved reg == 1.  */
- 
- /* { dg-do run } */
--/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
-+/* { dg-options "-O2 -fomit-frame-pointer --save-temps -fno-stack-protector" } */
- 
- #include "test_frame_common.h"
- 
-
-base-commit: 1bd15d87031e8bf8fe9585fbc166b315303f676c
--- 
-2.43.0
-

gating.yaml

@@ -0,0 +1,6 @@
+--- !Policy
+product_versions:
+  - rhel-8
+decision_context: osci_compose_gate
+rules:
+  - !PassingTestCaseRule {test_case_name: baseos-ci.brew-build.tier1.functional}

gcc.spec

@@ -5,13 +5,13 @@ BuildRequires: scl-utils-build
 %{?scl:%global __strip %%{_scl_root}/usr/bin/strip}
 %{?scl:%global __objdump %%{_scl_root}/usr/bin/objdump}
 %{?scl:%scl_package gcc}
-%global DATE 20231205
-%global gitrev f783814ad6a04ae5ef44595216596a2b75eda15b
-%global gcc_version 13.2.1
+%global DATE 20240611
+%global gitrev 03b1a31f9807251f378fcecb29c4669eed357eb2
+%global gcc_version 13.3.1
 %global gcc_major 13
 # Note, gcc_release must be integer, if you want to add suffixes to
 # %%{release}, append them after %%{gcc_release} on Release: line.
-%global gcc_release 6
+%global gcc_release 2
 %global nvptx_tools_gitrev aa3404ad5a496cda5d79a50bedb1344fd63e8763
 %global newlib_cygwin_gitrev 9e09d6ed83cce4777a5950412647ccc603040409
 %global mpc_version 1.0.3
@@ -146,10 +146,10 @@ BuildRequires: scl-utils-build
 %else
 %global build_annobin_plugin 0
 %endif
-Summary: GCC version 13
+Summary: GCC version %{gcc_major}
 Name: %{?scl_prefix}gcc
 Version: %{gcc_version}
-Release: %{gcc_release}.3%{?dist}
+Release: %{gcc_release}.1%{?dist}
 # libgcc, libgfortran, libgomp, libstdc++ and crtstuff have
 # GCC Runtime Exception.
 License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD
@@ -329,7 +329,11 @@ Patch8: gcc13-no-add-needed.patch
 Patch9: gcc13-Wno-format-security.patch
 Patch10: gcc13-rh1574936.patch
 Patch11: gcc13-d-shared-libphobos.patch
-Patch12: gcc13-pr110792.patch
+Patch12: gcc13-znver5.patch
+Patch13: gcc13-pr107071.patch
+Patch14: gcc13-vector-merge-1.patch
+Patch15: gcc13-vector-merge-2.patch
+Patch16: gcc13-vector-merge-3.patch
 
 Patch50: isl-rh2155127.patch
 
@@ -361,7 +365,6 @@ Patch3018: 0021-libstdc++-disable-tests.patch
 Patch3019: 0022-libstdc++-revert-behavior.patch
 Patch3021: gcc13-testsuite-p10.patch
 Patch3023: gcc13-testsuite-dwarf.patch
-Patch3024: gcc13-testsuite-aarch64-add-fno-stack-protector.patch
 
 %if 0%{?rhel} == 9
 %global nonsharedver 110
@@ -392,10 +395,11 @@ Patch3024: gcc13-testsuite-aarch64-add-fno-stack-protector.patch
 %endif
 
 %description
-The %{?scl_prefix}gcc%{!?scl:13} package contains the GNU Compiler Collection version 10.
+The %{?scl_prefix}gcc%{!?scl:13} package contains the GNU Compiler Collection
+version %{gcc_major}.
 
 %package -n libgcc
-Summary: GCC version 13 shared support library
+Summary: GCC version %{gcc_major} shared support library
 Autoreq: false
 
 %description -n libgcc
@@ -403,7 +407,7 @@ This package contains GCC shared support library which is needed
 e.g. for exception handling support.
 
 %package c++
-Summary: C++ support for GCC version 13
+Summary: C++ support for GCC version %{gcc_major}
 Requires: %{?scl_prefix}gcc%{!?scl:13} = %{version}-%{release}
 Requires: libstdc++
 Requires: %{?scl_prefix}libstdc++%{!?scl:13}-devel = %{version}-%{release}
@@ -411,8 +415,8 @@ Autoreq: true
 
 %description c++
 This package adds C++ support to the GNU Compiler Collection
-version 13.  It includes support for most of the current C++ specification
-and a lot of support for the upcoming C++ specification.
+version %{gcc_major}.  It includes support for most of the current C++
+specification and a lot of support for the upcoming C++ specification.
 
 %package -n libstdc++
 Summary: GNU Standard C++ Library
@@ -442,7 +446,7 @@ Manual, doxygen generated API information and Frequently Asked Questions
 for the GNU standard C++ library.
 
 %package gfortran
-Summary: Fortran support for GCC 13
+Summary: Fortran support for GCC %{gcc_major}
 Requires: %{?scl_prefix}gcc%{!?scl:13} = %{version}-%{release}
 %if 0%{?rhel} > 7
 Requires: libgfortran >= 8.1.1
@@ -465,18 +469,18 @@ programs with the GNU Compiler Collection.
 
 
 %package gdb-plugin
-Summary: GCC 13 plugin for GDB
+Summary: GCC %{gcc_major} plugin for GDB
 Requires: %{?scl_prefix}gcc%{!?scl:13} = %{version}-%{release}
 
 %description gdb-plugin
-This package contains GCC 13 plugin for GDB C expression evaluation.
+This package contains GCC %{gcc_major} plugin for GDB C expression evaluation.
 
 %package -n %{?scl_prefix}libgccjit
 Summary: Library for embedding GCC inside programs and libraries
 Requires: %{?scl_prefix}gcc%{!?scl:13} = %{version}-%{release}
 
 %description -n %{?scl_prefix}libgccjit
-This package contains shared library with GCC 13 JIT front-end.
+This package contains shared library with GCC %{gcc_major} JIT front-end.
 
 %package -n %{?scl_prefix}libgccjit-devel
 Summary: Support for embedding GCC inside programs and libraries
@@ -486,7 +490,7 @@ Requires: %{?scl_prefix}libgccjit = %{version}-%{release}
 #Requires: %%{?scl_prefix}libgccjit-docs = %%{version}-%%{release}
 
 %description -n %{?scl_prefix}libgccjit-devel
-This package contains header files for GCC 13 JIT front end.
+This package contains header files for GCC %{gcc_major} JIT front end.
 
 %package -n %{?scl_prefix}libgccjit-docs
 Summary: Documentation for embedding GCC inside programs and libraries
@@ -500,10 +504,10 @@ Requires(post): /sbin/install-info
 Requires(preun): /sbin/install-info
 
 %description -n %{?scl_prefix}libgccjit-docs
-This package contains documentation for GCC 13 JIT front-end.
+This package contains documentation for GCC %{gcc_major} JIT front-end.
 
 %package -n libquadmath
-Summary: GCC 13 __float128 shared support library
+Summary: GCC %{gcc_major} __float128 shared support library
 Requires(post): /sbin/install-info
 Requires(preun): /sbin/install-info
 
@@ -512,7 +516,7 @@ This package contains GCC shared support library which is needed
 for __float128 math support and for Fortran REAL*16 support.
 
 %package -n %{?scl_prefix}libquadmath-devel
-Summary: GCC 13 __float128 support
+Summary: GCC %{gcc_major} __float128 support
 Group: Development/Libraries
 %if 0%{!?scl:1}
 Requires: %{?scl_prefix}libquadmath%{_isa} = %{version}-%{release}
@@ -553,7 +557,7 @@ Requires: libmpc-devel >= 0.8.1
 
 %description plugin-devel
 This package contains header files and other support files
-for compiling GCC 13 plugins.  The GCC plugin ABI is currently
+for compiling GCC %{gcc_major} plugins.  The GCC plugin ABI is currently
 not stable, so plugins must be rebuilt any time GCC is updated.
 
 %package -n libatomic
@@ -575,10 +579,10 @@ Requires: libatomic%{_isa} >= 4.8.0
 This package contains GNU Atomic static libraries.
 
 %package -n libasan8
-Summary: The Address Sanitizer runtime library from GCC 13
+Summary: The Address Sanitizer runtime library from GCC %{gcc_major}
 
 %description -n libasan8
-This package contains the Address Sanitizer library from GCC 13
+This package contains the Address Sanitizer library from GCC %{gcc_major}
 which is used for -fsanitize=address instrumented programs.
 
 %package -n %{?scl_prefix}libasan-devel
@@ -695,7 +699,11 @@ so that there cannot be any synchronization problems.
 %patch -P10 -p0 -b .rh1574936~
 %endif
 %patch -P11 -p0 -b .d-shared-libphobos~
-%patch -P12 -p0 -b .pr110792~
+%patch -P12 -p1 -b .znver5~
+%patch -P13 -p1 -b .pr107071~
+%patch -P14 -p1 -b .vector-merge-1~
+%patch -P15 -p1 -b .vector-merge-2~
+%patch -P16 -p1 -b .vector-merge-3~
 
 %if 0%{?rhel} >= 6
 %patch -P100 -p1 -b .fortran-fdec-duplicates~
@@ -743,7 +751,6 @@ rm -f libphobos/testsuite/libphobos.gc/forkgc2.d
 %endif
 %patch -P3021 -p1 -b .dts-test-21~
 %patch -P3023 -p1 -b .dts-test-23~
-%patch -P3024 -p1 -b .dts-test-24~
 
 find gcc/testsuite -name \*.pr96939~ | xargs rm -f
 
@@ -1181,7 +1188,8 @@ CC="`$ANNOBIN_FLAGS --build-cc`" CXX="`$ANNOBIN_FLAGS --build-cxx`" \
   CFLAGS="$ANNOBIN_CFLAGS1 $ANNOBIN_CFLAGS2 $ANNOBIN_LDFLAGS" \
   CXXFLAGS="$ANNOBIN_CFLAGS1 `$ANNOBIN_FLAGS --build-includes` $ANNOBIN_CFLAGS2 $ANNOBIN_LDFLAGS" \
   ./configure --with-gcc-plugin-dir=%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/plugin \
-	      --without-annocheck --without-tests --without-docs --disable-rpath --without-debuginfod
+	      --without-annocheck --without-tests --without-docs --disable-rpath --without-debuginfod \
+	      --without-clang-plugin --without-llvm-plugin
 make
 cd ../..
 %endif
@@ -1826,7 +1834,7 @@ ln -sf ../../../%{multilib_32_arch}-%{_vendor}-%{_target_os}%{?_gnu}/%{gcc_major
 %if 0%{?_enable_debug_packages}
 mkdir -p $RPM_BUILD_ROOT%{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/lib/debug%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}
 adirs="$FULLPATH"
-if [ $FULLLPATH -ne $FULLPATH ]; then
+if [ "$FULLLPATH" != "$FULLPATH" ]; then
   adirs="$adirs $FULLLPATH"
 fi
 for f in `find $adirs -maxdepth 1 -a \
@@ -2907,6 +2915,86 @@ fi
 %endif
 
 %changelog
+* Fri Jul 12 2024 Marek Polacek <polacek@redhat.com> 13.3.1-2.1
+- fix wrong RTL patterns for vector merge high/low word on LE (RHEL-45190)
+
+* Tue Jun 11 2024 Marek Polacek <polacek@redhat.com> 13.3.1-2
+- update from releases/gcc-13 branch
+  - PRs ada/114398, ada/114708, c/114493, c++/111529, c++/113598,
+	fortran/110415, fortran/114827, fortran/115150, libstdc++/114940,
+	libstdc++/115269, middle-end/108789, rtl-optimization/114902,
+	rtl-optimization/115092, target/113281, target/113719, target/115297,
+	target/115317, target/115324, tree-optimization/115192,
+	tree-optimization/115307, tree-optimization/115337
+- fix a shell condition (RHEL-40722)
+- backport a fix for modes_1.f90 (RHEL-40234)
+- fix up pointer types to may_alias structures (PR c/114493, RHEL-40244)
+
+* Thu May 30 2024 Marek Polacek <polacek@redhat.com> 13.3.1-1
+- update from releases/gcc-13 branch
+  - GCC 13.3 release
+  - PRs analyzer/104042, analyzer/108171, analyzer/109251, analyzer/109577,
+	analyzer/110014, analyzer/110112, analyzer/110700, analyzer/110882,
+	analyzer/111289, analyzer/112790, analyzer/112889, analyzer/112969,
+	analyzer/113253, analyzer/113333, analyzer/114408, analyzer/114473,
+	bootstrap/106472, bootstrap/114369, c/112571, c/114780, c++/89224,
+	c++/97990, c++/100667, c++/103825, c++/110006, c++/111284, c++/112769,
+	c++/113141, c++/113966, c++/114303, c++/114377, c++/114537,
+	c++/114561, c++/114562, c++/114572, c++/114580, c++/114634,
+	c++/114691, c++/114709, debug/112718, driver/111700, fortran/36337,
+	fortran/50410, fortran/55978, fortran/89462, fortran/93678,
+	fortran/95374, fortran/101135, fortran/102003, fortran/103707,
+	fortran/103715, fortran/103716, fortran/104352, fortran/106987,
+	fortran/106999, fortran/107426, fortran/110987, fortran/112407,
+	fortran/113799, fortran/113866, fortran/113885, fortran/113956,
+	fortran/114001, fortran/114474, fortran/114535, fortran/114739,
+	fortran/114825, fortran/115039, gcov-profile/114115,
+	gcov-profile/114715, ipa/92606, ipa/108007, ipa/111571, ipa/112616,
+	ipa/113359, ipa/113907, ipa/113964, jit/110466, libgcc/111731,
+	libquadmath/114533, libstdc++/66146, libstdc++/93672,
+	libstdc++/104606, libstdc++/107800, libstdc++/108976,
+	libstdc++/110050, libstdc++/110054, libstdc++/113841,
+	libstdc++/114147, libstdc++/114316, libstdc++/114359,
+	libstdc++/114367, libstdc++/114401, libstdc++/114750,
+	libstdc++/114803, libstdc++/114863, libstdc++/115063, lto/114655,
+	middle-end/110027, middle-end/111151, middle-end/111632,
+	middle-end/111683, middle-end/112684, middle-end/112732,
+	middle-end/113396, middle-end/113622, middle-end/114070,
+	middle-end/114348, middle-end/114552, middle-end/114599,
+	middle-end/114734, middle-end/114753, middle-end/114907,
+	rtl-optimization/54052, rtl-optimization/114415,
+	rtl-optimization/114768, rtl-optimization/114924, sanitizer/97696,
+	sanitizer/114687, sanitizer/114743, sanitizer/114956,
+	sanitizer/115172, target/88309, target/101865, target/105522,
+	target/110621, target/111234, target/111600, target/111610,
+	target/111822, target/112397, target/113095, target/113233,
+	target/113950, target/114049, target/114130, target/114160,
+	target/114172, target/114175, target/114272, target/114747,
+	target/114752, target/114794, target/114837, target/114848,
+	target/114981, testsuite/111066, testsuite/112297, testsuite/114034,
+	testsuite/114036, testsuite/114662, tree-optimization/91838,
+	tree-optimization/109925, tree-optimization/110838,
+	tree-optimization/111009, tree-optimization/111268,
+	tree-optimization/111407, tree-optimization/111736,
+	tree-optimization/111882, tree-optimization/112281,
+	tree-optimization/112303, tree-optimization/112793,
+	tree-optimization/112961, tree-optimization/112991,
+	tree-optimization/113552, tree-optimization/113630,
+	tree-optimization/113670, tree-optimization/113831,
+	tree-optimization/113910, tree-optimization/114027,
+	tree-optimization/114115, tree-optimization/114121,
+	tree-optimization/114203, tree-optimization/114231,
+	tree-optimization/114246, tree-optimization/114375,
+	tree-optimization/114396, tree-optimization/114485,
+	tree-optimization/114566, tree-optimization/114672,
+	tree-optimization/114733, tree-optimization/114736,
+	tree-optimization/114749, tree-optimization/114787,
+	tree-optimization/114799, tree-optimization/114876,
+	tree-optimization/114965, tree-optimization/115143,
+	tree-optimization/115152, tree-optimization/115154
+- add --without-clang-plugin --without-llvm-plugin to annobin configure
+  options
+
 * Tue Jan  9 2024 Marek Polacek <polacek@redhat.com> 13.2.1-6.3
 - use the system dir in --with-libstdcxx-zoneinfo (RHEL-21093)
 

gcc13-libstdc++-compat.patch

@@ -8804,7 +8804,7 @@
 +	$(OPT_LDFLAGS) $(SECTION_LDFLAGS) $(AM_CXXFLAGS) $(LTLDFLAGS) -o $@
 --- libstdc++-v3/src/nonshared20/tzdb80.cc.jj	2023-05-19 20:25:50.447297532 +0200
 +++ libstdc++-v3/src/nonshared20/tzdb80.cc	2023-05-19 19:51:19.200552634 +0200
-@@ -0,0 +1,128 @@
+@@ -0,0 +1,126 @@
 +// Copyright The GNU Toolchain Authors.
 +//
 +// This file is part of the GNU ISO C++ Library.  This library is free
@@ -8906,9 +8906,7 @@
 +asm (".hidden _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag");
 +asm (".hidden _ZZNSt8__detail18__waiter_pool_base6_S_forEPKvE3__w");
 +asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv");
-+#if defined(__aarch64__) || defined(__powerpc64__) || defined(__x86_64__)
 +asm (".hidden _ZNKSt10filesystem7__cxx114path8iteratordeEv");
-+#endif
 +#if defined(__aarch64__) || defined(__x86_64__)
 +asm (".hidden _ZSt25__unguarded_linear_insertIN9__gnu_cxx17__normal_iteratorIPNSt6chrono9time_zoneESt6vectorIS3_SaIS3_EEEENS0_5__ops14_Val_comp_iterIZNSt6ranges8__detail16__make_comp_projINSB_4lessEMS3_KDoFSt17basic_string_viewIcSt11char_traitsIcEEvEEEDaRT_RT0_EUlOSL_OSN_E_EEEvSL_SN_");
 +#endif
@@ -12052,7 +12050,7 @@
 +#include "../c++17/string-inst.cc"
 --- libstdc++-v3/src/nonshared17/floating_to_chars110.cc.jj	2023-05-19 18:08:54.897043256 +0200
 +++ libstdc++-v3/src/nonshared17/floating_to_chars110.cc	2023-05-19 19:39:17.219738117 +0200
-@@ -0,0 +1,31 @@
+@@ -0,0 +1,36 @@
 +// Copyright (C) 2019-2023 Free Software Foundation, Inc.
 +//
 +// This file is part of the GNU ISO C++ Library.  This library is free
@@ -12084,6 +12082,11 @@
 +#if !defined(__s390x__) && !defined(__aarch64__)
 +asm (".hidden _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_");
 +#endif
++#if defined(__powerpc64__)
++asm (".hidden _ZSt8to_charsPcS_u9__ieee128");
++asm (".hidden _ZSt8to_charsPcS_u9__ieee128St12chars_format");
++asm (".hidden _ZSt8to_charsPcS_u9__ieee128St12chars_formati");
++#endif
 --- libstdc++-v3/src/nonshared17/string-inst110.cc.jj	2023-05-19 20:14:44.341711057 +0200
 +++ libstdc++-v3/src/nonshared17/string-inst110.cc	2023-05-19 19:41:57.743474432 +0200
 @@ -0,0 +1,37 @@
@@ -12759,8 +12762,8 @@
    lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
    lt_status=$lt_dlunknown
    cat > conftest.$ac_ext <<_LT_EOF
--#line 12190 "configure"
-+#line 12192 "configure"
+-#line 12192 "configure"
++#line 12194 "configure"
  #include "confdefs.h"
  
  #if HAVE_DLFCN_H
@@ -12768,8 +12771,8 @@
    lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
    lt_status=$lt_dlunknown
    cat > conftest.$ac_ext <<_LT_EOF
--#line 12296 "configure"
-+#line 12298 "configure"
+-#line 12298 "configure"
++#line 12300 "configure"
  #include "confdefs.h"
  
  #if HAVE_DLFCN_H
@@ -12777,8 +12780,8 @@
    # Fake what AC_TRY_COMPILE does.
  
      cat > conftest.$ac_ext << EOF
--#line 16020 "configure"
-+#line 16022 "configure"
+-#line 16036 "configure"
++#line 16038 "configure"
  int main()
  {
    typedef bool atomic_type;
@@ -12786,8 +12789,8 @@
      rm -f conftest*
  
      cat > conftest.$ac_ext << EOF
--#line 16055 "configure"
-+#line 16057 "configure"
+-#line 16071 "configure"
++#line 16073 "configure"
  int main()
  {
    typedef short atomic_type;
@@ -12795,8 +12798,8 @@
      rm -f conftest*
  
      cat > conftest.$ac_ext << EOF
--#line 16090 "configure"
-+#line 16092 "configure"
+-#line 16106 "configure"
++#line 16108 "configure"
  int main()
  {
    // NB: _Atomic_word not necessarily int.
@@ -12804,8 +12807,8 @@
      rm -f conftest*
  
      cat > conftest.$ac_ext << EOF
--#line 16126 "configure"
-+#line 16128 "configure"
+-#line 16142 "configure"
++#line 16144 "configure"
  int main()
  {
    typedef long long atomic_type;
@@ -12813,8 +12816,8 @@
    # unnecessary for this test.
  
      cat > conftest.$ac_ext << EOF
--#line 16282 "configure"
-+#line 16284 "configure"
+-#line 16298 "configure"
++#line 16300 "configure"
  int main()
  {
    _Decimal32 d1;
@@ -12822,8 +12825,8 @@
    # unnecessary for this test.
  
    cat > conftest.$ac_ext << EOF
--#line 16324 "configure"
-+#line 16326 "configure"
+-#line 16340 "configure"
++#line 16342 "configure"
  template<typename T1, typename T2>
    struct same
    { typedef T2 type; };

gcc13-libstdc++-docs.patch

@@ -4,7 +4,7 @@
        <a class="link" href="https://www.fsf.org" target="_top">FSF
        </a>
      </p><p>
-+      Release 13.2.1
++      Release 13.3.1
 +    </p><p>
        Permission is granted to copy, distribute and/or modify this
        document under the terms of the GNU Free Documentation
@@ -17,7 +17,7 @@
  </p><p>
 -  The API documentation, rendered into HTML, can be viewed online
 +  The API documentation, rendered into HTML, can be viewed locally
-+  <a class="link" href="api/index.html" target="_top">for the 13.2.1 release</a>,
++  <a class="link" href="api/index.html" target="_top">for the 13.3.1 release</a>,
 +  online
    <a class="link" href="http://gcc.gnu.org/onlinedocs/" target="_top">for each GCC release</a>
    and

gcc13-pr107071.patch

@@ -0,0 +1,28 @@
+commit c8c587b854c9e85fc9ce58c8192d532205f0ee1f
+Author: Tamar Christina <tamar.christina@arm.com>
+Date:   Wed Feb 21 11:42:13 2024 +0000
+
+    AArch64: skip modes_1.f90 [PR107071]
+    
+    This test has never worked on AArch64 since the day it was committed.  It has
+    a number of issues that prevent it from working on AArch64:
+    
+    The testfailures seem to be known and triaged, so until that's fixed there's
+    no point in running this test.
+    
+    gcc/testsuite/ChangeLog:
+    
+            PR fortran/107071
+            * gfortran.dg/ieee/modes_1.f90: skip aarch64, arm.
+
+diff --git a/gcc/testsuite/gfortran.dg/ieee/modes_1.f90 b/gcc/testsuite/gfortran.dg/ieee/modes_1.f90
+index 205c47f3800..e29d8c678e6 100644
+--- a/gcc/testsuite/gfortran.dg/ieee/modes_1.f90
++++ b/gcc/testsuite/gfortran.dg/ieee/modes_1.f90
+@@ -1,5 +1,5 @@
+ ! { dg-do run }
+-!
++! { dg-skip-if "PR libfortran/78314" { aarch64*-*-gnu* arm*-*-gnueabi arm*-*-gnueabihf } }
+ ! Test IEEE_MODES_TYPE, IEEE_GET_MODES and IEEE_SET_MODES
+ 
+ 

gcc13-vector-merge-1.patch

@@ -0,0 +1,522 @@
+commit 361bfcec901ca882130e338aebaa2ebc6ea2dc3b
+Author: Kewen Lin <linkw@linux.ibm.com>
+Date:   Thu Jun 20 20:23:56 2024 -0500
+
+    rs6000: Fix wrong RTL patterns for vector merge high/low word on LE
+    
+    Commit r12-4496 changes some define_expands and define_insns
+    for vector merge high/low word, which are altivec_vmrg[hl]w,
+    vsx_xxmrg[hl]w_<VSX_W:mode>.  These defines are mainly for
+    built-in function vec_merge{h,l}, __builtin_vsx_xxmrghw,
+    __builtin_vsx_xxmrghw_4si and some internal gen function
+    needs.  These functions should consider endianness, taking
+    vec_mergeh as example, as PVIPR defines, vec_mergeh "Merges
+    the first halves (in element order) of two vectors", it does
+    note it's in element order.  So it's mapped into vmrghw on
+    BE while vmrglw on LE respectively.  Although the mapped
+    insns are different, as the discussion in PR106069, the RTL
+    pattern should be still the same, it is conformed before
+    commit r12-4496, define_expand altivec_vmrghw got expanded
+    into:
+    
+      (vec_select:VSX_W
+         (vec_concat:<VS_double>
+            (match_operand:VSX_W 1 "register_operand" "wa,v")
+            (match_operand:VSX_W 2 "register_operand" "wa,v"))
+            (parallel [(const_int 0) (const_int 4)
+                       (const_int 1) (const_int 5)])))]
+    
+    on both BE and LE then.  But commit r12-4496 changed it to
+    expand into:
+    
+      (vec_select:VSX_W
+         (vec_concat:<VS_double>
+            (match_operand:VSX_W 1 "register_operand" "wa,v")
+            (match_operand:VSX_W 2 "register_operand" "wa,v"))
+            (parallel [(const_int 0) (const_int 4)
+                       (const_int 1) (const_int 5)])))]
+    
+    on BE, and
+    
+      (vec_select:VSX_W
+         (vec_concat:<VS_double>
+            (match_operand:VSX_W 1 "register_operand" "wa,v")
+            (match_operand:VSX_W 2 "register_operand" "wa,v"))
+            (parallel [(const_int 2) (const_int 6)
+                       (const_int 3) (const_int 7)])))]
+    
+    on LE, although the mapped insn are still vmrghw on BE and
+    vmrglw on LE, the associated RTL pattern is completely
+    wrong and inconsistent with the mapped insn.  If optimization
+    passes leave this pattern alone, even if its pattern doesn't
+    represent its mapped insn, it's still fine, that's why simple
+    testing on bif doesn't expose this issue.  But once some
+    optimization pass such as combine does some changes basing
+    on this wrong pattern, because the pattern doesn't match the
+    semantics that the expanded insn is intended to represent,
+    it would cause the unexpected result.
+    
+    So this patch is to fix the wrong RTL pattern, ensure the
+    associated RTL patterns become the same as before which can
+    have the same semantic as their mapped insns.  With the
+    proposed patch, the expanders like altivec_vmrghw expands
+    into altivec_vmrghb_direct_be or altivec_vmrglb_direct_le
+    depending on endianness, "direct" can easily show which
+    insn would be generated, _be and _le are mainly for the
+    different RTL patterns as endianness.
+    
+    Co-authored-by: Xionghu Luo <xionghuluo@tencent.com>
+    
+            PR target/106069
+            PR target/115355
+    
+    gcc/ChangeLog:
+    
+            * config/rs6000/altivec.md (altivec_vmrghw_direct_<VSX_W:mode>): Rename
+            to ...
+            (altivec_vmrghw_direct_<VSX_W:mode>_be): ... this.  Add the condition
+            BYTES_BIG_ENDIAN.
+            (altivec_vmrghw_direct_<VSX_W:mode>_le): New define_insn.
+            (altivec_vmrglw_direct_<VSX_W:mode>): Rename to ...
+            (altivec_vmrglw_direct_<VSX_W:mode>_be): ... this.  Add the condition
+            BYTES_BIG_ENDIAN.
+            (altivec_vmrglw_direct_<VSX_W:mode>_le): New define_insn.
+            (altivec_vmrghw): Adjust by calling gen_altivec_vmrghw_direct_v4si_be
+            for BE and gen_altivec_vmrglw_direct_v4si_le for LE.
+            (altivec_vmrglw): Adjust by calling gen_altivec_vmrglw_direct_v4si_be
+            for BE and gen_altivec_vmrghw_direct_v4si_le for LE.
+            (vec_widen_umult_hi_v8hi): Adjust the call to
+            gen_altivec_vmrghw_direct_v4si by gen_altivec_vmrghw for BE
+            and by gen_altivec_vmrglw for LE.
+            (vec_widen_smult_hi_v8hi): Likewise.
+            (vec_widen_umult_lo_v8hi): Adjust the call to
+            gen_altivec_vmrglw_direct_v4si by gen_altivec_vmrglw for BE
+            and by gen_altivec_vmrghw for LE
+            (vec_widen_smult_lo_v8hi): Likewise.
+            * config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace
+            CODE_FOR_altivec_vmrghw_direct_v4si by
+            CODE_FOR_altivec_vmrghw_direct_v4si_be for BE and
+            CODE_FOR_altivec_vmrghw_direct_v4si_le for LE.  And replace
+            CODE_FOR_altivec_vmrglw_direct_v4si by
+            CODE_FOR_altivec_vmrglw_direct_v4si_be for BE and
+            CODE_FOR_altivec_vmrglw_direct_v4si_le for LE.
+            * config/rs6000/vsx.md (vsx_xxmrghw_<VSX_W:mode>): Adjust by calling
+            gen_altivec_vmrghw_direct_v4si_be for BE and
+            gen_altivec_vmrglw_direct_v4si_le for LE.
+            (vsx_xxmrglw_<VSX_W:mode>): Adjust by calling
+            gen_altivec_vmrglw_direct_v4si_be for BE and
+            gen_altivec_vmrghw_direct_v4si_le for LE.
+    
+    gcc/testsuite/ChangeLog:
+    
+            * g++.target/powerpc/pr106069.C: New test.
+            * gcc.target/powerpc/pr115355.c: New test.
+    
+    (cherry picked from commit 52c112800d9f44457c4832309a48c00945811313)
+
+diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
+index ad1224e0b57..92e2e4a4090 100644
+--- a/gcc/config/rs6000/altivec.md
++++ b/gcc/config/rs6000/altivec.md
+@@ -1212,16 +1212,18 @@ (define_expand "altivec_vmrghw"
+    (use (match_operand:V4SI 2 "register_operand"))]
+   "VECTOR_MEM_ALTIVEC_P (V4SImode)"
+ {
+-  rtx (*fun) (rtx, rtx, rtx);
+-  fun = BYTES_BIG_ENDIAN ? gen_altivec_vmrghw_direct_v4si
+-			 : gen_altivec_vmrglw_direct_v4si;
+-  if (!BYTES_BIG_ENDIAN)
+-    std::swap (operands[1], operands[2]);
+-  emit_insn (fun (operands[0], operands[1], operands[2]));
++  if (BYTES_BIG_ENDIAN)
++    emit_insn (gen_altivec_vmrghw_direct_v4si_be (operands[0],
++						  operands[1],
++						  operands[2]));
++  else
++    emit_insn (gen_altivec_vmrglw_direct_v4si_le (operands[0],
++						  operands[2],
++						  operands[1]));
+   DONE;
+ })
+ 
+-(define_insn "altivec_vmrghw_direct_<mode>"
++(define_insn "altivec_vmrghw_direct_<mode>_be"
+   [(set (match_operand:VSX_W 0 "register_operand" "=wa,v")
+ 	(vec_select:VSX_W
+ 	  (vec_concat:<VS_double>
+@@ -1229,7 +1231,21 @@ (define_insn "altivec_vmrghw_direct_<mode>"
+ 	    (match_operand:VSX_W 2 "register_operand" "wa,v"))
+ 	  (parallel [(const_int 0) (const_int 4)
+ 		     (const_int 1) (const_int 5)])))]
+-  "TARGET_ALTIVEC"
++  "TARGET_ALTIVEC && BYTES_BIG_ENDIAN"
++  "@
++   xxmrghw %x0,%x1,%x2
++   vmrghw %0,%1,%2"
++  [(set_attr "type" "vecperm")])
++
++(define_insn "altivec_vmrghw_direct_<mode>_le"
++  [(set (match_operand:VSX_W 0 "register_operand" "=wa,v")
++	(vec_select:VSX_W
++	  (vec_concat:<VS_double>
++	    (match_operand:VSX_W 2 "register_operand" "wa,v")
++	    (match_operand:VSX_W 1 "register_operand" "wa,v"))
++	  (parallel [(const_int 2) (const_int 6)
++		     (const_int 3) (const_int 7)])))]
++  "TARGET_ALTIVEC && !BYTES_BIG_ENDIAN"
+   "@
+    xxmrghw %x0,%x1,%x2
+    vmrghw %0,%1,%2"
+@@ -1318,16 +1334,18 @@ (define_expand "altivec_vmrglw"
+    (use (match_operand:V4SI 2 "register_operand"))]
+   "VECTOR_MEM_ALTIVEC_P (V4SImode)"
+ {
+-  rtx (*fun) (rtx, rtx, rtx);
+-  fun = BYTES_BIG_ENDIAN ? gen_altivec_vmrglw_direct_v4si
+-			 : gen_altivec_vmrghw_direct_v4si;
+-  if (!BYTES_BIG_ENDIAN)
+-    std::swap (operands[1], operands[2]);
+-  emit_insn (fun (operands[0], operands[1], operands[2]));
++  if (BYTES_BIG_ENDIAN)
++    emit_insn (gen_altivec_vmrglw_direct_v4si_be (operands[0],
++						  operands[1],
++						  operands[2]));
++  else
++    emit_insn (gen_altivec_vmrghw_direct_v4si_le (operands[0],
++						  operands[2],
++						  operands[1]));
+   DONE;
+ })
+ 
+-(define_insn "altivec_vmrglw_direct_<mode>"
++(define_insn "altivec_vmrglw_direct_<mode>_be"
+   [(set (match_operand:VSX_W 0 "register_operand" "=wa,v")
+ 	(vec_select:VSX_W
+ 	  (vec_concat:<VS_double>
+@@ -1335,7 +1353,21 @@ (define_insn "altivec_vmrglw_direct_<mode>"
+ 	    (match_operand:VSX_W 2 "register_operand" "wa,v"))
+ 	  (parallel [(const_int 2) (const_int 6)
+ 		     (const_int 3) (const_int 7)])))]
+-  "TARGET_ALTIVEC"
++  "TARGET_ALTIVEC && BYTES_BIG_ENDIAN"
++  "@
++   xxmrglw %x0,%x1,%x2
++   vmrglw %0,%1,%2"
++  [(set_attr "type" "vecperm")])
++
++(define_insn "altivec_vmrglw_direct_<mode>_le"
++  [(set (match_operand:VSX_W 0 "register_operand" "=wa,v")
++	(vec_select:VSX_W
++	  (vec_concat:<VS_double>
++	    (match_operand:VSX_W 2 "register_operand" "wa,v")
++	    (match_operand:VSX_W 1 "register_operand" "wa,v"))
++	  (parallel [(const_int 0) (const_int 4)
++		     (const_int 1) (const_int 5)])))]
++  "TARGET_ALTIVEC && !BYTES_BIG_ENDIAN"
+   "@
+    xxmrglw %x0,%x1,%x2
+    vmrglw %0,%1,%2"
+@@ -3807,13 +3839,13 @@ (define_expand "vec_widen_umult_hi_v8hi"
+     {
+       emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrghw_direct_v4si (operands[0], ve, vo));
++      emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
+     }
+   else
+     {
+       emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrghw_direct_v4si (operands[0], vo, ve));
++      emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
+     }
+   DONE;
+ })
+@@ -3832,13 +3864,13 @@ (define_expand "vec_widen_umult_lo_v8hi"
+     {
+       emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrglw_direct_v4si (operands[0], ve, vo));
++      emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
+     }
+   else
+     {
+       emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrglw_direct_v4si (operands[0], vo, ve));
++      emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
+     }
+   DONE;
+ })
+@@ -3857,13 +3889,13 @@ (define_expand "vec_widen_smult_hi_v8hi"
+     {
+       emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrghw_direct_v4si (operands[0], ve, vo));
++      emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
+     }
+   else
+     {
+       emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrghw_direct_v4si (operands[0], vo, ve));
++      emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
+     }
+   DONE;
+ })
+@@ -3882,13 +3914,13 @@ (define_expand "vec_widen_smult_lo_v8hi"
+     {
+       emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrglw_direct_v4si (operands[0], ve, vo));
++      emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
+     }
+   else
+     {
+       emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrglw_direct_v4si (operands[0], vo, ve));
++      emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
+     }
+   DONE;
+ })
+diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
+index 9cfde1a52ea..b3d648312f1 100644
+--- a/gcc/config/rs6000/rs6000.cc
++++ b/gcc/config/rs6000/rs6000.cc
+@@ -23174,8 +23174,8 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
+ 		      : CODE_FOR_altivec_vmrglh_direct,
+      {0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}},
+     {OPTION_MASK_ALTIVEC,
+-     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct_v4si
+-		      : CODE_FOR_altivec_vmrglw_direct_v4si,
++     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct_v4si_be
++		      : CODE_FOR_altivec_vmrglw_direct_v4si_le,
+      {0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}},
+     {OPTION_MASK_ALTIVEC,
+      BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
+@@ -23186,8 +23186,8 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
+ 		      : CODE_FOR_altivec_vmrghh_direct,
+      {8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31}},
+     {OPTION_MASK_ALTIVEC,
+-     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct_v4si
+-		      : CODE_FOR_altivec_vmrghw_direct_v4si,
++     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct_v4si_be
++		      : CODE_FOR_altivec_vmrghw_direct_v4si_le,
+      {8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31}},
+     {OPTION_MASK_P8_VECTOR,
+      BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
+diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
+index f70d69ee4b9..b9a1bfb5c16 100644
+--- a/gcc/config/rs6000/vsx.md
++++ b/gcc/config/rs6000/vsx.md
+@@ -4683,12 +4683,14 @@ (define_expand "vsx_xxmrghw_<mode>"
+ 		     (const_int 1) (const_int 5)])))]
+   "VECTOR_MEM_VSX_P (<MODE>mode)"
+ {
+-  rtx (*fun) (rtx, rtx, rtx);
+-  fun = BYTES_BIG_ENDIAN ? gen_altivec_vmrghw_direct_<mode>
+-			 : gen_altivec_vmrglw_direct_<mode>;
+-  if (!BYTES_BIG_ENDIAN)
+-    std::swap (operands[1], operands[2]);
+-  emit_insn (fun (operands[0], operands[1], operands[2]));
++  if (BYTES_BIG_ENDIAN)
++    emit_insn (gen_altivec_vmrghw_direct_v4si_be (operands[0],
++						  operands[1],
++						  operands[2]));
++  else
++    emit_insn (gen_altivec_vmrglw_direct_v4si_le (operands[0],
++						  operands[2],
++						  operands[1]));
+   DONE;
+ }
+   [(set_attr "type" "vecperm")])
+@@ -4703,12 +4705,14 @@ (define_expand "vsx_xxmrglw_<mode>"
+ 		     (const_int 3) (const_int 7)])))]
+   "VECTOR_MEM_VSX_P (<MODE>mode)"
+ {
+-  rtx (*fun) (rtx, rtx, rtx);
+-  fun = BYTES_BIG_ENDIAN ? gen_altivec_vmrglw_direct_<mode>
+-			 : gen_altivec_vmrghw_direct_<mode>;
+-  if (!BYTES_BIG_ENDIAN)
+-    std::swap (operands[1], operands[2]);
+-  emit_insn (fun (operands[0], operands[1], operands[2]));
++  if (BYTES_BIG_ENDIAN)
++    emit_insn (gen_altivec_vmrglw_direct_v4si_be (operands[0],
++						  operands[1],
++						  operands[2]));
++  else
++    emit_insn (gen_altivec_vmrghw_direct_v4si_le (operands[0],
++						  operands[2],
++						  operands[1]));
+   DONE;
+ }
+   [(set_attr "type" "vecperm")])
+diff --git a/gcc/testsuite/g++.target/powerpc/pr106069.C b/gcc/testsuite/g++.target/powerpc/pr106069.C
+new file mode 100644
+index 00000000000..537207d2fe8
+--- /dev/null
++++ b/gcc/testsuite/g++.target/powerpc/pr106069.C
+@@ -0,0 +1,119 @@
++/* { dg-options "-O -fno-tree-forwprop -maltivec" } */
++/* { dg-require-effective-target vmx_hw } */
++/* { dg-do run } */
++
++typedef __attribute__ ((altivec (vector__))) unsigned native_simd_type;
++
++union
++{
++  native_simd_type V;
++  int R[4];
++} store_le_vec;
++
++struct S
++{
++  S () = default;
++  S (unsigned B0)
++  {
++    native_simd_type val{B0};
++    m_simd = val;
++  }
++  void store_le (unsigned int out[])
++  {
++    store_le_vec.V = m_simd;
++    unsigned int x0 = store_le_vec.R[0];
++    __builtin_memcpy (out, &x0, 4);
++  }
++  S rotl (unsigned int r)
++  {
++    native_simd_type rot{r};
++    return __builtin_vec_rl (m_simd, rot);
++  }
++  void operator+= (S other)
++  {
++    m_simd = __builtin_vec_add (m_simd, other.m_simd);
++  }
++  void operator^= (S other)
++  {
++    m_simd = __builtin_vec_xor (m_simd, other.m_simd);
++  }
++  static void transpose (S &B0, S B1, S B2, S B3)
++  {
++    native_simd_type T0 = __builtin_vec_mergeh (B0.m_simd, B2.m_simd);
++    native_simd_type T1 = __builtin_vec_mergeh (B1.m_simd, B3.m_simd);
++    native_simd_type T2 = __builtin_vec_mergel (B0.m_simd, B2.m_simd);
++    native_simd_type T3 = __builtin_vec_mergel (B1.m_simd, B3.m_simd);
++    B0 = __builtin_vec_mergeh (T0, T1);
++    B3 = __builtin_vec_mergel (T2, T3);
++  }
++  S (native_simd_type x) : m_simd (x) {}
++  native_simd_type m_simd;
++};
++
++void
++foo (unsigned int output[], unsigned state[])
++{
++  S R00 = state[0];
++  S R01 = state[0];
++  S R02 = state[2];
++  S R03 = state[0];
++  S R05 = state[5];
++  S R06 = state[6];
++  S R07 = state[7];
++  S R08 = state[8];
++  S R09 = state[9];
++  S R10 = state[10];
++  S R11 = state[11];
++  S R12 = state[12];
++  S R13 = state[13];
++  S R14 = state[4];
++  S R15 = state[15];
++  for (int r = 0; r != 10; ++r)
++    {
++      R09 += R13;
++      R11 += R15;
++      R05 ^= R09;
++      R06 ^= R10;
++      R07 ^= R11;
++      R07 = R07.rotl (7);
++      R00 += R05;
++      R01 += R06;
++      R02 += R07;
++      R15 ^= R00;
++      R12 ^= R01;
++      R13 ^= R02;
++      R00 += R05;
++      R01 += R06;
++      R02 += R07;
++      R15 ^= R00;
++      R12 = R12.rotl (8);
++      R13 = R13.rotl (8);
++      R10 += R15;
++      R11 += R12;
++      R08 += R13;
++      R09 += R14;
++      R05 ^= R10;
++      R06 ^= R11;
++      R07 ^= R08;
++      R05 = R05.rotl (7);
++      R06 = R06.rotl (7);
++      R07 = R07.rotl (7);
++    }
++  R00 += state[0];
++  S::transpose (R00, R01, R02, R03);
++  R00.store_le (output);
++}
++
++unsigned int res[1];
++unsigned main_state[]{1634760805, 60878,      2036477234, 6,
++		      0,	  825562964,  1471091955, 1346092787,
++		      506976774,  4197066702, 518848283,  118491664,
++		      0,	  0,	      0,	  0};
++int
++main ()
++{
++  foo (res, main_state);
++  if (res[0] != 0x41fcef98)
++    __builtin_abort ();
++  return 0;
++}
+diff --git a/gcc/testsuite/gcc.target/powerpc/pr115355.c b/gcc/testsuite/gcc.target/powerpc/pr115355.c
+new file mode 100644
+index 00000000000..8955126b808
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/powerpc/pr115355.c
+@@ -0,0 +1,37 @@
++/* { dg-do run } */
++/* { dg-require-effective-target p9vector_hw } */
++/* Force vectorization with -fno-vect-cost-model to have vector unpack
++   which exposes the issue in PR115355.  */
++/* { dg-options "-O2 -mdejagnu-cpu=power9 -fno-vect-cost-model" } */
++
++/* Verify it runs successfully.  */
++
++__attribute__((noipa))
++void setToIdentityGOOD(unsigned long long *mVec, unsigned int mLen)
++{
++  #pragma GCC novector
++  for (unsigned int i = 0; i < mLen; i++)
++    mVec[i] = i;
++}
++
++__attribute__((noipa))
++void setToIdentityBAD(unsigned long long *mVec, unsigned int mLen)
++{
++  for (unsigned int i = 0; i < mLen; i++)
++    mVec[i] = i;
++}
++
++unsigned long long vec1[100];
++unsigned long long vec2[100];
++
++int main()
++{
++  unsigned int l = 29;
++  setToIdentityGOOD (vec1, 29);
++  setToIdentityBAD (vec2, 29);
++
++  if (__builtin_memcmp (vec1, vec2, l * sizeof (vec1[0])) != 0)
++    __builtin_abort ();
++
++  return 0;
++}

gcc13-vector-merge-2.patch

@@ -0,0 +1,240 @@
+commit ffdd377fc07cdc7b62669d354e23f30940eaaffe
+Author: Kewen Lin <linkw@linux.ibm.com>
+Date:   Wed Jun 26 02:16:17 2024 -0500
+
+    rs6000: Fix wrong RTL patterns for vector merge high/low char on LE
+    
+    Commit r12-4496 changes some define_expands and define_insns
+    for vector merge high/low char, which are altivec_vmrg[hl]b.
+    These defines are mainly for built-in function vec_merge{h,l}
+    and some internal gen function needs.  These functions should
+    consider endianness, taking vec_mergeh as example, as PVIPR
+    defines, vec_mergeh "Merges the first halves (in element order)
+    of two vectors", it does note it's in element order.  So it's
+    mapped into vmrghb on BE while vmrglb on LE respectively.
+    Although the mapped insns are different, as the discussion in
+    PR106069, the RTL pattern should be still the same, it is
+    conformed before commit r12-4496, but gets changed into
+    different patterns on BE and LE starting from commit r12-4496.
+    Similar to 32-bit element case in commit log of r15-1504, this
+    8-bit element pattern on LE doesn't actually match what the
+    underlying insn is intended to represent, once some optimization
+    like combine does some changes basing on it, it would cause
+    the unexpected consequence.  The newly constructed test case
+    pr106069-1.c is a typical example for this issue.
+    
+    So this patch is to fix the wrong RTL pattern, ensure the
+    associated RTL patterns become the same as before which can
+    have the same semantic as their mapped insns.  With the
+    proposed patch, the expanders like altivec_vmrghb expands
+    into altivec_vmrghb_direct_be or altivec_vmrglb_direct_le
+    depending on endianness, "direct" can easily show which
+    insn would be generated, _be and _le are mainly for the
+    different RTL patterns as endianness.
+    
+    Co-authored-by: Xionghu Luo <xionghuluo@tencent.com>
+    
+            PR target/106069
+            PR target/115355
+    
+    gcc/ChangeLog:
+    
+            * config/rs6000/altivec.md (altivec_vmrghb_direct): Rename to ...
+            (altivec_vmrghb_direct_be): ... this.  Add condition BYTES_BIG_ENDIAN.
+            (altivec_vmrghb_direct_le): New define_insn.
+            (altivec_vmrglb_direct): Rename to ...
+            (altivec_vmrglb_direct_be): ... this.  Add condition BYTES_BIG_ENDIAN.
+            (altivec_vmrglb_direct_le): New define_insn.
+            (altivec_vmrghb): Adjust by calling gen_altivec_vmrghb_direct_be
+            for BE and gen_altivec_vmrglb_direct_le for LE.
+            (altivec_vmrglb): Adjust by calling gen_altivec_vmrglb_direct_be
+            for BE and gen_altivec_vmrghb_direct_le for LE.
+            * config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace
+            CODE_FOR_altivec_vmrghb_direct by
+            CODE_FOR_altivec_vmrghb_direct_be for BE and
+            CODE_FOR_altivec_vmrghb_direct_le for LE.  And replace
+            CODE_FOR_altivec_vmrglb_direct by
+            CODE_FOR_altivec_vmrglb_direct_be for BE and
+            CODE_FOR_altivec_vmrglb_direct_le for LE.
+    
+    gcc/testsuite/ChangeLog:
+    
+            * gcc.target/powerpc/pr106069-1.c: New test.
+    
+    (cherry picked from commit 62520e4e9f7e2fe8a16ee57a4bd35da2e921ae22)
+
+diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
+index 92e2e4a4090..47664204bc5 100644
+--- a/gcc/config/rs6000/altivec.md
++++ b/gcc/config/rs6000/altivec.md
+@@ -1152,15 +1152,16 @@ (define_expand "altivec_vmrghb"
+    (use (match_operand:V16QI 2 "register_operand"))]
+   "TARGET_ALTIVEC"
+ {
+-  rtx (*fun) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN ? gen_altivec_vmrghb_direct
+-						: gen_altivec_vmrglb_direct;
+-  if (!BYTES_BIG_ENDIAN)
+-    std::swap (operands[1], operands[2]);
+-  emit_insn (fun (operands[0], operands[1], operands[2]));
++  if (BYTES_BIG_ENDIAN)
++    emit_insn (
++      gen_altivec_vmrghb_direct_be (operands[0], operands[1], operands[2]));
++  else
++    emit_insn (
++      gen_altivec_vmrglb_direct_le (operands[0], operands[2], operands[1]));
+   DONE;
+ })
+ 
+-(define_insn "altivec_vmrghb_direct"
++(define_insn "altivec_vmrghb_direct_be"
+   [(set (match_operand:V16QI 0 "register_operand" "=v")
+ 	(vec_select:V16QI
+ 	  (vec_concat:V32QI
+@@ -1174,7 +1175,25 @@ (define_insn "altivec_vmrghb_direct"
+ 		     (const_int 5) (const_int 21)
+ 		     (const_int 6) (const_int 22)
+ 		     (const_int 7) (const_int 23)])))]
+-  "TARGET_ALTIVEC"
++  "TARGET_ALTIVEC && BYTES_BIG_ENDIAN"
++  "vmrghb %0,%1,%2"
++  [(set_attr "type" "vecperm")])
++
++(define_insn "altivec_vmrghb_direct_le"
++  [(set (match_operand:V16QI 0 "register_operand" "=v")
++	(vec_select:V16QI
++	  (vec_concat:V32QI
++	    (match_operand:V16QI 2 "register_operand" "v")
++	    (match_operand:V16QI 1 "register_operand" "v"))
++	  (parallel [(const_int  8) (const_int 24)
++		     (const_int  9) (const_int 25)
++		     (const_int 10) (const_int 26)
++		     (const_int 11) (const_int 27)
++		     (const_int 12) (const_int 28)
++		     (const_int 13) (const_int 29)
++		     (const_int 14) (const_int 30)
++		     (const_int 15) (const_int 31)])))]
++  "TARGET_ALTIVEC && !BYTES_BIG_ENDIAN"
+   "vmrghb %0,%1,%2"
+   [(set_attr "type" "vecperm")])
+ 
+@@ -1274,15 +1293,16 @@ (define_expand "altivec_vmrglb"
+    (use (match_operand:V16QI 2 "register_operand"))]
+   "TARGET_ALTIVEC"
+ {
+-  rtx (*fun) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN ? gen_altivec_vmrglb_direct
+-						: gen_altivec_vmrghb_direct;
+-  if (!BYTES_BIG_ENDIAN)
+-    std::swap (operands[1], operands[2]);
+-  emit_insn (fun (operands[0], operands[1], operands[2]));
++  if (BYTES_BIG_ENDIAN)
++    emit_insn (
++      gen_altivec_vmrglb_direct_be (operands[0], operands[1], operands[2]));
++  else
++    emit_insn (
++      gen_altivec_vmrghb_direct_le (operands[0], operands[2], operands[1]));
+   DONE;
+ })
+ 
+-(define_insn "altivec_vmrglb_direct"
++(define_insn "altivec_vmrglb_direct_be"
+   [(set (match_operand:V16QI 0 "register_operand" "=v")
+ 	(vec_select:V16QI
+ 	  (vec_concat:V32QI
+@@ -1296,7 +1316,25 @@ (define_insn "altivec_vmrglb_direct"
+ 		     (const_int 13) (const_int 29)
+ 		     (const_int 14) (const_int 30)
+ 		     (const_int 15) (const_int 31)])))]
+-  "TARGET_ALTIVEC"
++  "TARGET_ALTIVEC && BYTES_BIG_ENDIAN"
++  "vmrglb %0,%1,%2"
++  [(set_attr "type" "vecperm")])
++
++(define_insn "altivec_vmrglb_direct_le"
++  [(set (match_operand:V16QI 0 "register_operand" "=v")
++	(vec_select:V16QI
++	  (vec_concat:V32QI
++	    (match_operand:V16QI 2 "register_operand" "v")
++	    (match_operand:V16QI 1 "register_operand" "v"))
++	  (parallel [(const_int 0) (const_int 16)
++		     (const_int 1) (const_int 17)
++		     (const_int 2) (const_int 18)
++		     (const_int 3) (const_int 19)
++		     (const_int 4) (const_int 20)
++		     (const_int 5) (const_int 21)
++		     (const_int 6) (const_int 22)
++		     (const_int 7) (const_int 23)])))]
++  "TARGET_ALTIVEC && !BYTES_BIG_ENDIAN"
+   "vmrglb %0,%1,%2"
+   [(set_attr "type" "vecperm")])
+ 
+diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
+index b3d648312f1..10088033aa1 100644
+--- a/gcc/config/rs6000/rs6000.cc
++++ b/gcc/config/rs6000/rs6000.cc
+@@ -23166,8 +23166,8 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
+      CODE_FOR_altivec_vpkuwum_direct,
+      {2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31}},
+     {OPTION_MASK_ALTIVEC,
+-     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
+-		      : CODE_FOR_altivec_vmrglb_direct,
++     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct_be
++		      : CODE_FOR_altivec_vmrglb_direct_le,
+      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23}},
+     {OPTION_MASK_ALTIVEC,
+      BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
+@@ -23178,8 +23178,8 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
+ 		      : CODE_FOR_altivec_vmrglw_direct_v4si_le,
+      {0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}},
+     {OPTION_MASK_ALTIVEC,
+-     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
+-		      : CODE_FOR_altivec_vmrghb_direct,
++     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct_be
++		      : CODE_FOR_altivec_vmrghb_direct_le,
+      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31}},
+     {OPTION_MASK_ALTIVEC,
+      BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
+diff --git a/gcc/testsuite/gcc.target/powerpc/pr106069-1.c b/gcc/testsuite/gcc.target/powerpc/pr106069-1.c
+new file mode 100644
+index 00000000000..4945d8fedfb
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/powerpc/pr106069-1.c
+@@ -0,0 +1,39 @@
++/* { dg-do run } */
++/* { dg-options "-O2" } */
++/* { dg-require-effective-target vmx_hw } */
++
++/* Test vector merge for 8-bit element size,
++   it will abort if the RTL pattern isn't expected.  */
++
++#include "altivec.h"
++
++__attribute__((noipa))
++signed char elem_6 (vector signed char a, vector signed char b)
++{
++  vector signed char c = vec_mergeh (a,b);
++  return vec_extract (c, 6);
++}
++
++__attribute__((noipa))
++unsigned char elem_15 (vector unsigned char a, vector unsigned char b)
++{
++  vector unsigned char c = vec_mergel (a,b);
++  return vec_extract (c, 15);
++}
++
++int
++main ()
++{
++  vector unsigned char v1
++    = {3, 33, 22, 12, 34, 14, 5, 25, 30, 11, 0, 21, 17, 27, 38, 8};
++  vector unsigned char v2
++    = {81, 82, 83, 84, 68, 67, 66, 65, 99, 100, 101, 102, 250, 125, 0, 6};
++  signed char x1 = elem_6 ((vector signed char) v1, (vector signed char) v2);
++  unsigned char x2 = elem_15 (v1, v2);
++
++  if (x1 != 12 || x2 != 6)
++    __builtin_abort ();
++
++  return 0;
++}
++

gcc13-vector-merge-3.patch

@@ -0,0 +1,306 @@
+commit bab38d9271ce3f26cb64b8cb712351eb3fedd559
+Author: Kewen Lin <linkw@linux.ibm.com>
+Date:   Wed Jun 26 02:16:17 2024 -0500
+
+    rs6000: Fix wrong RTL patterns for vector merge high/low short on LE
+    
+    Commit r12-4496 changes some define_expands and define_insns
+    for vector merge high/low short, which are altivec_vmrg[hl]h.
+    These defines are mainly for built-in function vec_merge{h,l}
+    and some internal gen function needs.  These functions should
+    consider endianness, taking vec_mergeh as example, as PVIPR
+    defines, vec_mergeh "Merges the first halves (in element order)
+    of two vectors", it does note it's in element order.  So it's
+    mapped into vmrghh on BE while vmrglh on LE respectively.
+    Although the mapped insns are different, as the discussion in
+    PR106069, the RTL pattern should be still the same, it is
+    conformed before commit r12-4496, but gets changed into
+    different patterns on BE and LE starting from commit r12-4496.
+    Similar to 32-bit element case in commit log of r15-1504, this
+    16-bit element pattern on LE doesn't actually match what the
+    underlying insn is intended to represent, once some optimization
+    like combine does some changes basing on it, it would cause
+    the unexpected consequence.  The newly constructed test case
+    pr106069-2.c is a typical example for this issue on element type
+    short.
+    
+    So this patch is to fix the wrong RTL pattern, ensure the
+    associated RTL patterns become the same as before which can
+    have the same semantic as their mapped insns.  With the
+    proposed patch, the expanders like altivec_vmrghh expands
+    into altivec_vmrghh_direct_be or altivec_vmrglh_direct_le
+    depending on endianness, "direct" can easily show which
+    insn would be generated, _be and _le are mainly for the
+    different RTL patterns as endianness.
+    
+    Co-authored-by: Xionghu Luo <xionghuluo@tencent.com>
+    
+            PR target/106069
+            PR target/115355
+    
+    gcc/ChangeLog:
+    
+            * config/rs6000/altivec.md (altivec_vmrghh_direct): Rename to ...
+            (altivec_vmrghh_direct_be): ... this.  Add condition BYTES_BIG_ENDIAN.
+            (altivec_vmrghh_direct_le): New define_insn.
+            (altivec_vmrglh_direct): Rename to ...
+            (altivec_vmrglh_direct_be): ... this.  Add condition BYTES_BIG_ENDIAN.
+            (altivec_vmrglh_direct_le): New define_insn.
+            (altivec_vmrghh): Adjust by calling gen_altivec_vmrghh_direct_be
+            for BE and gen_altivec_vmrglh_direct_le for LE.
+            (altivec_vmrglh): Adjust by calling gen_altivec_vmrglh_direct_be
+            for BE and gen_altivec_vmrghh_direct_le for LE.
+            (vec_widen_umult_hi_v16qi): Adjust the call to
+            gen_altivec_vmrghh_direct by gen_altivec_vmrghh for BE
+            and by gen_altivec_vmrglh for LE.
+            (vec_widen_smult_hi_v16qi): Likewise.
+            (vec_widen_umult_lo_v16qi): Adjust the call to
+            gen_altivec_vmrglh_direct by gen_altivec_vmrglh for BE
+            and by gen_altivec_vmrghh for LE.
+            (vec_widen_smult_lo_v16qi): Likewise.
+            * config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace
+            CODE_FOR_altivec_vmrghh_direct by
+            CODE_FOR_altivec_vmrghh_direct_be for BE and
+            CODE_FOR_altivec_vmrghh_direct_le for LE.  And replace
+            CODE_FOR_altivec_vmrglh_direct by
+            CODE_FOR_altivec_vmrglh_direct_be for BE and
+            CODE_FOR_altivec_vmrglh_direct_le for LE.
+    
+    gcc/testsuite/ChangeLog:
+    
+            * gcc.target/powerpc/pr106069-2.c: New test.
+    
+    (cherry picked from commit 812c70bf4981958488331d4ea5af8709b5321da1)
+
+diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
+index 47664204bc5..6557393a97c 100644
+--- a/gcc/config/rs6000/altivec.md
++++ b/gcc/config/rs6000/altivec.md
+@@ -1203,17 +1203,18 @@ (define_expand "altivec_vmrghh"
+    (use (match_operand:V8HI 2 "register_operand"))]
+   "TARGET_ALTIVEC"
+ {
+-  rtx (*fun) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN ? gen_altivec_vmrghh_direct
+-						: gen_altivec_vmrglh_direct;
+-  if (!BYTES_BIG_ENDIAN)
+-    std::swap (operands[1], operands[2]);
+-  emit_insn (fun (operands[0], operands[1], operands[2]));
++  if (BYTES_BIG_ENDIAN)
++    emit_insn (
++      gen_altivec_vmrghh_direct_be (operands[0], operands[1], operands[2]));
++  else
++    emit_insn (
++      gen_altivec_vmrglh_direct_le (operands[0], operands[2], operands[1]));
+   DONE;
+ })
+ 
+-(define_insn "altivec_vmrghh_direct"
++(define_insn "altivec_vmrghh_direct_be"
+   [(set (match_operand:V8HI 0 "register_operand" "=v")
+-        (vec_select:V8HI
++	(vec_select:V8HI
+ 	  (vec_concat:V16HI
+ 	    (match_operand:V8HI 1 "register_operand" "v")
+ 	    (match_operand:V8HI 2 "register_operand" "v"))
+@@ -1221,7 +1222,21 @@ (define_insn "altivec_vmrghh_direct"
+ 		     (const_int 1) (const_int 9)
+ 		     (const_int 2) (const_int 10)
+ 		     (const_int 3) (const_int 11)])))]
+-  "TARGET_ALTIVEC"
++  "TARGET_ALTIVEC && BYTES_BIG_ENDIAN"
++  "vmrghh %0,%1,%2"
++  [(set_attr "type" "vecperm")])
++
++(define_insn "altivec_vmrghh_direct_le"
++  [(set (match_operand:V8HI 0 "register_operand" "=v")
++        (vec_select:V8HI
++	  (vec_concat:V16HI
++	    (match_operand:V8HI 2 "register_operand" "v")
++	    (match_operand:V8HI 1 "register_operand" "v"))
++	  (parallel [(const_int 4) (const_int 12)
++		     (const_int 5) (const_int 13)
++		     (const_int 6) (const_int 14)
++		     (const_int 7) (const_int 15)])))]
++  "TARGET_ALTIVEC && !BYTES_BIG_ENDIAN"
+   "vmrghh %0,%1,%2"
+   [(set_attr "type" "vecperm")])
+ 
+@@ -1344,15 +1359,16 @@ (define_expand "altivec_vmrglh"
+    (use (match_operand:V8HI 2 "register_operand"))]
+   "TARGET_ALTIVEC"
+ {
+-  rtx (*fun) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN ? gen_altivec_vmrglh_direct
+-						: gen_altivec_vmrghh_direct;
+-  if (!BYTES_BIG_ENDIAN)
+-    std::swap (operands[1], operands[2]);
+-  emit_insn (fun (operands[0], operands[1], operands[2]));
++  if (BYTES_BIG_ENDIAN)
++    emit_insn (
++      gen_altivec_vmrglh_direct_be (operands[0], operands[1], operands[2]));
++  else
++    emit_insn (
++      gen_altivec_vmrghh_direct_le (operands[0], operands[2], operands[1]));
+   DONE;
+ })
+ 
+-(define_insn "altivec_vmrglh_direct"
++(define_insn "altivec_vmrglh_direct_be"
+   [(set (match_operand:V8HI 0 "register_operand" "=v")
+         (vec_select:V8HI
+ 	  (vec_concat:V16HI
+@@ -1362,7 +1378,21 @@ (define_insn "altivec_vmrglh_direct"
+ 		     (const_int 5) (const_int 13)
+ 		     (const_int 6) (const_int 14)
+ 		     (const_int 7) (const_int 15)])))]
+-  "TARGET_ALTIVEC"
++  "TARGET_ALTIVEC && BYTES_BIG_ENDIAN"
++  "vmrglh %0,%1,%2"
++  [(set_attr "type" "vecperm")])
++
++(define_insn "altivec_vmrglh_direct_le"
++  [(set (match_operand:V8HI 0 "register_operand" "=v")
++	(vec_select:V8HI
++	  (vec_concat:V16HI
++	    (match_operand:V8HI 2 "register_operand" "v")
++	    (match_operand:V8HI 1 "register_operand" "v"))
++	  (parallel [(const_int 0) (const_int 8)
++		     (const_int 1) (const_int 9)
++		     (const_int 2) (const_int 10)
++		     (const_int 3) (const_int 11)])))]
++  "TARGET_ALTIVEC && !BYTES_BIG_ENDIAN"
+   "vmrglh %0,%1,%2"
+   [(set_attr "type" "vecperm")])
+ 
+@@ -3777,13 +3807,13 @@ (define_expand "vec_widen_umult_hi_v16qi"
+     {
+       emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));
++      emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
+     }
+   else
+     {
+       emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
++      emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
+     }
+   DONE;
+ })
+@@ -3802,13 +3832,13 @@ (define_expand "vec_widen_umult_lo_v16qi"
+     {
+       emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));
++      emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
+     }
+   else
+     {
+       emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
++      emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
+     }
+   DONE;
+ })
+@@ -3827,13 +3857,13 @@ (define_expand "vec_widen_smult_hi_v16qi"
+     {
+       emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));
++      emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
+     }
+   else
+     {
+       emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
++      emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
+     }
+   DONE;
+ })
+@@ -3852,13 +3882,13 @@ (define_expand "vec_widen_smult_lo_v16qi"
+     {
+       emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));
++      emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
+     }
+   else
+     {
+       emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));
+       emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));
+-      emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
++      emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
+     }
+   DONE;
+ })
+diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
+index 10088033aa1..76eb89ad529 100644
+--- a/gcc/config/rs6000/rs6000.cc
++++ b/gcc/config/rs6000/rs6000.cc
+@@ -23170,8 +23170,8 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
+ 		      : CODE_FOR_altivec_vmrglb_direct_le,
+      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23}},
+     {OPTION_MASK_ALTIVEC,
+-     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
+-		      : CODE_FOR_altivec_vmrglh_direct,
++     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct_be
++		      : CODE_FOR_altivec_vmrglh_direct_le,
+      {0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}},
+     {OPTION_MASK_ALTIVEC,
+      BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct_v4si_be
+@@ -23182,8 +23182,8 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
+ 		      : CODE_FOR_altivec_vmrghb_direct_le,
+      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31}},
+     {OPTION_MASK_ALTIVEC,
+-     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
+-		      : CODE_FOR_altivec_vmrghh_direct,
++     BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct_be
++		      : CODE_FOR_altivec_vmrghh_direct_le,
+      {8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31}},
+     {OPTION_MASK_ALTIVEC,
+      BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct_v4si_be
+diff --git a/gcc/testsuite/gcc.target/powerpc/pr106069-2.c b/gcc/testsuite/gcc.target/powerpc/pr106069-2.c
+new file mode 100644
+index 00000000000..283e3290fb3
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/powerpc/pr106069-2.c
+@@ -0,0 +1,37 @@
++/* { dg-do run } */
++/* { dg-options "-O2" } */
++/* { dg-require-effective-target vmx_hw } */
++
++/* Test vector merge for 16-bit element size,
++   it will abort if the RTL pattern isn't expected.  */
++
++#include "altivec.h"
++
++__attribute__((noipa))
++signed short elem_2 (vector signed short a, vector signed short b)
++{
++  vector signed short c = vec_mergeh (a,b);
++  return vec_extract (c, 2);
++}
++
++__attribute__((noipa))
++unsigned short elem_7 (vector unsigned short a, vector unsigned short b)
++{
++  vector unsigned short c = vec_mergel (a,b);
++  return vec_extract (c, 7);
++}
++
++int
++main ()
++{
++  vector unsigned short v1 = {3, 22, 12, 34, 5, 25, 30, 11};
++  vector unsigned short v2 = {84, 168, 267, 966, 65, 399, 999, 99};
++  signed short x1 = elem_2 ((vector signed short) v1, (vector signed short) v2);
++  unsigned short x2 = elem_7 (v1, v2);
++
++  if (x1 != 22 || x2 != 99)
++    __builtin_abort ();
++
++  return 0;
++}
++

sources

@@ -0,0 +1,4 @@
+SHA512 (gcc-13.3.1-20240611.tar.xz) = 4cf86cf58663e89b54198824eaf6387157f8fb205f700815d8066150f393ceecb41f3f369c772e5855a4555eccf24c5dfd501507337d0438cc8134d0df02f696
+SHA512 (isl-0.24.tar.bz2) = aab3bddbda96b801d0f56d2869f943157aad52a6f6e6a61745edd740234c635c38231af20bc3f1a08d416a5e973a90e18249078ed8e4ae2f1d5de57658738e95
+SHA512 (newlib-cygwin-9e09d6ed83cce4777a5950412647ccc603040409.tar.xz) = bef3fa04f7b1a915fc1356ebed114698b5cc835e9fa04b0becff05a9efc76c59fb376482990873d222d7acdcfee3c4f30f5a4cb7f3be1f291f1fa5f1c7a9d983
+SHA512 (nvptx-tools-aa3404ad5a496cda5d79a50bedb1344fd63e8763.tar.xz) = 33a024326426375533cb5dd9b68b2508f37540be418d2506bfa19a5f5866485e9af150469064e9059b68136ad8cb080b3b12e7eb5c6b7d1288cf6bfb3f6bb5d0