81 lines
3.1 KiB
Diff
81 lines
3.1 KiB
Diff
From 15ac3968a929adebc27985be77fe90d3847abd57 Mon Sep 17 00:00:00 2001
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From: Xianting Tian <xianting.tian@linux.alibaba.com>
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Date: Thu, 20 Oct 2022 09:50:11 +0800
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Subject: [PATCH 56/89] RISCV64: Add 'help -r' command support
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Add support form printing out the registers from the dump file.
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With the patch, we can get the regs,
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crash> help -r
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CPU 0:
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epc : 00ffffffa5537400 ra : ffffffff80088620 sp : ff2000001039bb90
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gp : ffffffff810dde38 tp : ff60000002269600 t0 : ffffffff8032be5c
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t1 : 0720072007200720 t2 : 666666666666663c s0 : ff2000001039bcf0
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s1 : 0000000000000000 a0 : ff2000001039bb98 a1 : 0000000000000001
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a2 : 0000000000000010 a3 : 0000000000000000 a4 : 0000000000000000
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a5 : ff60000001c7d000 a6 : 000000000000003c a7 : ffffffff8035c998
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s2 : ffffffff810df0a8 s3 : ffffffff810df718 s4 : ff2000001039bb98
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s5 : 0000000000000000 s6 : 0000000000000007 s7 : ffffffff80c4a468
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s8 : 00fffffffde45410 s9 : 0000000000000007 s10: 00aaaaaad1640700
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s11: 0000000000000001 t3 : ff60000001218f00 t4 : ff60000001218f00
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t5 : ff60000001218000 t6 : ff2000001039b988
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Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
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Signed-off-by: Lianbo Jiang <lijiang@redhat.com>
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---
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riscv64.c | 38 ++++++++++++++++++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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diff --git a/riscv64.c b/riscv64.c
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index 4c9b35bb93f2..6d1d3b5f36d1 100644
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--- a/riscv64.c
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+++ b/riscv64.c
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@@ -1320,6 +1320,44 @@ riscv64_init(int when)
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void
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riscv64_display_regs_from_elf_notes(int cpu, FILE *ofp)
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{
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+ const struct machine_specific *ms = machdep->machspec;
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+ struct riscv64_register *regs;
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+
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+ if (!ms->crash_task_regs) {
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+ error(INFO, "registers not collected for cpu %d\n", cpu);
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+ return;
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+ }
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+
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+ regs = &ms->crash_task_regs[cpu];
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+ if (!regs->regs[RISCV64_REGS_SP] && !regs->regs[RISCV64_REGS_EPC]) {
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+ error(INFO, "registers not collected for cpu %d\n", cpu);
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+ return;
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+ }
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+
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+ /* Print riscv64 32 regs */
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+ fprintf(ofp,
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+ "epc : " REG_FMT " ra : " REG_FMT " sp : " REG_FMT "\n"
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+ " gp : " REG_FMT " tp : " REG_FMT " t0 : " REG_FMT "\n"
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+ " t1 : " REG_FMT " t2 : " REG_FMT " s0 : " REG_FMT "\n"
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+ " s1 : " REG_FMT " a0 : " REG_FMT " a1 : " REG_FMT "\n"
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+ " a2 : " REG_FMT " a3 : " REG_FMT " a4 : " REG_FMT "\n"
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+ " a5 : " REG_FMT " a6 : " REG_FMT " a7 : " REG_FMT "\n"
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+ " s2 : " REG_FMT " s3 : " REG_FMT " s4 : " REG_FMT "\n"
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+ " s5 : " REG_FMT " s6 : " REG_FMT " s7 : " REG_FMT "\n"
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+ " s8 : " REG_FMT " s9 : " REG_FMT " s10: " REG_FMT "\n"
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+ " s11: " REG_FMT " t3 : " REG_FMT " t4 : " REG_FMT "\n"
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+ " t5 : " REG_FMT " t6 : " REG_FMT "\n",
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+ regs->regs[0], regs->regs[1], regs->regs[2],
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+ regs->regs[3], regs->regs[4], regs->regs[5],
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+ regs->regs[6], regs->regs[7], regs->regs[8],
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+ regs->regs[9], regs->regs[10], regs->regs[11],
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+ regs->regs[12], regs->regs[13], regs->regs[14],
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+ regs->regs[15], regs->regs[16], regs->regs[17],
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+ regs->regs[18], regs->regs[19], regs->regs[20],
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+ regs->regs[21], regs->regs[22], regs->regs[23],
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+ regs->regs[24], regs->regs[25], regs->regs[26],
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+ regs->regs[27], regs->regs[28], regs->regs[29],
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+ regs->regs[30], regs->regs[31]);
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}
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#else /* !RISCV64 */
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--
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2.37.1
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