forked from rpms/kernel
56 lines
2.4 KiB
Diff
56 lines
2.4 KiB
Diff
From patchwork Mon Oct 2 14:08:40 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: PCI: aspm: deal with missing root ports in link state handling
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From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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X-Patchwork-Id: 9980861
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Message-Id: <20171002140840.7767-1-ard.biesheuvel@linaro.org>
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To: linux-pci@vger.kernel.org, bhelgaas@google.com
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Cc: graeme.gregory@linaro.org, leif.lindholm@linaro.org,
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daniel.thompson@Linaro.org, Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Date: Mon, 2 Oct 2017 15:08:40 +0100
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Even though it is unconventional, some PCIe host implementations omit
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the root ports entirely, and simply consist of a host bridge (which
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is not modeled as a device in the PCI hierarchy) and a link.
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When the downstream device is an endpoint, our current code does not
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seem to mind this unusual configuration. However, when PCIe switches
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are involved, the ASPM code assumes that any downstream switch port
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has a parent, and blindly derefences the bus->parent->self field of
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the pci_dev struct to chain the downstream link state to the link
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state of the root port. Given that the root port is missing, the link
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is not modeled at all, and nor is the link state, and attempting to
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access it results in a NULL pointer dereference and a crash.
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So let's avoid this by allowing the link state chain to terminate at
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the downstream port if no root port exists.
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Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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---
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drivers/pci/pcie/aspm.c | 8 ++++++--
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1 file changed, 6 insertions(+), 2 deletions(-)
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diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
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index 1dfa10cc566b..0bea8498b5a5 100644
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--- a/drivers/pci/pcie/aspm.c
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+++ b/drivers/pci/pcie/aspm.c
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@@ -802,10 +802,14 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
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/*
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* Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
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- * hierarchies.
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+ * hierarchies. Note that some PCIe host implementations omit
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+ * the root ports entirely, in which case a downstream port on
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+ * a switch may become the root of the link state chain for all
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+ * its subordinate endpoints.
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*/
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if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
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- pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE) {
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+ pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
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+ !pdev->bus->parent->self) {
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link->root = link;
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} else {
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struct pcie_link_state *parent;
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