forked from rpms/kernel
		
	kernel-6.7.0-0.rc5.20231213git88035e5694a8.43
* Wed Dec 13 2023 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.7.0-0.rc5.88035e5694a8.43] - Some Fedora config updates for MLX5 (Justin M. Forbes) - Turn on DRM_ACCEL drivers for Fedora (Justin M. Forbes) - Linux v6.7.0-0.rc5.88035e5694a8 Resolves: Signed-off-by: Justin M. Forbes <jforbes@fedoraproject.org>
This commit is contained in:
		
							parent
							
								
									e1ffd92efa
								
							
						
					
					
						commit
						b15f45300d
					
				| @ -12,7 +12,7 @@ RHEL_MINOR = 99 | ||||
| #
 | ||||
| # Use this spot to avoid future merge conflicts.
 | ||||
| # Do not trim this comment.
 | ||||
| RHEL_RELEASE = 42 | ||||
| RHEL_RELEASE = 43 | ||||
| 
 | ||||
| #
 | ||||
| # RHEL_REBASE_NUM
 | ||||
|  | ||||
| @ -1879,7 +1879,8 @@ CONFIG_DPOT_DAC=m | ||||
| CONFIG_DRAGONRISE_FF=y | ||||
| CONFIG_DRBD_FAULT_INJECTION=y | ||||
| CONFIG_DRIVER_PE_KUNIT_TEST=m | ||||
| # CONFIG_DRM_ACCEL is not set | ||||
| CONFIG_DRM_ACCEL_QAIC=m | ||||
| CONFIG_DRM_ACCEL=y | ||||
| CONFIG_DRM_AMD_ACP=y | ||||
| CONFIG_DRM_AMD_DC_HDCP=y | ||||
| CONFIG_DRM_AMD_DC_SI=y | ||||
| @ -4468,19 +4469,22 @@ CONFIG_MLX4_DEBUG=y | ||||
| CONFIG_MLX4_EN_DCB=y | ||||
| CONFIG_MLX4_EN=m | ||||
| CONFIG_MLX4_INFINIBAND=m | ||||
| CONFIG_MLX5_ACCEL=y | ||||
| CONFIG_MLX5_CLS_ACT=y | ||||
| CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| # CONFIG_MLX5_DPLL is not set | ||||
| CONFIG_MLX5_DPLL=m | ||||
| CONFIG_MLX5_EN_ARFS=y | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_EN_MACSEC=y | ||||
| CONFIG_MLX5_EN_RXNFC=y | ||||
| CONFIG_MLX5_EN_TLS=y | ||||
| CONFIG_MLX5_ESWITCH=y | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_FPGA_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA_TLS is not set | ||||
| CONFIG_MLX5_FPGA=y | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| CONFIG_MLX5_IPSEC=y | ||||
| CONFIG_MLX5_MACSEC=y | ||||
|  | ||||
| @ -1870,7 +1870,8 @@ CONFIG_DPOT_DAC=m | ||||
| CONFIG_DRAGONRISE_FF=y | ||||
| # CONFIG_DRBD_FAULT_INJECTION is not set | ||||
| CONFIG_DRIVER_PE_KUNIT_TEST=m | ||||
| # CONFIG_DRM_ACCEL is not set | ||||
| CONFIG_DRM_ACCEL_QAIC=m | ||||
| CONFIG_DRM_ACCEL=y | ||||
| CONFIG_DRM_AMD_ACP=y | ||||
| CONFIG_DRM_AMD_DC_HDCP=y | ||||
| CONFIG_DRM_AMD_DC_SI=y | ||||
| @ -4443,19 +4444,22 @@ CONFIG_MLX4_DEBUG=y | ||||
| CONFIG_MLX4_EN_DCB=y | ||||
| CONFIG_MLX4_EN=m | ||||
| CONFIG_MLX4_INFINIBAND=m | ||||
| CONFIG_MLX5_ACCEL=y | ||||
| CONFIG_MLX5_CLS_ACT=y | ||||
| CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| # CONFIG_MLX5_DPLL is not set | ||||
| CONFIG_MLX5_DPLL=m | ||||
| CONFIG_MLX5_EN_ARFS=y | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_EN_MACSEC=y | ||||
| CONFIG_MLX5_EN_RXNFC=y | ||||
| CONFIG_MLX5_EN_TLS=y | ||||
| CONFIG_MLX5_ESWITCH=y | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_FPGA_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA_TLS is not set | ||||
| CONFIG_MLX5_FPGA=y | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| CONFIG_MLX5_IPSEC=y | ||||
| CONFIG_MLX5_MACSEC=y | ||||
|  | ||||
| @ -1879,7 +1879,8 @@ CONFIG_DPOT_DAC=m | ||||
| CONFIG_DRAGONRISE_FF=y | ||||
| CONFIG_DRBD_FAULT_INJECTION=y | ||||
| CONFIG_DRIVER_PE_KUNIT_TEST=m | ||||
| # CONFIG_DRM_ACCEL is not set | ||||
| CONFIG_DRM_ACCEL_QAIC=m | ||||
| CONFIG_DRM_ACCEL=y | ||||
| CONFIG_DRM_AMD_ACP=y | ||||
| CONFIG_DRM_AMD_DC_HDCP=y | ||||
| CONFIG_DRM_AMD_DC_SI=y | ||||
| @ -4468,19 +4469,22 @@ CONFIG_MLX4_DEBUG=y | ||||
| CONFIG_MLX4_EN_DCB=y | ||||
| CONFIG_MLX4_EN=m | ||||
| CONFIG_MLX4_INFINIBAND=m | ||||
| CONFIG_MLX5_ACCEL=y | ||||
| CONFIG_MLX5_CLS_ACT=y | ||||
| CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| # CONFIG_MLX5_DPLL is not set | ||||
| CONFIG_MLX5_DPLL=m | ||||
| CONFIG_MLX5_EN_ARFS=y | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_EN_MACSEC=y | ||||
| CONFIG_MLX5_EN_RXNFC=y | ||||
| CONFIG_MLX5_EN_TLS=y | ||||
| CONFIG_MLX5_ESWITCH=y | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_FPGA_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA_TLS is not set | ||||
| CONFIG_MLX5_FPGA=y | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| CONFIG_MLX5_IPSEC=y | ||||
| CONFIG_MLX5_MACSEC=y | ||||
|  | ||||
| @ -1870,7 +1870,8 @@ CONFIG_DPOT_DAC=m | ||||
| CONFIG_DRAGONRISE_FF=y | ||||
| # CONFIG_DRBD_FAULT_INJECTION is not set | ||||
| CONFIG_DRIVER_PE_KUNIT_TEST=m | ||||
| # CONFIG_DRM_ACCEL is not set | ||||
| CONFIG_DRM_ACCEL_QAIC=m | ||||
| CONFIG_DRM_ACCEL=y | ||||
| CONFIG_DRM_AMD_ACP=y | ||||
| CONFIG_DRM_AMD_DC_HDCP=y | ||||
| CONFIG_DRM_AMD_DC_SI=y | ||||
| @ -4443,19 +4444,22 @@ CONFIG_MLX4_DEBUG=y | ||||
| CONFIG_MLX4_EN_DCB=y | ||||
| CONFIG_MLX4_EN=m | ||||
| CONFIG_MLX4_INFINIBAND=m | ||||
| CONFIG_MLX5_ACCEL=y | ||||
| CONFIG_MLX5_CLS_ACT=y | ||||
| CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| # CONFIG_MLX5_DPLL is not set | ||||
| CONFIG_MLX5_DPLL=m | ||||
| CONFIG_MLX5_EN_ARFS=y | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_EN_MACSEC=y | ||||
| CONFIG_MLX5_EN_RXNFC=y | ||||
| CONFIG_MLX5_EN_TLS=y | ||||
| CONFIG_MLX5_ESWITCH=y | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_FPGA_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA_TLS is not set | ||||
| CONFIG_MLX5_FPGA=y | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| CONFIG_MLX5_IPSEC=y | ||||
| CONFIG_MLX5_MACSEC=y | ||||
|  | ||||
| @ -1448,7 +1448,8 @@ CONFIG_DPOT_DAC=m | ||||
| CONFIG_DRAGONRISE_FF=y | ||||
| CONFIG_DRBD_FAULT_INJECTION=y | ||||
| CONFIG_DRIVER_PE_KUNIT_TEST=m | ||||
| # CONFIG_DRM_ACCEL is not set | ||||
| # CONFIG_DRM_ACCEL_QAIC is not set | ||||
| CONFIG_DRM_ACCEL=y | ||||
| CONFIG_DRM_AMD_ACP=y | ||||
| CONFIG_DRM_AMD_DC_HDCP=y | ||||
| CONFIG_DRM_AMD_DC_SI=y | ||||
| @ -3736,19 +3737,22 @@ CONFIG_MLX4_DEBUG=y | ||||
| CONFIG_MLX4_EN_DCB=y | ||||
| CONFIG_MLX4_EN=m | ||||
| CONFIG_MLX4_INFINIBAND=m | ||||
| CONFIG_MLX5_ACCEL=y | ||||
| CONFIG_MLX5_CLS_ACT=y | ||||
| CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| # CONFIG_MLX5_DPLL is not set | ||||
| CONFIG_MLX5_DPLL=m | ||||
| CONFIG_MLX5_EN_ARFS=y | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_EN_MACSEC=y | ||||
| CONFIG_MLX5_EN_RXNFC=y | ||||
| CONFIG_MLX5_EN_TLS=y | ||||
| CONFIG_MLX5_ESWITCH=y | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_FPGA_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA_TLS is not set | ||||
| CONFIG_MLX5_FPGA=y | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| CONFIG_MLX5_IPSEC=y | ||||
| CONFIG_MLX5_MACSEC=y | ||||
|  | ||||
| @ -1437,7 +1437,8 @@ CONFIG_DPOT_DAC=m | ||||
| CONFIG_DRAGONRISE_FF=y | ||||
| # CONFIG_DRBD_FAULT_INJECTION is not set | ||||
| CONFIG_DRIVER_PE_KUNIT_TEST=m | ||||
| # CONFIG_DRM_ACCEL is not set | ||||
| # CONFIG_DRM_ACCEL_QAIC is not set | ||||
| CONFIG_DRM_ACCEL=y | ||||
| CONFIG_DRM_AMD_ACP=y | ||||
| CONFIG_DRM_AMD_DC_HDCP=y | ||||
| CONFIG_DRM_AMD_DC_SI=y | ||||
| @ -3709,19 +3710,22 @@ CONFIG_MLX4_DEBUG=y | ||||
| CONFIG_MLX4_EN_DCB=y | ||||
| CONFIG_MLX4_EN=m | ||||
| CONFIG_MLX4_INFINIBAND=m | ||||
| CONFIG_MLX5_ACCEL=y | ||||
| CONFIG_MLX5_CLS_ACT=y | ||||
| CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| # CONFIG_MLX5_DPLL is not set | ||||
| CONFIG_MLX5_DPLL=m | ||||
| CONFIG_MLX5_EN_ARFS=y | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_EN_MACSEC=y | ||||
| CONFIG_MLX5_EN_RXNFC=y | ||||
| CONFIG_MLX5_EN_TLS=y | ||||
| CONFIG_MLX5_ESWITCH=y | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_FPGA_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA_TLS is not set | ||||
| CONFIG_MLX5_FPGA=y | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| CONFIG_MLX5_IPSEC=y | ||||
| CONFIG_MLX5_MACSEC=y | ||||
|  | ||||
| @ -1453,7 +1453,8 @@ CONFIG_DPOT_DAC=m | ||||
| CONFIG_DRAGONRISE_FF=y | ||||
| CONFIG_DRBD_FAULT_INJECTION=y | ||||
| CONFIG_DRIVER_PE_KUNIT_TEST=m | ||||
| # CONFIG_DRM_ACCEL is not set | ||||
| # CONFIG_DRM_ACCEL_QAIC is not set | ||||
| CONFIG_DRM_ACCEL=y | ||||
| CONFIG_DRM_AMD_ACP=y | ||||
| CONFIG_DRM_AMD_DC_HDCP=y | ||||
| CONFIG_DRM_AMD_DC_SI=y | ||||
| @ -3708,19 +3709,22 @@ CONFIG_MLX4_DEBUG=y | ||||
| CONFIG_MLX4_EN_DCB=y | ||||
| CONFIG_MLX4_EN=m | ||||
| CONFIG_MLX4_INFINIBAND=m | ||||
| CONFIG_MLX5_ACCEL=y | ||||
| CONFIG_MLX5_CLS_ACT=y | ||||
| CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| # CONFIG_MLX5_DPLL is not set | ||||
| CONFIG_MLX5_DPLL=m | ||||
| CONFIG_MLX5_EN_ARFS=y | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_EN_MACSEC=y | ||||
| CONFIG_MLX5_EN_RXNFC=y | ||||
| CONFIG_MLX5_EN_TLS=y | ||||
| CONFIG_MLX5_ESWITCH=y | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_FPGA_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA_TLS is not set | ||||
| CONFIG_MLX5_FPGA=y | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| CONFIG_MLX5_IPSEC=y | ||||
| CONFIG_MLX5_MACSEC=y | ||||
|  | ||||
| @ -1442,7 +1442,8 @@ CONFIG_DPOT_DAC=m | ||||
| CONFIG_DRAGONRISE_FF=y | ||||
| # CONFIG_DRBD_FAULT_INJECTION is not set | ||||
| CONFIG_DRIVER_PE_KUNIT_TEST=m | ||||
| # CONFIG_DRM_ACCEL is not set | ||||
| # CONFIG_DRM_ACCEL_QAIC is not set | ||||
| CONFIG_DRM_ACCEL=y | ||||
| CONFIG_DRM_AMD_ACP=y | ||||
| CONFIG_DRM_AMD_DC_HDCP=y | ||||
| CONFIG_DRM_AMD_DC_SI=y | ||||
| @ -3681,19 +3682,22 @@ CONFIG_MLX4_DEBUG=y | ||||
| CONFIG_MLX4_EN_DCB=y | ||||
| CONFIG_MLX4_EN=m | ||||
| CONFIG_MLX4_INFINIBAND=m | ||||
| CONFIG_MLX5_ACCEL=y | ||||
| CONFIG_MLX5_CLS_ACT=y | ||||
| CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| # CONFIG_MLX5_DPLL is not set | ||||
| CONFIG_MLX5_DPLL=m | ||||
| CONFIG_MLX5_EN_ARFS=y | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_EN_MACSEC=y | ||||
| CONFIG_MLX5_EN_RXNFC=y | ||||
| CONFIG_MLX5_EN_TLS=y | ||||
| CONFIG_MLX5_ESWITCH=y | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_FPGA_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA_TLS is not set | ||||
| CONFIG_MLX5_FPGA=y | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| CONFIG_MLX5_IPSEC=y | ||||
| CONFIG_MLX5_MACSEC=y | ||||
|  | ||||
| @ -1580,7 +1580,10 @@ CONFIG_DPTF_POWER=m | ||||
| CONFIG_DRAGONRISE_FF=y | ||||
| CONFIG_DRBD_FAULT_INJECTION=y | ||||
| CONFIG_DRIVER_PE_KUNIT_TEST=m | ||||
| # CONFIG_DRM_ACCEL is not set | ||||
| CONFIG_DRM_ACCEL_HABANALABS=m | ||||
| CONFIG_DRM_ACCEL_IVPU=m | ||||
| CONFIG_DRM_ACCEL_QAIC=m | ||||
| CONFIG_DRM_ACCEL=y | ||||
| CONFIG_DRM_AMD_ACP=y | ||||
| CONFIG_DRM_AMD_DC_HDCP=y | ||||
| CONFIG_DRM_AMD_DC_SI=y | ||||
| @ -4056,19 +4059,22 @@ CONFIG_MLX4_DEBUG=y | ||||
| CONFIG_MLX4_EN_DCB=y | ||||
| CONFIG_MLX4_EN=m | ||||
| CONFIG_MLX4_INFINIBAND=m | ||||
| CONFIG_MLX5_ACCEL=y | ||||
| CONFIG_MLX5_CLS_ACT=y | ||||
| CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| # CONFIG_MLX5_DPLL is not set | ||||
| CONFIG_MLX5_DPLL=m | ||||
| CONFIG_MLX5_EN_ARFS=y | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_EN_MACSEC=y | ||||
| CONFIG_MLX5_EN_RXNFC=y | ||||
| CONFIG_MLX5_EN_TLS=y | ||||
| CONFIG_MLX5_ESWITCH=y | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_FPGA_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA_TLS is not set | ||||
| CONFIG_MLX5_FPGA=y | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| CONFIG_MLX5_IPSEC=y | ||||
| CONFIG_MLX5_MACSEC=y | ||||
|  | ||||
| @ -1569,7 +1569,10 @@ CONFIG_DPTF_POWER=m | ||||
| CONFIG_DRAGONRISE_FF=y | ||||
| # CONFIG_DRBD_FAULT_INJECTION is not set | ||||
| CONFIG_DRIVER_PE_KUNIT_TEST=m | ||||
| # CONFIG_DRM_ACCEL is not set | ||||
| CONFIG_DRM_ACCEL_HABANALABS=m | ||||
| CONFIG_DRM_ACCEL_IVPU=m | ||||
| CONFIG_DRM_ACCEL_QAIC=m | ||||
| CONFIG_DRM_ACCEL=y | ||||
| CONFIG_DRM_AMD_ACP=y | ||||
| CONFIG_DRM_AMD_DC_HDCP=y | ||||
| CONFIG_DRM_AMD_DC_SI=y | ||||
| @ -4030,19 +4033,22 @@ CONFIG_MLX4_DEBUG=y | ||||
| CONFIG_MLX4_EN_DCB=y | ||||
| CONFIG_MLX4_EN=m | ||||
| CONFIG_MLX4_INFINIBAND=m | ||||
| CONFIG_MLX5_ACCEL=y | ||||
| CONFIG_MLX5_CLS_ACT=y | ||||
| CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| # CONFIG_MLX5_DPLL is not set | ||||
| CONFIG_MLX5_DPLL=m | ||||
| CONFIG_MLX5_EN_ARFS=y | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_EN_MACSEC=y | ||||
| CONFIG_MLX5_EN_RXNFC=y | ||||
| CONFIG_MLX5_EN_TLS=y | ||||
| CONFIG_MLX5_ESWITCH=y | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_FPGA_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA_TLS is not set | ||||
| CONFIG_MLX5_FPGA=y | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| CONFIG_MLX5_IPSEC=y | ||||
| CONFIG_MLX5_MACSEC=y | ||||
|  | ||||
							
								
								
									
										11
									
								
								kernel.spec
									
									
									
									
									
								
							
							
						
						
									
										11
									
								
								kernel.spec
									
									
									
									
									
								
							| @ -163,13 +163,13 @@ Summary: The Linux kernel | ||||
| %define specrpmversion 6.7.0 | ||||
| %define specversion 6.7.0 | ||||
| %define patchversion 6.7 | ||||
| %define pkgrelease 0.rc5.20231212git26aff849438c.42 | ||||
| %define pkgrelease 0.rc5.20231213git88035e5694a8.43 | ||||
| %define kversion 6 | ||||
| %define tarfile_release 6.7-rc5-14-g26aff849438c | ||||
| %define tarfile_release 6.7-rc5-42-g88035e5694a8 | ||||
| # This is needed to do merge window version magic | ||||
| %define patchlevel 7 | ||||
| # This allows pkg_release to have configurable %%{?dist} tag | ||||
| %define specrelease 0.rc5.20231212git26aff849438c.42%{?buildid}%{?dist} | ||||
| %define specrelease 0.rc5.20231213git88035e5694a8.43%{?buildid}%{?dist} | ||||
| # This defines the kabi tarball version | ||||
| %define kabiversion 6.7.0 | ||||
| 
 | ||||
| @ -3754,6 +3754,11 @@ fi\ | ||||
| # | ||||
| # | ||||
| %changelog | ||||
| * Wed Dec 13 2023 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.7.0-0.rc5.88035e5694a8.43] | ||||
| - Some Fedora config updates for MLX5 (Justin M. Forbes) | ||||
| - Turn on DRM_ACCEL drivers for Fedora (Justin M. Forbes) | ||||
| - Linux v6.7.0-0.rc5.88035e5694a8 | ||||
| 
 | ||||
| * Tue Dec 12 2023 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.7.0-0.rc5.26aff849438c.42] | ||||
| - redhat: enable the kfence test (Nico Pache) | ||||
| - Linux v6.7.0-0.rc5.26aff849438c | ||||
|  | ||||
							
								
								
									
										6
									
								
								sources
									
									
									
									
									
								
							
							
						
						
									
										6
									
								
								sources
									
									
									
									
									
								
							| @ -1,5 +1,5 @@ | ||||
| SHA512 (kernel-abi-stablelists-6.6.0.tar.bz2) = 4f917598056dee5e23814621ec96ff2e4a411c8c4ba9d56ecb01b23cb96431825bedbecfcbaac9338efbf5cb21694d85497fa0bf43e7c80d9cd10bc6dd144dbd | ||||
| SHA512 (kernel-kabi-dw-6.6.0.tar.bz2) = 19308cd976031d05e18ef7f5d093218acdb89446418bab0cd956ff12cf66369915b9e64bb66fa9f20939428a60e81884fec5be3529c6c7461738d6540d3cc5c6 | ||||
| SHA512 (linux-6.7-rc5-14-g26aff849438c.tar.xz) = d55ba052d6955450b17f29c33727a927df1c52b62705e0d080637cf385b6742be4c74e3437f240ba0eeb6d622a1728ef612f61dd5d3891d5f223fa057601daec | ||||
| SHA512 (kernel-abi-stablelists-6.7.0.tar.xz) = 85bd0c37af8ec9afe7f6a521bd4bfff75df1390ae0e043c8c38f07ec0690efff3f785bf6291a334b58d74677cdff52bb73f7dcb7b14cef445b6b4d97c94c5dbe | ||||
| SHA512 (kernel-kabi-dw-6.7.0.tar.xz) = 500a21354926ad105cc6b32db608a9c2b96fd55b3dc06e6c871d3ff2c35a377b0d8fc91c6151db04113c77984d5d4a4131ae63bee466b55f221516f6c03f6743 | ||||
| SHA512 (linux-6.7-rc5-42-g88035e5694a8.tar.xz) = d667c83b0fad651003b8f7e0f3af8fc3f0051d261df36af4458b83b5bd236a1766a97010636ffbf04a3c27a2333094ea849e4430b57766de79f7e905e826315b | ||||
| SHA512 (kernel-abi-stablelists-6.7.0.tar.xz) = be718917acf6d7a0d4de3b2b66e18c885980cfad0dcaee800133c94c65eea2ea287cac4db921919a9e65ce6814b1141dd674a7e1a06afd34bdb0fb9087a3505c | ||||
| SHA512 (kernel-kabi-dw-6.7.0.tar.xz) = aa6509a6da7f613f639f5a30b6d6e4d0a9d5c87c92b685020e5d9c903c6135eb27e1d37d11f8a136c1036d71c32209b5b7d715df1d6bdbab52dcc534aea8c4b3 | ||||
|  | ||||
		Loading…
	
		Reference in New Issue
	
	Block a user